plugins/wimax/msg_reg_req.c

   1 /* msg_reg_req.c
   2  * WiMax MAC Management REG-REQ Message decoder
   3  *
   4  * Copyright (c) 2007 by Intel Corporation.
   5  *
   6  * Author: John R. Underwood <junderx@yahoo.com>
   7  *
   8  * $Id$
   9  *
  10  * Wireshark - Network traffic analyzer
  11  * By Gerald Combs <gerald@wireshark.org>
  12  * Copyright 1999 Gerald Combs
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  27  */
  28
  29 /* Include files */
  30
  31 #include "config.h"
  32
  33 #define WIMAX_16E_2005
  34
  35 #include <glib.h>
  36 #include <epan/packet.h>
  37 #include "crc.h"
  38 #include "wimax_tlv.h"
  39 #include "wimax_mac.h"
  40 #include "wimax_utils.h"
  41
  42 extern gboolean include_cor2_changes;
  43
  44 void proto_register_mac_mgmt_msg_reg_req(void);
  45 void proto_reg_handoff_mac_mgmt_msg_reg_req(void);
  46
  47 static gint proto_mac_mgmt_msg_reg_req_decoder = -1;
  48 static gint ett_mac_mgmt_msg_reg_req_decoder = -1;
  49
  50 /* REG-REQ fields */
  51 static gint hf_reg_ss_mgmt_support                   = -1;
  52 static gint hf_reg_ip_mgmt_mode                      = -1;
  53 static gint hf_reg_ip_version                        = -1;
  54 static gint hf_reg_req_secondary_mgmt_cid            = -1;
  55 static gint hf_reg_ul_cids                           = -1;
  56 static gint hf_reg_max_classifiers                   = -1;
  57 static gint hf_reg_phs                               = -1;
  58 static gint hf_reg_arq                               = -1;
  59 static gint hf_reg_dsx_flow_control                  = -1;
  60 static gint hf_reg_mac_crc_support                   = -1;
  61 static gint hf_reg_mca_flow_control                  = -1;
  62 static gint hf_reg_mcast_polling_cids                = -1;
  63 static gint hf_reg_num_dl_trans_cid                  = -1;
  64 static gint hf_reg_mac_address                       = -1;
  65 static gint hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame      = -1;
  66 static gint hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame      = -1;
  67 static gint hf_reg_tlv_t_21_packing_support                        = -1;
  68 static gint hf_reg_tlv_t_22_mac_extended_rtps_support              = -1;
  69 static gint hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms = -1;
  70 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp     = -1;
  71 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4 = -1;
  72 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6   = -1;
  73 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6     = -1;
  74 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd     = -1;
  75 static gint hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable          = -1;
  76 static gint hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps = -1;
  77 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map = -1;
  78 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps       = -1;
  79 static gint hf_reg_tlv_t_27_handover_mdho_ul_multiple              = -1;
  80 static gint hf_reg_tlv_t_27_handover_reserved                      = -1;
  81 static gint hf_reg_tlv_t_29_ho_process_opt_ms_timer                = -1;
  82 static gint hf_reg_tlv_t_31_mobility_handover                      = -1;
  83 static gint hf_reg_tlv_t_31_mobility_sleep_mode                    = -1;
  84 static gint hf_reg_tlv_t_31_mobility_idle_mode                     = -1;
  85 static gint hf_reg_req_tlv_t_32_sleep_mode_recovery_time           = -1;
  86 static gint hf_ms_previous_ip_address_v4                           = -1;
  87 static gint hf_ms_previous_ip_address_v6                           = -1;
  88 static gint hf_idle_mode_timeout                                   = -1;
  89 static gint hf_reg_req_tlv_t_45_ms_periodic_ranging_timer          = -1;
  90 static gint hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry = -1;
  91 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry = -1;
  92 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry = -1;
  93 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack = -1;
  94 static gint hf_reg_tlv_t_40_arq_ack_type_reserved                  = -1;
  95 static gint hf_reg_tlv_t_41_ho_connections_param_processing_time   = -1;
  96 static gint hf_reg_tlv_t_42_ho_tek_processing_time                 = -1;
  97 static gint hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support = -1;
  98 static gint hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support = -1;
  99 static gint hf_reg_tlv_t_43_cqich_allocation_request_header_support = -1;
 100 static gint hf_reg_tlv_t_43_phy_channel_report_header_support      = -1;
 101 static gint hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support = -1;
 102 static gint hf_reg_tlv_t_43_sn_report_header_support               = -1;
 103 static gint hf_reg_tlv_t_43_feedback_header_support                = -1;
 104 static gint hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter = -1;
 105 static gint hf_reg_tlv_t_43_sdu_sn_parameter                       = -1;
 106 static gint hf_reg_tlv_t_43_dl_sleep_control_extended_subheader    = -1;
 107 static gint hf_reg_tlv_t_43_feedback_request_extended_subheader    = -1;
 108 static gint hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader  = -1;
 109 static gint hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader  = -1;
 110 static gint hf_reg_tlv_t_43_mini_feedback_extended_subheader       = -1;
 111 static gint hf_reg_tlv_t_43_sn_request_extended_subheader          = -1;
 112 static gint hf_reg_tlv_t_43_pdu_sn_short_extended_subheader        = -1;
 113 static gint hf_reg_tlv_t_43_pdu_sn_long_extended_subheader         = -1;
 114 static gint hf_reg_tlv_t_43_reserved                               = -1;
 115 static gint hf_reg_tlv_t_46_handover_indication_readiness_timer    = -1;
 116 static gint hf_reg_req_min_time_for_intra_fa                       = -1;
 117 static gint hf_reg_req_min_time_for_inter_fa                       = -1;
 118 static gint hf_reg_encap_atm_4                                     = -1;
 119 static gint hf_reg_encap_ipv4_4                                      = -1;
 120 static gint hf_reg_encap_ipv6_4                                      = -1;
 121 static gint hf_reg_encap_802_3_4                                     = -1;
 122 static gint hf_reg_encap_802_1q_4                                    = -1;
 123 static gint hf_reg_encap_ipv4_802_3_4                                = -1;
 124 static gint hf_reg_encap_ipv6_802_3_4                                = -1;
 125 static gint hf_reg_encap_ipv4_802_1q_4                               = -1;
 126 static gint hf_reg_encap_ipv6_802_1q_4                               = -1;
 127 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4  = -1;
 128 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4 = -1;
 129 static gint hf_reg_encap_packet_ip_rohc_header_compression_4         = -1;
 130 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_4        = -1;
 131 static gint hf_reg_encap_rsvd_4                                     = -1;
 132 static gint hf_reg_encap_atm_2                                     = -1;
 133 static gint hf_reg_encap_ipv4_2                                      = -1;
 134 static gint hf_reg_encap_ipv6_2                                      = -1;
 135 static gint hf_reg_encap_802_3_2                                     = -1;
 136 static gint hf_reg_encap_802_1q_2                                    = -1;
 137 static gint hf_reg_encap_ipv4_802_3_2                                = -1;
 138 static gint hf_reg_encap_ipv6_802_3_2                                = -1;
 139 static gint hf_reg_encap_ipv4_802_1q_2                               = -1;
 140 static gint hf_reg_encap_ipv6_802_1q_2                               = -1;
 141 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2  = -1;
 142 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2 = -1;
 143 static gint hf_reg_encap_packet_ip_rohc_header_compression_2         = -1;
 144 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_2        = -1;
 145 static gint hf_reg_encap_rsvd_2                                     = -1;
 146 static gint hf_tlv_type                                            = -1;
 147 static gint hf_reg_invalid_tlv                                     = -1;
 148 static gint hf_reg_power_saving_class_type_i                       = -1;
 149 static gint hf_reg_power_saving_class_type_ii                      = -1;
 150 static gint hf_reg_power_saving_class_type_iii                     = -1;
 151 static gint hf_reg_multi_active_power_saving_classes               = -1;
 152 static gint hf_reg_total_power_saving_class_instances              = -1;
 153 static gint hf_reg_power_saving_class_reserved                     = -1;
 154 static gint hf_reg_power_saving_class_capability                   = -1;
 155 static gint hf_reg_ip_phs_sdu_encap                                = -1;
 156 static gint hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn = -1;
 157 static gint hf_reg_tlv_t_27_handover_supported                     = -1;
 158 static gint hf_reg_tlv_t_31_mobility_features_supported            = -1;
 159 static gint hf_reg_tlv_t_40_arq_ack_type                           = -1;
 160 static gint hf_reg_tlv_t_43_mac_header_ext_header_support          = -1;
 161 static gint hf_reg_req_bs_switching_timer                          = -1;
 162
 163 /* STRING RESOURCES */
 164
 165 static const true_false_string tfs_reg_ip_mgmt_mode = {
 166     "IP-managed mode",
 167     "Unmanaged mode"
 168 };
 169
 170 static const true_false_string tfs_reg_ss_mgmt_support = {
 171     "secondary management connection",
 172     "no secondary management connection"
 173 };
 174
 175 #if 0
 176 static const true_false_string tfs_arq_enable = {
 177             "ARQ Requested/Accepted",
 178                 "ARQ Not Requested/Accepted"
 179 };
 180 #endif
 181
 182 #if 0
 183 static const true_false_string tfs_arq_deliver_in_order = {
 184             "Order of delivery is preserved",
 185                 "Order of delivery is not preserved"
 186 };
 187 #endif
 188
 189 static const true_false_string tfs_reg_fbss_mdho_ho_disable = {
 190     "Disable",
 191     "Enable"
 192 };
 193
 194 static const value_string vals_reg_ip_version[] = {
 195     {0x1,                               "IPv4"},
 196     {0x2,                               "IPV6"},
 197     {0,                                 NULL}
 198 };
 199
 200 static const value_string vals_reg_phs_support[] = {
 201     {0,                                 "no PHS support"},
 202     {1,                                 "ATM PHS"},
 203     {2,                                 "Packet PHS"},
 204     {3,                                 "ATM and Packet PHS"},
 205     {0,                                 NULL}
 206 };
 207
 208 static const true_false_string tfs_supported = {
 209     "supported",
 210     "unsupported"
 211 };
 212
 213 static const true_false_string tfs_mac_crc_support = {
 214     "MAC CRC Support (Default)",
 215     "No MAC CRC Support"
 216 };
 217
 218 static const value_string tfs_support[] = {
 219     {0,                                 "not supported"},
 220     {1,                                 "supported"},
 221     {0,                                 NULL}
 222 };
 223
 224 /* Decode REG-REQ sub-TLV's. */
 225 void dissect_extended_tlv(proto_tree *reg_req_tree, gint tlv_type, tvbuff_t *tvb, guint tlv_offset, guint tlv_len, packet_info *pinfo, guint offset, gint proto_registry)
 226 {
 227         proto_item *tlv_item;
 228         proto_tree *tlv_tree;
 229         guint tvb_len;
 230         tlv_info_t tlv_info;
 231         guint tlv_end;
 232         guint length;
 233         guint nblocks;
 234
 235         /* Get the tvb reported length */
 236         tvb_len =  tvb_reported_length(tvb);
 237
 238         /* get the TLV information */
 239         init_tlv_info(&tlv_info, tvb, offset);
 240
 241 #ifdef WIMAX_16E_2005
 242         switch (tlv_type) {
 243                 case REG_ARQ_PARAMETERS:
 244                         /* display ARQ Service Flow Encodings info */
 245                         /* add subtree */
 246                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, offset, tlv_len, "ARQ Service Flow Encodings");
 247                         /* decode and display the DL Service Flow Encodings */
 248                         wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
 249                         break;
 250                 case REG_SS_MGMT_SUPPORT:
 251                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ss_mgmt_support, tvb, offset, ENC_BIG_ENDIAN);
 252                         break;
 253                 case REG_IP_MGMT_MODE:
 254                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_mgmt_mode, tvb, offset, ENC_BIG_ENDIAN);
 255                         break;
 256                 case REG_IP_VERSION:
 257                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_version, tvb, offset, ENC_BIG_ENDIAN);
 258                         break;
 259                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
 260                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ul_cids, tvb, offset, ENC_BIG_ENDIAN);
 261                         break;
 262
 263                 case REG_POWER_SAVING_CLASS_CAPABILITY:
 264                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_power_saving_class_capability, tvb, offset, ENC_BIG_ENDIAN);
 265                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 266                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_i, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 267                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_ii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 268                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_iii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 269                         proto_tree_add_item(tlv_tree, hf_reg_multi_active_power_saving_classes, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 270                         proto_tree_add_item(tlv_tree, hf_reg_total_power_saving_class_instances, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 271                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_reserved, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 272                         break;
 273                 case REG_IP_PHS_SDU_ENCAP:
 274                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_phs_sdu_encap, tvb, offset, ENC_BIG_ENDIAN);
 275                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 276
 277 #ifdef WIMAX_16E_2005
 278                         if (tlv_len == 2){
 279                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 280                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 281                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 282                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 283                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 284                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 285                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 286                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 287                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 288                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 289                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 290                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 291                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 292                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 293                         } else if(tlv_len == 4){
 294                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 295                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 296                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 297                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 298                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 299                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 300                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 301                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 302                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 303                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 304                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 305                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 306                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 307                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 308                         }
 309 #endif
 310                         break;
 311                 case REG_MAX_CLASSIFIERS_SUPPORTED:
 312                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_max_classifiers, tvb, offset, ENC_BIG_ENDIAN);
 313                         break;
 314                 case REG_PHS_SUPPORT:
 315                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_phs, tvb, offset, ENC_BIG_ENDIAN);
 316                         break;
 317                 case REG_ARQ_SUPPORT:
 318                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_arq, tvb, offset, ENC_BIG_ENDIAN);
 319                         break;
 320                 case REG_DSX_FLOW_CONTROL:
 321                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_dsx_flow_control, tvb, offset, ENC_BIG_ENDIAN);
 322                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
 323                                 proto_item_append_text(tlv_item, " (no limit)");
 324                         }
 325                         break;
 326                 case REG_MAC_CRC_SUPPORT:
 327                         if (!include_cor2_changes) {
 328                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mac_crc_support, tvb, offset, ENC_NA);
 329                         } else {
 330                                 /* Unknown TLV Type */
 331                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_tlv_type, tvb, offset, ENC_NA);
 332                         }
 333                         break;
 334                 case REG_MCA_FLOW_CONTROL:
 335                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mca_flow_control, tvb, offset, ENC_BIG_ENDIAN);
 336                         if (tvb_get_guint8(tvb, tlv_offset) == 0) {
 337                                 proto_item_append_text(tlv_item, " (no limit)");
 338                         }
 339                         break;
 340                 case REG_MCAST_POLLING_CIDS:
 341                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mcast_polling_cids, tvb, offset, ENC_BIG_ENDIAN);
 342                         break;
 343                 case REG_NUM_DL_TRANS_CID:
 344                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_num_dl_trans_cid, tvb, offset, ENC_BIG_ENDIAN);
 345                         break;
 346                 case REG_MAC_ADDRESS:
 347                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mac_address, tvb, offset, ENC_NA);
 348                         break;
 349                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
 350                         /* display Maximum MAC level data per frame info */
 351                         /* add subtree */
 352                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, offset, tlv_len, "Maximum MAC level data per frame");
 353                         /* decode and display Maximum MAC level data per frame for UL & DL */
 354                         /* Set endpoint of the subTLVs (tlv_offset + length) */
 355                         tlv_end = tlv_offset + tlv_len;
 356                         /* process subTLVs */
 357                         while ( tlv_offset < tlv_end )
 358                         {       /* get the TLV information */
 359                                 init_tlv_info(&tlv_info, tvb, tlv_offset);
 360                                 /* get the TLV type */
 361                                 tlv_type = get_tlv_type(&tlv_info);
 362                                 /* get the TLV length */
 363                                 length = get_tlv_length(&tlv_info);
 364                                 if(tlv_type == -1 || length > MAX_TLV_LEN || length < 1)
 365                                 {       /* invalid tlv info */
 366                                         col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
 367                                         proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
 368                                         break;
 369                                 }
 370                                 /* update the offset */
 371                                 tlv_offset += get_tlv_value_offset(&tlv_info);
 372                                 nblocks = tvb_get_ntohs(tvb, tlv_offset);
 373                                 switch (tlv_type)
 374                                 {
 375                                         case REG_TLV_T_20_1_MAX_MAC_LEVEL_DATA_PER_DL_FRAME:
 376                                                 tlv_item = add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_BIG_ENDIAN);
 377                                                 if ( nblocks == 0 )
 378                                                 {
 379                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
 380                                                 } else {
 381                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
 382                                                 }
 383                                                 break;
 384                                         case REG_TLV_T_20_2_MAX_MAC_LEVEL_DATA_PER_UL_FRAME:
 385                                                 tlv_item = add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_BIG_ENDIAN);
 386                                                 if ( nblocks == 0 )
 387                                                 {
 388                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
 389                                                 } else {
 390                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
 391                                                 }
 392                                                 break;
 393                                         default:
 394                                                 add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_invalid_tlv, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_NA);
 395                                                 break;
 396                                 }
 397                                 tlv_offset += length;
 398                         }
 399                         break;
 400
 401                 case REG_TLV_T_21_PACKING_SUPPORT:
 402                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_21_packing_support, tvb, offset, ENC_BIG_ENDIAN);
 403                         break;
 404                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
 405                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, offset, ENC_BIG_ENDIAN);
 406                         break;
 407                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
 408                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, offset, ENC_BIG_ENDIAN);
 409                         break;
 410                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
 411                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn, tvb, offset, ENC_BIG_ENDIAN);
 412                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 413                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 414                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 415                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 416                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 417                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 418                         break;
 419                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
 420                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_27_handover_supported, tvb, offset, ENC_BIG_ENDIAN);
 421                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 422                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 423                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 424                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 425                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 426                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_ul_multiple, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 427                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 428                         break;
 429                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
 430                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, offset, ENC_BIG_ENDIAN);
 431                         break;
 432                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
 433                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_31_mobility_features_supported, tvb, offset, ENC_BIG_ENDIAN);
 434                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 435                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_handover, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 436                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_sleep_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 437                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_idle_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 438                         break;
 439                 case REG_TLV_T_40_ARQ_ACK_TYPE:
 440                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_40_arq_ack_type, tvb, offset, ENC_BIG_ENDIAN);
 441                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 442                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 443                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 444                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 445                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 446                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 447                         break;
 448                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
 449                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, offset, ENC_BIG_ENDIAN);
 450                         break;
 451                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
 452                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, offset, ENC_BIG_ENDIAN);
 453                         break;
 454                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
 455                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_43_mac_header_ext_header_support, tvb, offset, ENC_BIG_ENDIAN);
 456                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 457                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 458                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 459                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_cqich_allocation_request_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 460                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_phy_channel_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 461                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 462                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 463                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 464                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 465                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 466                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_dl_sleep_control_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 467                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 468                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 469                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 470                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mini_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 471                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 472                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_short_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 473                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_long_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 474                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_reserved, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 475                         break;
 476                 case REG_REQ_BS_SWITCHING_TIMER:
 477                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_bs_switching_timer, tvb, offset, ENC_BIG_ENDIAN);
 478                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 479                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_intra_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 480                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_inter_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 481                         break;
 482                 case VENDOR_SPECIFIC_INFO:
 483                 case VENDOR_ID_ENCODING:
 484                 case CURRENT_TX_POWER:
 485                 case MAC_VERSION_ENCODING:
 486                 case CMAC_TUPLE:        /* Table 348b */
 487                         wimax_common_tlv_encoding_decoder(tvb_new_subset_remaining(tvb, offset), pinfo, reg_req_tree);
 488                         break;
 489                 default:
 490                         add_tlv_subtree(&tlv_info, reg_req_tree, proto_registry, tvb, offset, ENC_NA);
 491                         break;
 492         }
 493 #endif
 494 }
 495
 496
 497 /* Decode REG-REQ messages. */
 498 static void dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree)
 499 {
 500         guint offset = 0;
 501         guint tlv_offset;
 502         guint tvb_len;
 503         proto_item *reg_req_item = NULL;
 504         proto_tree *reg_req_tree = NULL;
 505         proto_tree *tlv_tree = NULL;
 506         gboolean hmac_found = FALSE;
 507         tlv_info_t tlv_info;
 508         gint tlv_type;
 509         gint tlv_len;
 510
 511         {       /* we are being asked for details */
 512
 513                 /* Get the tvb reported length */
 514                 tvb_len =  tvb_reported_length(tvb);
 515                 /* display MAC payload type REG-REQ */
 516                 reg_req_item = proto_tree_add_protocol_format(tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tvb_len, "MAC Management Message, REG-REQ");
 517                 /* add MAC REG-REQ subtree */
 518                 reg_req_tree = proto_item_add_subtree(reg_req_item, ett_mac_mgmt_msg_reg_req_decoder);
 519
 520                 while(offset < tvb_len)
 521                 {
 522                         /* Get the TLV data. */
 523                         init_tlv_info(&tlv_info, tvb, offset);
 524                         /* get the TLV type */
 525                         tlv_type = get_tlv_type(&tlv_info);
 526                         /* get the TLV length */
 527                         tlv_len = get_tlv_length(&tlv_info);
 528                         if(tlv_type == -1 || tlv_len > MAX_TLV_LEN || tlv_len < 1)
 529                         {       /* invalid tlv info */
 530                                 col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
 531                                 proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
 532                                 break;
 533                         }
 534                         /* get the offset to the TLV data */
 535                         tlv_offset = offset + get_tlv_value_offset(&tlv_info);
 536
 537                         switch (tlv_type) {
 538                                 case REG_ARQ_PARAMETERS:
 539                                 case REG_SS_MGMT_SUPPORT:
 540                                 case REG_IP_MGMT_MODE:
 541                                 case REG_IP_VERSION:
 542                                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
 543                                 case REG_IP_PHS_SDU_ENCAP:
 544                                 case REG_MAX_CLASSIFIERS_SUPPORTED:
 545                                 case REG_PHS_SUPPORT:
 546                                 case REG_ARQ_SUPPORT:
 547                                 case REG_DSX_FLOW_CONTROL:
 548                                 case REG_MAC_CRC_SUPPORT:
 549                                 case REG_MCA_FLOW_CONTROL:
 550                                 case REG_MCAST_POLLING_CIDS:
 551                                 case REG_NUM_DL_TRANS_CID:
 552                                 case REG_MAC_ADDRESS:
 553 #ifdef WIMAX_16E_2005
 554                                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
 555                                 case REG_TLV_T_21_PACKING_SUPPORT:
 556                                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
 557                                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
 558                                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
 559                                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
 560                                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
 561                                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
 562                                 case REG_TLV_T_40_ARQ_ACK_TYPE:
 563                                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
 564                                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
 565                                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
 566                                 case REG_REQ_BS_SWITCHING_TIMER:
 567                                 case REG_POWER_SAVING_CLASS_CAPABILITY:
 568 #endif
 569                                         /* Decode REG-REQ sub-TLV's. */
 570                                         dissect_extended_tlv(reg_req_tree, tlv_type, tvb, tlv_offset, tlv_len, pinfo, offset, proto_mac_mgmt_msg_reg_req_decoder);
 571                                         break;
 572                                 case REG_REQ_SECONDARY_MGMT_CID:
 573                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_secondary_mgmt_cid, tvb, offset, ENC_BIG_ENDIAN);
 574                                         break;
 575                                 case REG_REQ_TLV_T_32_SLEEP_MODE_RECOVERY_TIME:
 576                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, offset, ENC_BIG_ENDIAN);
 577                                         break;
 578                                 case REG_REQ_TLV_T_33_MS_PREV_IP_ADDR:
 579                                         if ( tlv_len == 4 ) {
 580                                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_ms_previous_ip_address_v4, tvb, offset, ENC_BIG_ENDIAN);
 581                                         } else if ( tlv_len == 16 ) {
 582                                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_ms_previous_ip_address_v6, tvb, offset, ENC_NA);
 583                                         }
 584                                         break;
 585                                 case REG_TLV_T_37_IDLE_MODE_TIMEOUT:
 586                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_idle_mode_timeout, tvb, offset, ENC_BIG_ENDIAN);
 587                                         break;
 588                                 case REG_REQ_TLV_T_45_MS_PERIODIC_RANGING_TIMER_INFO:
 589                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, offset, ENC_BIG_ENDIAN);
 590                                         break;
 591                                 case REG_HANDOVER_INDICATION_READINESS_TIMER:
 592                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, offset, ENC_BIG_ENDIAN);
 593                                         break;
 594
 595                                 case DSx_UPLINK_FLOW:
 596                                         /* display Uplink Service Flow Encodings info */
 597                                         /* add subtree */
 598                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "Uplink Service Flow Encodings");
 599                                         /* decode and display the DL Service Flow Encodings */
 600                                         wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
 601                                         break;
 602                                 case DSx_DOWNLINK_FLOW:
 603                                         /* display Downlink Service Flow Encodings info */
 604                                         /* add subtree */
 605                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "Downlink Service Flow Encodings");
 606                                         /* decode and display the DL Service Flow Encodings */
 607                                         wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
 608                                         break;
 609                                 case HMAC_TUPLE:        /* Table 348d */
 610                                         /* decode and display the HMAC Tuple */
 611                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "HMAC Tuple");
 612                                         wimax_hmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
 613                                         hmac_found = TRUE;
 614                                         break;
 615                                 case CMAC_TUPLE:        /* Table 348b */
 616                                         /* decode and display the CMAC Tuple */
 617                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "CMAC Tuple");
 618                                         wimax_cmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
 619                                         break;
 620                                 default:
 621                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_tlv_type, tvb, offset, ENC_NA);
 622                                         break;
 623                         }
 624                         /* update the offset */
 625                         offset = tlv_len + tlv_offset;
 626                 } /* End while() looping through the tvb. */
 627                 if (!hmac_found)
 628                         proto_item_append_text(reg_req_tree, " (HMAC Tuple is missing !)");
 629         }
 630 }
 631
 632 /* Register Wimax Mac Payload Protocol and Dissector */
 633 void proto_register_mac_mgmt_msg_reg_req(void)
 634 {
 635         /* REG-REQ fields display */
 636         static hf_register_info hf[] =
 637         {
 638                 {
 639                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp,
 640                         {
 641                                 "DHCP", "wmx.reg.alloc_sec_mgmt_dhcp",
 642                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
 643                         }
 644                 },
 645                 {
 646                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6,
 647                         {
 648                                 "DHCPv6", "wmx.reg.alloc_sec_mgmt_dhcpv6",
 649                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
 650                         }
 651                 },
 652                 {
 653                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6,
 654                         {
 655                                 "IPv6 Stateless Address Autoconfiguration", "wmx.reg.alloc_sec_mgmt_ipv6",
 656                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
 657                         }
 658                 },
 659                 {
 660                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4,
 661                         {
 662                                 "Mobile IPv4", "wmx.reg.alloc_sec_mgmt_mobile_ipv4",
 663                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
 664                         }
 665                 },
 666                 {
 667                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd,
 668                         {
 669                                 "Reserved", "wmx.reg.alloc_sec_mgmt_rsvd",
 670                                 FT_UINT8, BASE_DEC, NULL, 0xF0, NULL, HFILL
 671                         }
 672                 },
 673                 {
 674                         &hf_reg_arq,
 675                         {
 676                                 "ARQ support", "wmx.reg.arq",
 677                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_supported), 0x0, NULL, HFILL
 678                         }
 679                 },
 680                 {
 681                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry,
 682                         {
 683                                 "Cumulative ACK entry", "wmx.reg.arq_ack_type_cumulative_ack_entry",
 684                                 FT_UINT8, BASE_DEC, NULL, 0x2, NULL, HFILL
 685                         }
 686                 },
 687                 {
 688                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack,
 689                         {
 690                                 "Cumulative ACK with Block Sequence ACK", "wmx.reg.arq_ack_type_cumulative_ack_with_block_sequence_ack",
 691                                 FT_UINT8, BASE_DEC, NULL, 0x8, NULL, HFILL
 692                         }
 693                 },
 694                 {
 695                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry,
 696                         {
 697                                 "Cumulative with Selective ACK entry", "wmx.reg.arq_ack_type_cumulative_with_selective_ack_entry",
 698                                 FT_UINT8, BASE_DEC, NULL, 0x4, NULL, HFILL
 699                         }
 700                 },
 701                 {
 702                         &hf_reg_tlv_t_40_arq_ack_type_reserved,
 703                         {
 704                                 "Reserved", "wmx.reg.arq_ack_type_reserved",
 705                                 FT_UINT8, BASE_DEC, NULL, 0xf0, NULL, HFILL
 706                         }
 707                 },
 708                 {
 709                         &hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry,
 710                         {
 711                                 "Selective ACK entry", "wmx.reg.arq_ack_type_selective_ack_entry",
 712                                 FT_UINT8, BASE_DEC, NULL, 0x1, NULL, HFILL
 713                         }
 714                 },
 715                 {
 716                         &hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support,
 717                         {
 718                                 "Bandwidth request and CINR report header support", "wmx.reg.bandwidth_request_cinr_report_header_support",
 719                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2, NULL, HFILL
 720                         }
 721                 },
 722                 {
 723                         &hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support,
 724                         {
 725                                 "Bandwidth request and uplink sleep control header support", "wmx.reg.bandwidth_request_ul_sleep_control_header_support",
 726                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10, NULL, HFILL
 727                         }
 728                 },
 729                 {
 730                         &hf_reg_tlv_t_43_cqich_allocation_request_header_support,
 731                         {
 732                                 "CQICH Allocation Request header support", "wmx.reg.cqich_allocation_request_header_support",
 733                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4, NULL, HFILL
 734                         }
 735                 },
 736                 {
 737                         &hf_reg_tlv_t_43_dl_sleep_control_extended_subheader,
 738                         {
 739                                 "Downlink sleep control extended subheader", "wmx.reg.dl_sleep_control_extended_subheader",
 740                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x800, NULL, HFILL
 741                         }
 742                 },
 743                 {
 744                         &hf_reg_dsx_flow_control,
 745                         {
 746                                 "DSx flow control", "wmx.reg.dsx_flow_control",
 747                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
 748                         }
 749                 },
 750                 /* When REG-REQ TLV 7 is length 2 */
 751                 {
 752                         &hf_reg_encap_802_1q_2,
 753                         {
 754                                 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 755                                 FT_UINT16, BASE_HEX, NULL, 0x0010, NULL, HFILL
 756                         }
 757                 },
 758                 {
 759                         &hf_reg_encap_802_3_2,
 760                         {
 761                                 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 762                                 FT_UINT16, BASE_HEX, NULL, 0x00000008, NULL, HFILL
 763                         }
 764                 },
 765                 {
 766                         &hf_reg_encap_atm_2,
 767                         {
 768                                 "ATM", "wmx.reg.encap_atm",
 769                                 FT_UINT16, BASE_HEX, NULL, 0x00000001, NULL, HFILL
 770                         }
 771                 },
 772                 {
 773                         &hf_reg_encap_ipv4_2,
 774                         {
 775                                 "Packet, IPv4", "wmx.reg.encap_ipv4",
 776                                 FT_UINT16, BASE_HEX, NULL, 0x00000002, NULL, HFILL
 777                         }
 778                 },
 779                 {
 780                         &hf_reg_encap_ipv6_2,
 781                         {
 782                                 "Packet, IPv6", "wmx.reg.encap_ipv6",
 783                                 FT_UINT16, BASE_HEX, NULL, 0x00000004, NULL, HFILL
 784                         }
 785                 },
 786                 {
 787                         &hf_reg_encap_ipv4_802_1q_2,
 788                         {
 789                                 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 790                                 FT_UINT16, BASE_HEX, NULL, 0x00000080, NULL, HFILL
 791                         }
 792                 },
 793                 {
 794                         &hf_reg_encap_ipv4_802_3_2,
 795                         {
 796                                 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 797                                 FT_UINT16, BASE_HEX, NULL, 0x00000020, NULL, HFILL
 798                         }
 799                 },
 800                 {
 801                         &hf_reg_encap_ipv6_802_1q_2,
 802                         {
 803                                 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 804                                 FT_UINT16, BASE_HEX, NULL, 0x00000100, NULL, HFILL
 805                         }
 806                 },
 807                 {
 808                         &hf_reg_encap_ipv6_802_3_2,
 809                         {
 810                                 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 811                                 FT_UINT16, BASE_HEX, NULL, 0x00000040, NULL, HFILL
 812                         }
 813                 },
 814                 {
 815                         &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2,
 816                         {
 817                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 818                                 FT_UINT16, BASE_HEX, NULL, 0x00000400, NULL, HFILL
 819                         }
 820                 },
 821                 {
 822                         &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2,
 823                         {
 824                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 825                                 FT_UINT16, BASE_HEX, NULL, 0x00000200, NULL, HFILL
 826                         }
 827                 },
 828                 {
 829                         &hf_reg_encap_packet_ip_ecrtp_header_compression_2,
 830                         {
 831                                 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 832                                 FT_UINT16, BASE_HEX, NULL, 0x00001000, NULL, HFILL
 833                         }
 834                 },
 835                 {
 836                         &hf_reg_encap_packet_ip_rohc_header_compression_2,
 837                         {
 838                                 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 839                                 FT_UINT16, BASE_HEX, NULL, 0x00000800, NULL, HFILL
 840                         }
 841                 },
 842                 {
 843                         &hf_reg_encap_rsvd_2,
 844                         {
 845                                 "Reserved", "wmx.reg.encap_rsvd",
 846                                 FT_UINT16, BASE_HEX, NULL, 0x0000E000, NULL, HFILL
 847                         }
 848                 },
 849                 /* When REG-REQ TLV 7 is length 4 */
 850                 {
 851                         &hf_reg_encap_802_1q_4,
 852                         {
 853                                 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 854                                 FT_UINT32, BASE_HEX, NULL, 0x0010, NULL, HFILL
 855                         }
 856                 },
 857                 {
 858                         &hf_reg_encap_802_3_4,
 859                         {
 860                                 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 861                                 FT_UINT32, BASE_HEX, NULL, 0x00000008, NULL, HFILL
 862                         }
 863                 },
 864                 {
 865                         &hf_reg_encap_atm_4,
 866                         {
 867                                 "ATM", "wmx.reg.encap_atm",
 868                                 FT_UINT32, BASE_HEX, NULL, 0x00000001, NULL, HFILL
 869                         }
 870                 },
 871                 {
 872                         &hf_reg_encap_ipv4_4,
 873                         {
 874                                 "Packet, IPv4", "wmx.reg.encap_ipv4",
 875                                 FT_UINT32, BASE_HEX, NULL, 0x00000002, NULL, HFILL
 876                         }
 877                 },
 878                 {
 879                         &hf_reg_encap_ipv4_802_1q_4,
 880                         {
 881                                 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 882                                 FT_UINT32, BASE_HEX, NULL, 0x00000080, NULL, HFILL
 883                         }
 884                 },
 885                 {
 886                         &hf_reg_encap_ipv4_802_3_4,
 887                         {
 888                                 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 889                                 FT_UINT32, BASE_HEX, NULL, 0x00000020, NULL, HFILL
 890                         }
 891                 },
 892                 {
 893                         &hf_reg_encap_ipv6_4,
 894                         {
 895                                 "Packet, IPv6", "wmx.reg.encap_ipv6",
 896                                 FT_UINT32, BASE_HEX, NULL, 0x00000004, NULL, HFILL
 897                         }
 898                 },
 899                 {
 900                         &hf_reg_encap_ipv6_802_1q_4,
 901                         {
 902                                 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 903                                 FT_UINT32, BASE_HEX, NULL, 0x00000100, NULL, HFILL
 904                         }
 905                 },
 906                 {
 907                         &hf_reg_encap_ipv6_802_3_4,
 908                         {
 909                                 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 910                                 FT_UINT32, BASE_HEX, NULL, 0x00000040, NULL, HFILL
 911                         }
 912                 },
 913                 {
 914                         &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4,
 915                         {
 916                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 917                                 FT_UINT32, BASE_HEX, NULL, 0x00000400, NULL, HFILL
 918                         }
 919                 },
 920                 {
 921                         &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4,
 922                         {
 923                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 924                                 FT_UINT32, BASE_HEX, NULL, 0x00000200, NULL, HFILL
 925                         }
 926                 },
 927                 {
 928                         &hf_reg_encap_packet_ip_ecrtp_header_compression_4,
 929                         {
 930                                 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 931                                 FT_UINT32, BASE_HEX, NULL, 0x00001000, NULL, HFILL
 932                         }
 933                 },
 934                 {
 935                         &hf_reg_encap_packet_ip_rohc_header_compression_4,
 936                         {
 937                                 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 938                                 FT_UINT32, BASE_HEX, NULL, 0x00000800, NULL, HFILL
 939                         }
 940                 },
 941                 {
 942                         &hf_reg_encap_rsvd_4,
 943                         {
 944                                 "Reserved", "wmx.reg.encap_rsvd",
 945                                 FT_UINT32, BASE_HEX, NULL, 0xFFFFE000, NULL, HFILL
 946                         }
 947                 },
 948                 {
 949                         &hf_reg_tlv_t_22_mac_extended_rtps_support,
 950                         {
 951                                 "MAC extended rtPS support", "wmx.reg.ext_rtps_support",
 952                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
 953                         }
 954                 },
 955                 {
 956                         &hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps,
 957                         {
 958                                 "FBSS/MDHO DL RF Combining with monitoring MAPs from active BSs", "wmx.reg.fbss_mdho_dl_rf_combining",
 959                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
 960                         }
 961                 },
 962                 {
 963                         &hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support,
 964                         {
 965                                 "Bandwidth request and UL Tx Power Report header support",
 966                                 "wimax.reg.bandwidth_request_ul_tx_pwr_report_header_support",
 967                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1, NULL, HFILL
 968                         }
 969                 },
 970                 {
 971                         &hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable,
 972                         {
 973                                 "MDHO/FBSS HO. BS ignore all other bits when set to 1", "wmx.reg.fbss_mdho_ho_disable",
 974                                 FT_BOOLEAN, 8, TFS(&tfs_reg_fbss_mdho_ho_disable), 0x01, NULL, HFILL
 975                         }
 976                 },
 977                 {
 978                         &hf_reg_tlv_t_43_feedback_header_support,
 979                         {
 980                                 "Feedback header support", "wmx.reg.feedback_header_support",
 981                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40, NULL, HFILL
 982                         }
 983                 },
 984                 {
 985                         &hf_reg_tlv_t_43_feedback_request_extended_subheader,
 986                         {
 987                                 "Feedback request extended subheader", "wmx.reg.feedback_request_extended_subheader",
 988                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1000, NULL, HFILL
 989                         }
 990                 },
 991                 {
 992                         &hf_reg_tlv_t_46_handover_indication_readiness_timer,
 993                         {
 994                                 "Handover indication readiness timer", "wmx.reg.handover_indication_readiness_timer",
 995                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
 996                         }
 997                 },
 998                 {
 999                         &hf_reg_tlv_t_27_handover_reserved,
1000                         {
1001                                 "Reserved", "wmx.reg.handover_reserved",
1002                                 FT_UINT8, BASE_DEC, NULL, 0xE0, NULL, HFILL
1003                         }
1004                 },
1005                 {
1006                         &hf_reg_tlv_t_41_ho_connections_param_processing_time,
1007                         {
1008                                 "MS HO connections parameters processing time", "wmx.reg.ho_connections_param_processing_time",
1009                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1010                         }
1011                 },
1012                 {
1013                         &hf_reg_tlv_t_29_ho_process_opt_ms_timer,
1014                         {
1015                                 "HO Process Optimization MS Timer", "wmx.reg.ho_process_opt_ms_timer",
1016                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1017                         }
1018                 },
1019                 {
1020                         &hf_reg_tlv_t_42_ho_tek_processing_time,
1021                         {
1022                                 "MS HO TEK processing time", "wmx.reg.ho_tek_processing_time",
1023                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1024                         }
1025                 },
1026                 {
1027                         &hf_idle_mode_timeout,
1028                         {
1029                                 "Idle Mode Timeout", "wmx.reg.idle_mode_timeout",
1030                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1031                         }
1032                 },
1033                 {
1034                         &hf_reg_ip_mgmt_mode,
1035                         {
1036                                 "IP management mode", "wmx.reg.ip_mgmt_mode",
1037                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ip_mgmt_mode), 0x0, NULL, HFILL
1038                         }
1039                 },
1040                 {
1041                         &hf_reg_ip_version,
1042                         {
1043                                 "IP version", "wmx.reg.ip_version",
1044                                 FT_UINT8, BASE_HEX, VALS(vals_reg_ip_version), 0x0, NULL, HFILL
1045                         }
1046                 },
1047                 {
1048                         &hf_reg_mac_address,
1049                         {
1050                                 "MAC Address of the SS", "wmx.reg.mac_address",
1051                                 FT_ETHER, BASE_NONE, NULL, 0x0, NULL, HFILL
1052                         }
1053                 },
1054                 {
1055                         &hf_reg_mac_crc_support,
1056                         {
1057                                 "MAC CRC", "wmx.reg.mac_crc_support",
1058                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_mac_crc_support), 0x0, NULL, HFILL
1059                         }
1060                 },
1061                 {
1062                         &hf_reg_max_classifiers,
1063                         {
1064                                 "Maximum number of classification rules", "wmx.reg.max_classifiers",
1065                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1066                         }
1067                 },
1068                 {
1069                         &hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms,
1070                         {
1071                                 "Maximum number of bursts transmitted concurrently to the MS", "wmx.reg.max_num_bursts_to_ms",
1072                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1073                         }
1074                 },
1075                 {
1076                         &hf_reg_mca_flow_control,
1077                         {
1078                                 "MCA flow control", "wmx.reg.mca_flow_control",
1079                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1080                         }
1081                 },
1082                 {
1083                         &hf_reg_mcast_polling_cids,
1084                         {
1085                                 "Multicast polling group CID support", "wmx.reg.mcast_polling_cids",
1086                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1087                         }
1088                 },
1089                 {
1090                         &hf_reg_tlv_t_27_handover_mdho_ul_multiple,
1091                         {
1092                                 "MDHO UL Multiple transmission", "wmx.reg.mdh_ul_multiple",
1093                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x10, NULL, HFILL
1094                         }
1095                 },
1096                 {
1097                         &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps,
1098                         {
1099                                 "MDHO DL soft combining with monitoring MAPs from active BSs", "wmx.reg.mdho_dl_monitor_maps",
1100                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1101                         }
1102                 },
1103                 {
1104                         &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map,
1105                         {
1106                                 "MDHO DL soft Combining with monitoring single MAP from anchor BS", "wmx.reg.mdho_dl_monitor_single_map",
1107                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1108                         }
1109                 },
1110                 {
1111                         &hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader,
1112                         {
1113                                 "MIMO mode feedback request extended subheader", "wmx.reg.mimo_mode_feedback_request_extended_subheader",
1114                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2000, NULL, HFILL
1115                         }
1116                 },
1117                 {
1118                         &hf_reg_tlv_t_43_mini_feedback_extended_subheader,
1119                         {
1120                                 "Mini-feedback extended subheader", "wmx.reg.mini_feedback_extended_subheader",
1121                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8000, NULL, HFILL
1122                         }
1123                 },
1124                 {
1125                         &hf_reg_tlv_t_31_mobility_handover,
1126                         {
1127                                 "Mobility (handover)", "wmx.reg.mobility_handover",
1128                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1129                         }
1130                 },
1131                 {
1132                         &hf_reg_tlv_t_31_mobility_idle_mode,
1133                         {
1134                                 "Idle mode", "wmx.reg.mobility_idle_mode",
1135                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1136                         }
1137                 },
1138                 {
1139                         &hf_reg_tlv_t_31_mobility_sleep_mode,
1140                         {
1141                                 "Sleep mode", "wmx.reg.mobility_sleep_mode",
1142                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1143                         }
1144                 },
1145                 {
1146                         &hf_reg_num_dl_trans_cid,
1147                         {
1148                                 "Number of Downlink transport CIDs the SS can support", "wmx.reg.dl_cids_supported",
1149                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1150                         }
1151                 },
1152                 {
1153                         &hf_reg_tlv_t_21_packing_support,
1154                         {
1155                                 "Packing support", "wmx.reg.packing.support",
1156                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1157                         }
1158                 },
1159                 {
1160                         &hf_reg_tlv_t_43_pdu_sn_long_extended_subheader,
1161                         {
1162                                 "PDU SN (long) extended subheader", "wmx.reg.pdu_sn_long_extended_subheader",
1163                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40000, NULL, HFILL
1164                         }
1165                 },
1166                 {
1167                         &hf_reg_tlv_t_43_pdu_sn_short_extended_subheader,
1168                         {
1169                                 "PDU SN (short) extended subheader", "wmx.reg.pdu_sn_short_extended_subheader",
1170                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20000, NULL, HFILL
1171                         }
1172                 },
1173                 {
1174                         &hf_reg_phs,
1175                         {
1176                                 "PHS support", "wmx.reg.phs",
1177                                 FT_UINT8, BASE_DEC, VALS(vals_reg_phs_support), 0x0, NULL, HFILL
1178                         }
1179                 },
1180                 {
1181                         &hf_reg_tlv_t_43_phy_channel_report_header_support,
1182                         {
1183                                 "PHY channel report header support", "wmx.reg.phy_channel_report_header_support",
1184                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8, NULL, HFILL
1185                         }
1186                 },
1187                 {
1188                         &hf_reg_tlv_t_43_reserved,
1189                         {
1190                                 "Reserved", "wmx.reg.reserved",
1191                                 FT_UINT24, BASE_DEC, NULL, 0xf80000, NULL, HFILL
1192                         }
1193                 },
1194                 {
1195                         &hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter,
1196                         {
1197                                 "SDU_SN extended subheader support", "wmx.reg.sdu_sn_extended_subheader_support",
1198                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x80, NULL, HFILL
1199                         }
1200                 },
1201                 {
1202                         &hf_reg_tlv_t_43_sdu_sn_parameter,
1203                         {
1204                                 "SDU_SN parameter", "wmx.reg.sdu_sn_parameter",
1205                                 FT_UINT24, BASE_DEC, NULL, 0x700, NULL, HFILL
1206                         }
1207                 },
1208                 {
1209                         &hf_reg_tlv_t_43_sn_report_header_support,
1210                         {
1211                                 "SN report header support", "wmx.reg.sn_report_header_support",
1212                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20, NULL, HFILL
1213                         }
1214                 },
1215                 {
1216                         &hf_reg_tlv_t_43_sn_request_extended_subheader,
1217                         {
1218                                 "SN request extended subheader", "wmx.reg.sn_request_extended_subheader",
1219                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10000, NULL, HFILL
1220                         }
1221                 },
1222                 {
1223                         &hf_reg_ss_mgmt_support,
1224                         {
1225                                 "SS management support", "wmx.reg.ss_mgmt_support",
1226                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ss_mgmt_support), 0x0, NULL, HFILL
1227                         }
1228                 },
1229                 {
1230                         &hf_reg_ul_cids,
1231                         {
1232                                 "Number of Uplink transport CIDs the SS can support", "wmx.reg.ul_cids_supported",
1233                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1234                         }
1235                 },
1236                 {
1237                         &hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader,
1238                         {
1239                                 "UL Tx power report extended subheader", "wmx.reg.ul_tx_power_report_extended_subheader",
1240                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4000, NULL, HFILL
1241                         }
1242                 },
1243                 {
1244                         &hf_tlv_type,
1245                         {
1246                                 "Unknown TLV Type", "wmx.reg.unknown_tlv_type",
1247                                 FT_BYTES, BASE_NONE, NULL, 0x00, NULL, HFILL
1248                         }
1249                 },
1250                 {
1251                         &hf_reg_invalid_tlv,
1252                         {
1253                                 "Invalid TLV", "wmx.reg_req.invalid_tlv",
1254                                 FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL
1255                         }
1256                 },
1257                 {
1258                         &hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame,
1259                         {
1260                                 "Maximum MAC level DL data per frame", "wmx.reg_req.max_mac_dl_data",
1261                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1262                         }
1263                 },
1264                 {
1265                         &hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame,
1266                         {
1267                                 "Maximum MAC level UL data per frame", "wmx.reg_req.max_mac_ul_data",
1268                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1269                         }
1270                 },
1271                 {
1272                         &hf_reg_req_min_time_for_inter_fa,
1273                         {
1274                                 "Minimum time for inter-FA HO, default=3", "wmx.reg_req.min_time_for_inter_fa",
1275                                 FT_UINT8, BASE_HEX, NULL, 0xF0, NULL, HFILL
1276                         }
1277                 },
1278                 {
1279                         &hf_reg_req_min_time_for_intra_fa,
1280                         {
1281                                 "Minimum time for intra-FA HO, default=2", "wmx.reg_req.min_time_for_intra_fa",
1282                                 FT_UINT8, BASE_HEX, NULL, 0x0F, NULL, HFILL
1283                         }
1284                 },
1285                 {
1286                         &hf_reg_req_tlv_t_45_ms_periodic_ranging_timer,
1287                         {
1288                                 "MS periodic ranging timer information", "wmx.reg_req.ms_periodic_ranging_timer_info",
1289                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1290                         }
1291                 },
1292                 {       /* IPv4 Mask */
1293                         &hf_ms_previous_ip_address_v4,
1294                         {
1295                                 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v4",
1296                                 FT_IPv4, BASE_NONE, NULL, 0x0, NULL, HFILL
1297                         }
1298                 },
1299                 {       /* IPv6 Source Address */
1300                         &hf_ms_previous_ip_address_v6,
1301                         {
1302                                 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v6",
1303                                 FT_IPv6, BASE_NONE, NULL, 0x0, NULL, HFILL
1304                         }
1305                 },
1306                 {
1307                         &hf_reg_req_secondary_mgmt_cid,
1308                         {
1309                                 "Secondary Management CID", "wmx.reg_req.secondary_mgmt_cid",
1310                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1311                         }
1312                 },
1313                 {
1314                         &hf_reg_req_tlv_t_32_sleep_mode_recovery_time,
1315                         {
1316                                 "Frames required for the MS to switch from sleep to awake-mode", "wmx.reg_req.sleep_recovery",
1317                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1318                         }
1319                 },
1320                 {
1321                         &hf_reg_power_saving_class_type_i,
1322                         {
1323                                 "Power saving class type I supported", "wmx.reg.power_saving_class_type_i",
1324                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1325                         }
1326                 },
1327                 {
1328                         &hf_reg_power_saving_class_type_ii,
1329                         {
1330                                 "Power saving class type II supported", "wmx.reg.power_saving_class_type_ii",
1331                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1332                         }
1333                 },
1334                 {
1335                         &hf_reg_power_saving_class_type_iii,
1336                         {
1337                                 "Power saving class type III supported", "wmx.reg.power_saving_class_type_iii",
1338                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1339                         }
1340                 },
1341                 {
1342                         &hf_reg_multi_active_power_saving_classes,
1343                         {
1344                                 "Multiple active power saving classes supported", "wmx.reg.multi_active_power_saving_classes",
1345                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1346                         }
1347                 },
1348                 {
1349                         &hf_reg_total_power_saving_class_instances,
1350                         {
1351                                 "Total number of power saving class instances of all", "wmx.reg_req.total_power_saving_class_instances",
1352                                 FT_UINT16, BASE_DEC, NULL, 0x1F0, NULL, HFILL
1353                         }
1354                 },
1355                 {
1356                         &hf_reg_power_saving_class_reserved,
1357                         {
1358                                 "Reserved", "wmx.reg.reserved",
1359                                 FT_UINT16, BASE_DEC, NULL, 0xFE00, NULL, HFILL
1360                         }
1361                 },
1362                 {
1363                         &hf_reg_power_saving_class_capability,
1364                         {
1365                                 "Power saving class capability", "wmx.reg.power_saving_class_capability",
1366                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1367                         }
1368                 },
1369                 {
1370                         &hf_reg_ip_phs_sdu_encap,
1371                         {
1372                                 "Classification/PHS options and SDU encapsulation support", "wmx.reg.ip_phs_sdu_encap",
1373                                 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL
1374                         }
1375                 },
1376                 {
1377                         &hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn,
1378                         {
1379                                 "Method for allocating IP address for the secondary management connection", "wmx.reg.method_alloc_ip_addr_secondary_mgmnt_conn",
1380                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1381                         }
1382                 },
1383                 {
1384                         &hf_reg_tlv_t_27_handover_supported,
1385                         {
1386                                 "Handover Support", "wmx.reg.handover_supported",
1387                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1388                         }
1389                 },
1390                 {
1391                         &hf_reg_tlv_t_31_mobility_features_supported,
1392                         {
1393                                 "Mobility Features Supported", "wmx.reg.mobility_features_supported",
1394                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1395                         }
1396                 },
1397                 {
1398                         &hf_reg_tlv_t_40_arq_ack_type,
1399                         {
1400                                 "ARQ ACK Type", "wmx.reg.arq_ack_type",
1401                                 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL
1402                         }
1403                 },
1404                 {
1405                         &hf_reg_tlv_t_43_mac_header_ext_header_support,
1406                         {
1407                                 "MAC header and extended subheader support", "wmx.reg.mac_header_ext_header_support",
1408                                 FT_UINT24, BASE_DEC, NULL, 0x0, NULL, HFILL
1409                         }
1410                 },
1411                 {
1412                         &hf_reg_req_bs_switching_timer,
1413                         {
1414                                 "BS switching timer", "wmx.reg.bs_switching_timer",
1415                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1416                         }
1417                 },
1418         };
1419
1420         /* Setup protocol subtree array */
1421         static gint *ett[] =
1422                 {
1423                         &ett_mac_mgmt_msg_reg_req_decoder
1424                 };
1425
1426
1427         proto_mac_mgmt_msg_reg_req_decoder = proto_register_protocol (
1428                 "WiMax REG-REQ Messages", /* name       */
1429                 "WiMax REG-REQ",          /* short name */
1430                 "wmx.reg_req"             /* abbrev     */
1431                 );
1432
1433         proto_register_field_array(proto_mac_mgmt_msg_reg_req_decoder, hf, array_length(hf));
1434         proto_register_subtree_array(ett, array_length(ett));
1435 }
1436
1437 void proto_reg_handoff_mac_mgmt_msg_reg_req(void)
1438 {
1439         dissector_handle_t reg_req_handle;
1440
1441         reg_req_handle = create_dissector_handle(dissect_mac_mgmt_msg_reg_req_decoder, proto_mac_mgmt_msg_reg_req_decoder);
1442         dissector_add_uint("wmx.mgmtmsg", MAC_MGMT_MSG_REG_REQ, reg_req_handle);
1443 }