arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain

The mfg_ref_sel clock is a mux used to switch between different "safe"
(and slower) clock sources for the GPU: this is used during MFGPLL
reconfiguration and eventually during idling at very low frequencies.

This clock getting turned off means that the GPU will occasionally be
unclocked, producing obvious consequences such as system crash or
unpredictable behavior: assigning it to the top level MFG power domain
will make sure that this stays on at all times during any operation on
the MFG domain (only GPU-related transactions).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230301095523.428461-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 34631adc52c633b7c0d4a26b7f90cfa45fdc1757..a29cdff8a09593f384f26bd999bbeaadbc6c0880 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -499,8 +499,9 @@
 
                                power-domain@MT8192_POWER_DOMAIN_MFG0 {
                                        reg = <MT8192_POWER_DOMAIN_MFG0>;
-                                       clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
-                                       clock-names = "mfg";
+                                       clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
+                                                <&topckgen CLK_TOP_MFG_REF_SEL>;
+                                       clock-names = "mfg", "alt";
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        #power-domain-cells = <1>;