drivers/infiniband/hw/ocrdma/ocrdma_sli.h

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) adapters.                   *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #ifndef __OCRDMA_SLI_H__
  29 #define __OCRDMA_SLI_H__
  30
  31 #define Bit(_b) (1 << (_b))
  32
  33 enum {
  34         OCRDMA_ASIC_GEN_SKH_R = 0x04,
  35         OCRDMA_ASIC_GEN_LANCER = 0x0B
  36 };
  37
  38 enum {
  39         OCRDMA_ASIC_REV_A0 = 0x00,
  40         OCRDMA_ASIC_REV_B0 = 0x10,
  41         OCRDMA_ASIC_REV_C0 = 0x20
  42 };
  43
  44 #define OCRDMA_SUBSYS_ROCE 10
  45 enum {
  46         OCRDMA_CMD_QUERY_CONFIG = 1,
  47         OCRDMA_CMD_ALLOC_PD,
  48         OCRDMA_CMD_DEALLOC_PD,
  49
  50         OCRDMA_CMD_CREATE_AH_TBL,
  51         OCRDMA_CMD_DELETE_AH_TBL,
  52
  53         OCRDMA_CMD_CREATE_QP,
  54         OCRDMA_CMD_QUERY_QP,
  55         OCRDMA_CMD_MODIFY_QP,
  56         OCRDMA_CMD_DELETE_QP,
  57
  58         OCRDMA_CMD_RSVD1,
  59         OCRDMA_CMD_ALLOC_LKEY,
  60         OCRDMA_CMD_DEALLOC_LKEY,
  61         OCRDMA_CMD_REGISTER_NSMR,
  62         OCRDMA_CMD_REREGISTER_NSMR,
  63         OCRDMA_CMD_REGISTER_NSMR_CONT,
  64         OCRDMA_CMD_QUERY_NSMR,
  65         OCRDMA_CMD_ALLOC_MW,
  66         OCRDMA_CMD_QUERY_MW,
  67
  68         OCRDMA_CMD_CREATE_SRQ,
  69         OCRDMA_CMD_QUERY_SRQ,
  70         OCRDMA_CMD_MODIFY_SRQ,
  71         OCRDMA_CMD_DELETE_SRQ,
  72
  73         OCRDMA_CMD_ATTACH_MCAST,
  74         OCRDMA_CMD_DETACH_MCAST,
  75         OCRDMA_CMD_GET_RDMA_STATS,
  76
  77         OCRDMA_CMD_MAX
  78 };
  79
  80 #define OCRDMA_SUBSYS_COMMON 1
  81 enum {
  82         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
  83         OCRDMA_CMD_CREATE_CQ            = 12,
  84         OCRDMA_CMD_CREATE_EQ            = 13,
  85         OCRDMA_CMD_CREATE_MQ            = 21,
  86         OCRDMA_CMD_GET_CTRL_ATTRIBUTES  = 32,
  87         OCRDMA_CMD_GET_FW_VER           = 35,
  88         OCRDMA_CMD_DELETE_MQ            = 53,
  89         OCRDMA_CMD_DELETE_CQ            = 54,
  90         OCRDMA_CMD_DELETE_EQ            = 55,
  91         OCRDMA_CMD_GET_FW_CONFIG        = 58,
  92         OCRDMA_CMD_CREATE_MQ_EXT        = 90,
  93         OCRDMA_CMD_PHY_DETAILS          = 102
  94 };
  95
  96 enum {
  97         QTYPE_EQ        = 1,
  98         QTYPE_CQ        = 2,
  99         QTYPE_MCCQ      = 3
 100 };
 101
 102 #define OCRDMA_MAX_SGID (8)
 103
 104 #define OCRDMA_MAX_QP    2048
 105 #define OCRDMA_MAX_CQ    2048
 106 #define OCRDMA_MAX_STAG  8192
 107
 108 enum {
 109         OCRDMA_DB_RQ_OFFSET             = 0xE0,
 110         OCRDMA_DB_GEN2_RQ_OFFSET        = 0x100,
 111         OCRDMA_DB_SQ_OFFSET             = 0x60,
 112         OCRDMA_DB_GEN2_SQ_OFFSET        = 0x1C0,
 113         OCRDMA_DB_SRQ_OFFSET            = OCRDMA_DB_RQ_OFFSET,
 114         OCRDMA_DB_GEN2_SRQ_OFFSET       = OCRDMA_DB_GEN2_RQ_OFFSET,
 115         OCRDMA_DB_CQ_OFFSET             = 0x120,
 116         OCRDMA_DB_EQ_OFFSET             = OCRDMA_DB_CQ_OFFSET,
 117         OCRDMA_DB_MQ_OFFSET             = 0x140,
 118
 119         OCRDMA_DB_SQ_SHIFT              = 16,
 120         OCRDMA_DB_RQ_SHIFT              = 24
 121 };
 122
 123 #define OCRDMA_DB_CQ_RING_ID_MASK       0x3FF   /* bits 0 - 9 */
 124 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK  0x0C00   /* bits 10-11 of qid at 12-11 */
 125 /* qid #2 msbits at 12-11 */
 126 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT  0x1
 127 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT       (16)        /* bits 16 - 28 */
 128 /* Rearm bit */
 129 #define OCRDMA_DB_CQ_REARM_SHIFT        (29)    /* bit 29 */
 130 /* solicited bit */
 131 #define OCRDMA_DB_CQ_SOLICIT_SHIFT   (31)       /* bit 31 */
 132
 133 #define OCRDMA_EQ_ID_MASK               0x1FF   /* bits 0 - 8 */
 134 #define OCRDMA_EQ_ID_EXT_MASK           0x3e00  /* bits 9-13 */
 135 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT     (2)     /* qid bits 9-13 at 11-15 */
 136
 137 /* Clear the interrupt for this eq */
 138 #define OCRDMA_EQ_CLR_SHIFT                     (9)     /* bit 9 */
 139 /* Must be 1 */
 140 #define OCRDMA_EQ_TYPE_SHIFT            (10)    /* bit 10 */
 141 /* Number of event entries processed */
 142 #define OCRDMA_NUM_EQE_SHIFT            (16)    /* bits 16 - 28 */
 143 /* Rearm bit */
 144 #define OCRDMA_REARM_SHIFT              (29)    /* bit 29 */
 145
 146 #define OCRDMA_MQ_ID_MASK               0x7FF   /* bits 0 - 10 */
 147 /* Number of entries posted */
 148 #define OCRDMA_MQ_NUM_MQE_SHIFT (16)    /* bits 16 - 29 */
 149
 150 #define OCRDMA_MIN_HPAGE_SIZE (4096)
 151
 152 #define OCRDMA_MIN_Q_PAGE_SIZE (4096)
 153 #define OCRDMA_MAX_Q_PAGES     (8)
 154
 155 #define OCRDMA_SLI_ASIC_ID_OFFSET       0x9C
 156 #define OCRDMA_SLI_ASIC_REV_MASK        0x000000FF
 157 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK    0x0000FF00
 158 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT   0x08
 159 /*
 160 # 0: 4K Bytes
 161 # 1: 8K Bytes
 162 # 2: 16K Bytes
 163 # 3: 32K Bytes
 164 # 4: 64K Bytes
 165 # 5: 128K Bytes
 166 # 6: 256K Bytes
 167 # 7: 512K Bytes
 168 */
 169 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8)
 170 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
 171
 172 #define MAX_OCRDMA_QP_PAGES      (8)
 173 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
 174
 175 #define OCRDMA_CREATE_CQ_MAX_PAGES (4)
 176 #define OCRDMA_DPP_CQE_SIZE (4)
 177
 178 #define OCRDMA_GEN2_MAX_CQE 1024
 179 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
 180 #define OCRDMA_GEN2_WQE_SIZE 256
 181 #define OCRDMA_MAX_CQE  4095
 182 #define OCRDMA_CQ_PAGE_SIZE 16384
 183 #define OCRDMA_WQE_SIZE 128
 184 #define OCRDMA_WQE_STRIDE 8
 185 #define OCRDMA_WQE_ALIGN_BYTES 16
 186
 187 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
 188
 189 enum {
 190         OCRDMA_MCH_OPCODE_SHIFT = 0,
 191         OCRDMA_MCH_OPCODE_MASK  = 0xFF,
 192         OCRDMA_MCH_SUBSYS_SHIFT = 8,
 193         OCRDMA_MCH_SUBSYS_MASK  = 0xFF00
 194 };
 195
 196 /* mailbox cmd header */
 197 struct ocrdma_mbx_hdr {
 198         u32 subsys_op;
 199         u32 timeout;            /* in seconds */
 200         u32 cmd_len;
 201         u32 rsvd_version;
 202 };
 203
 204 enum {
 205         OCRDMA_MBX_RSP_OPCODE_SHIFT     = 0,
 206         OCRDMA_MBX_RSP_OPCODE_MASK      = 0xFF,
 207         OCRDMA_MBX_RSP_SUBSYS_SHIFT     = 8,
 208         OCRDMA_MBX_RSP_SUBSYS_MASK      = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
 209
 210         OCRDMA_MBX_RSP_STATUS_SHIFT     = 0,
 211         OCRDMA_MBX_RSP_STATUS_MASK      = 0xFF,
 212         OCRDMA_MBX_RSP_ASTATUS_SHIFT    = 8,
 213         OCRDMA_MBX_RSP_ASTATUS_MASK     = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
 214 };
 215
 216 /* mailbox cmd response */
 217 struct ocrdma_mbx_rsp {
 218         u32 subsys_op;
 219         u32 status;
 220         u32 rsp_len;
 221         u32 add_rsp_len;
 222 };
 223
 224 enum {
 225         OCRDMA_MQE_EMBEDDED     = 1,
 226         OCRDMA_MQE_NONEMBEDDED  = 0
 227 };
 228
 229 struct ocrdma_mqe_sge {
 230         u32 pa_lo;
 231         u32 pa_hi;
 232         u32 len;
 233 };
 234
 235 enum {
 236         OCRDMA_MQE_HDR_EMB_SHIFT        = 0,
 237         OCRDMA_MQE_HDR_EMB_MASK         = Bit(0),
 238         OCRDMA_MQE_HDR_SGE_CNT_SHIFT    = 3,
 239         OCRDMA_MQE_HDR_SGE_CNT_MASK     = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
 240         OCRDMA_MQE_HDR_SPECIAL_SHIFT    = 24,
 241         OCRDMA_MQE_HDR_SPECIAL_MASK     = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
 242 };
 243
 244 struct ocrdma_mqe_hdr {
 245         u32 spcl_sge_cnt_emb;
 246         u32 pyld_len;
 247         u32 tag_lo;
 248         u32 tag_hi;
 249         u32 rsvd3;
 250 };
 251
 252 struct ocrdma_mqe_emb_cmd {
 253         struct ocrdma_mbx_hdr mch;
 254         u8 pyld[220];
 255 };
 256
 257 struct ocrdma_mqe {
 258         struct ocrdma_mqe_hdr hdr;
 259         union {
 260                 struct ocrdma_mqe_emb_cmd emb_req;
 261                 struct {
 262                         struct ocrdma_mqe_sge sge[19];
 263                 } nonemb_req;
 264                 u8 cmd[236];
 265                 struct ocrdma_mbx_rsp rsp;
 266         } u;
 267 };
 268
 269 #define OCRDMA_EQ_LEN       4096
 270 #define OCRDMA_MQ_CQ_LEN    256
 271 #define OCRDMA_MQ_LEN       128
 272
 273 #define PAGE_SHIFT_4K           12
 274 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 275
 276 /* Returns number of pages spanned by the data starting at the given addr */
 277 #define PAGES_4K_SPANNED(_address, size) \
 278         ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 279                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 280
 281 struct ocrdma_delete_q_req {
 282         struct ocrdma_mbx_hdr req;
 283         u32 id;
 284 };
 285
 286 struct ocrdma_pa {
 287         u32 lo;
 288         u32 hi;
 289 };
 290
 291 #define MAX_OCRDMA_EQ_PAGES (8)
 292 struct ocrdma_create_eq_req {
 293         struct ocrdma_mbx_hdr req;
 294         u32 num_pages;
 295         u32 valid;
 296         u32 cnt;
 297         u32 delay;
 298         u32 rsvd;
 299         struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
 300 };
 301
 302 enum {
 303         OCRDMA_CREATE_EQ_VALID  = Bit(29),
 304         OCRDMA_CREATE_EQ_CNT_SHIFT      = 26,
 305         OCRDMA_CREATE_CQ_DELAY_SHIFT    = 13,
 306 };
 307
 308 struct ocrdma_create_eq_rsp {
 309         struct ocrdma_mbx_rsp rsp;
 310         u32 vector_eqid;
 311 };
 312
 313 #define OCRDMA_EQ_MINOR_OTHER (0x1)
 314
 315 enum {
 316         OCRDMA_MCQE_STATUS_SHIFT        = 0,
 317         OCRDMA_MCQE_STATUS_MASK         = 0xFFFF,
 318         OCRDMA_MCQE_ESTATUS_SHIFT       = 16,
 319         OCRDMA_MCQE_ESTATUS_MASK        = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
 320         OCRDMA_MCQE_CONS_SHIFT          = 27,
 321         OCRDMA_MCQE_CONS_MASK           = Bit(27),
 322         OCRDMA_MCQE_CMPL_SHIFT          = 28,
 323         OCRDMA_MCQE_CMPL_MASK           = Bit(28),
 324         OCRDMA_MCQE_AE_SHIFT            = 30,
 325         OCRDMA_MCQE_AE_MASK             = Bit(30),
 326         OCRDMA_MCQE_VALID_SHIFT         = 31,
 327         OCRDMA_MCQE_VALID_MASK          = Bit(31)
 328 };
 329
 330 struct ocrdma_mcqe {
 331         u32 status;
 332         u32 tag_lo;
 333         u32 tag_hi;
 334         u32 valid_ae_cmpl_cons;
 335 };
 336
 337 enum {
 338         OCRDMA_AE_MCQE_QPVALID          = Bit(31),
 339         OCRDMA_AE_MCQE_QPID_MASK        = 0xFFFF,
 340
 341         OCRDMA_AE_MCQE_CQVALID          = Bit(31),
 342         OCRDMA_AE_MCQE_CQID_MASK        = 0xFFFF,
 343         OCRDMA_AE_MCQE_VALID            = Bit(31),
 344         OCRDMA_AE_MCQE_AE               = Bit(30),
 345         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
 346         OCRDMA_AE_MCQE_EVENT_TYPE_MASK  =
 347                                         0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
 348         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
 349         OCRDMA_AE_MCQE_EVENT_CODE_MASK  =
 350                                         0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
 351 };
 352 struct ocrdma_ae_mcqe {
 353         u32 qpvalid_qpid;
 354         u32 cqvalid_cqid;
 355         u32 evt_tag;
 356         u32 valid_ae_event;
 357 };
 358
 359 enum {
 360         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
 361         OCRDMA_AE_PVID_MCQE_ENABLED_MASK  = 0xFF,
 362         OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
 363         OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
 364 };
 365
 366 struct ocrdma_ae_pvid_mcqe {
 367         u32 tag_enabled;
 368         u32 event_tag;
 369         u32 rsvd1;
 370         u32 rsvd2;
 371 };
 372
 373 enum {
 374         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT         = 16,
 375         OCRDMA_AE_MPA_MCQE_REQ_ID_MASK          = 0xFFFF <<
 376                                         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
 377
 378         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT     = 8,
 379         OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK      = 0xFF <<
 380                                         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
 381         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT     = 16,
 382         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK      = 0xFF <<
 383                                         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
 384         OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT       = 30,
 385         OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = Bit(30),
 386         OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT    = 31,
 387         OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = Bit(31)
 388 };
 389
 390 struct ocrdma_ae_mpa_mcqe {
 391         u32 req_id;
 392         u32 w1;
 393         u32 w2;
 394         u32 valid_ae_event;
 395 };
 396
 397 enum {
 398         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT    = 0,
 399         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK     = 0xFFFF,
 400         OCRDMA_AE_QP_MCQE_QP_ID_SHIFT           = 16,
 401         OCRDMA_AE_QP_MCQE_QP_ID_MASK            = 0xFFFF <<
 402                                                 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
 403
 404         OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT      = 8,
 405         OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK       = 0xFF <<
 406                                 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
 407         OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT      = 16,
 408         OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK       = 0xFF <<
 409                                 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
 410         OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT        = 30,
 411         OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = Bit(30),
 412         OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT     = 31,
 413         OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = Bit(31)
 414 };
 415
 416 struct ocrdma_ae_qp_mcqe {
 417         u32 qp_id_state;
 418         u32 w1;
 419         u32 w2;
 420         u32 valid_ae_event;
 421 };
 422
 423 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
 424 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
 425 #define OCRDMA_ASYNC_EVENT_PVID_STATE 0x3
 426
 427 enum OCRDMA_ASYNC_EVENT_TYPE {
 428         OCRDMA_CQ_ERROR                 = 0x00,
 429         OCRDMA_CQ_OVERRUN_ERROR         = 0x01,
 430         OCRDMA_CQ_QPCAT_ERROR           = 0x02,
 431         OCRDMA_QP_ACCESS_ERROR          = 0x03,
 432         OCRDMA_QP_COMM_EST_EVENT        = 0x04,
 433         OCRDMA_SQ_DRAINED_EVENT         = 0x05,
 434         OCRDMA_DEVICE_FATAL_EVENT       = 0x08,
 435         OCRDMA_SRQCAT_ERROR             = 0x0E,
 436         OCRDMA_SRQ_LIMIT_EVENT          = 0x0F,
 437         OCRDMA_QP_LAST_WQE_EVENT        = 0x10
 438 };
 439
 440 /* mailbox command request and responses */
 441 enum {
 442         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT          = 2,
 443         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = Bit(2),
 444         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT        = 3,
 445         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = Bit(3),
 446         OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT               = 8,
 447         OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK                = 0xFFFFFF <<
 448                                 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
 449
 450         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT               = 16,
 451         OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK                = 0xFFFF <<
 452                                         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
 453         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT         = 8,
 454         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK          = 0xFF <<
 455                                 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
 456
 457         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT         = 0,
 458         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK          = 0xFFFF,
 459         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT        = 16,
 460         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK         = 0xFFFF <<
 461                                 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
 462
 463         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT       = 0,
 464         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK        = 0xFFFF,
 465         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT       = 16,
 466         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK        = 0xFFFF <<
 467                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
 468
 469         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET        = 24,
 470         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK          = 0xFF <<
 471                                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
 472         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET        = 16,
 473         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK          = 0xFF <<
 474                                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
 475         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET        = 0,
 476         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK          = 0xFFFF <<
 477                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
 478
 479         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET             = 16,
 480         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK               = 0xFFFF <<
 481                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
 482         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET        = 0,
 483         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK          = 0xFFFF <<
 484                                 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
 485
 486         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET         = 16,
 487         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK           = 0xFFFF <<
 488                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
 489         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET     = 0,
 490         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK       = 0xFFFF <<
 491                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
 492
 493         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET         = 0,
 494         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK           = 0xFFFF <<
 495                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
 496
 497         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET     = 16,
 498         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK       = 0xFFFF <<
 499                                 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
 500         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET     = 0,
 501         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK       = 0xFFFF <<
 502                                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
 503
 504         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET              = 16,
 505         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK                = 0xFFFF <<
 506                                 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
 507         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET     = 0,
 508         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK       = 0xFFFF <<
 509                                 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
 510
 511         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET         = 16,
 512         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK           = 0xFFFF <<
 513                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
 514         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET         = 0,
 515         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK           = 0xFFFF <<
 516                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
 517 };
 518
 519 struct ocrdma_mbx_query_config {
 520         struct ocrdma_mqe_hdr hdr;
 521         struct ocrdma_mbx_rsp rsp;
 522         u32 qp_srq_cq_ird_ord;
 523         u32 max_pd_ca_ack_delay;
 524         u32 max_write_send_sge;
 525         u32 max_ird_ord_per_qp;
 526         u32 max_shared_ird_ord;
 527         u32 max_mr;
 528         u32 max_mr_size_lo;
 529         u32 max_mr_size_hi;
 530         u32 max_num_mr_pbl;
 531         u32 max_mw;
 532         u32 max_fmr;
 533         u32 max_pages_per_frmr;
 534         u32 max_mcast_group;
 535         u32 max_mcast_qp_attach;
 536         u32 max_total_mcast_qp_attach;
 537         u32 wqe_rqe_stride_max_dpp_cqs;
 538         u32 max_srq_rpir_qps;
 539         u32 max_dpp_pds_credits;
 540         u32 max_dpp_credits_pds_per_pd;
 541         u32 max_wqes_rqes_per_q;
 542         u32 max_cq_cqes_per_cq;
 543         u32 max_srq_rqe_sge;
 544 };
 545
 546 struct ocrdma_fw_ver_rsp {
 547         struct ocrdma_mqe_hdr hdr;
 548         struct ocrdma_mbx_rsp rsp;
 549
 550         u8 running_ver[32];
 551 };
 552
 553 struct ocrdma_fw_conf_rsp {
 554         struct ocrdma_mqe_hdr hdr;
 555         struct ocrdma_mbx_rsp rsp;
 556
 557         u32 config_num;
 558         u32 asic_revision;
 559         u32 phy_port;
 560         u32 fn_mode;
 561         struct {
 562                 u32 mode;
 563                 u32 nic_wqid_base;
 564                 u32 nic_wq_tot;
 565                 u32 prot_wqid_base;
 566                 u32 prot_wq_tot;
 567                 u32 prot_rqid_base;
 568                 u32 prot_rqid_tot;
 569                 u32 rsvd[6];
 570         } ulp[2];
 571         u32 fn_capabilities;
 572         u32 rsvd1;
 573         u32 rsvd2;
 574         u32 base_eqid;
 575         u32 max_eq;
 576
 577 };
 578
 579 enum {
 580         OCRDMA_FN_MODE_RDMA     = 0x4
 581 };
 582
 583 struct ocrdma_get_phy_info_rsp {
 584         struct ocrdma_mqe_hdr hdr;
 585         struct ocrdma_mbx_rsp rsp;
 586
 587         u16 phy_type;
 588         u16 interface_type;
 589         u32 misc_params;
 590         u16 ext_phy_details;
 591         u16 rsvd;
 592         u16 auto_speeds_supported;
 593         u16 fixed_speeds_supported;
 594         u32 future_use[2];
 595 };
 596
 597 enum {
 598         OCRDMA_PHY_SPEED_ZERO = 0x0,
 599         OCRDMA_PHY_SPEED_10MBPS = 0x1,
 600         OCRDMA_PHY_SPEED_100MBPS = 0x2,
 601         OCRDMA_PHY_SPEED_1GBPS = 0x4,
 602         OCRDMA_PHY_SPEED_10GBPS = 0x8,
 603         OCRDMA_PHY_SPEED_40GBPS = 0x20
 604 };
 605
 606
 607 struct ocrdma_get_link_speed_rsp {
 608         struct ocrdma_mqe_hdr hdr;
 609         struct ocrdma_mbx_rsp rsp;
 610
 611         u8 pt_port_num;
 612         u8 link_duplex;
 613         u8 phys_port_speed;
 614         u8 phys_port_fault;
 615         u16 rsvd1;
 616         u16 qos_lnk_speed;
 617         u8 logical_lnk_status;
 618         u8 rsvd2[3];
 619 };
 620
 621 enum {
 622         OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
 623         OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
 624         OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
 625         OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
 626         OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
 627         OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
 628         OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
 629         OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
 630         OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
 631 };
 632
 633 enum {
 634         OCRDMA_CREATE_CQ_VER2                   = 2,
 635         OCRDMA_CREATE_CQ_VER3                   = 3,
 636
 637         OCRDMA_CREATE_CQ_PAGE_CNT_MASK          = 0xFFFF,
 638         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT        = 16,
 639         OCRDMA_CREATE_CQ_PAGE_SIZE_MASK         = 0xFF,
 640
 641         OCRDMA_CREATE_CQ_COALESCWM_SHIFT        = 12,
 642         OCRDMA_CREATE_CQ_COALESCWM_MASK         = Bit(13) | Bit(12),
 643         OCRDMA_CREATE_CQ_FLAGS_NODELAY          = Bit(14),
 644         OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = Bit(15),
 645
 646         OCRDMA_CREATE_CQ_EQ_ID_MASK             = 0xFFFF,
 647         OCRDMA_CREATE_CQ_CQE_COUNT_MASK         = 0xFFFF
 648 };
 649
 650 enum {
 651         OCRDMA_CREATE_CQ_VER0                   = 0,
 652         OCRDMA_CREATE_CQ_DPP                    = 1,
 653         OCRDMA_CREATE_CQ_TYPE_SHIFT             = 24,
 654         OCRDMA_CREATE_CQ_EQID_SHIFT             = 22,
 655
 656         OCRDMA_CREATE_CQ_CNT_SHIFT              = 27,
 657         OCRDMA_CREATE_CQ_FLAGS_VALID            = Bit(29),
 658         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = Bit(31),
 659         OCRDMA_CREATE_CQ_DEF_FLAGS              = OCRDMA_CREATE_CQ_FLAGS_VALID |
 660                                         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
 661                                         OCRDMA_CREATE_CQ_FLAGS_NODELAY
 662 };
 663
 664 struct ocrdma_create_cq_cmd {
 665         struct ocrdma_mbx_hdr req;
 666         u32 pgsz_pgcnt;
 667         u32 ev_cnt_flags;
 668         u32 eqn;
 669         u16 cqe_count;
 670         u16 pd_id;
 671         u32 rsvd6;
 672         struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
 673 };
 674
 675 struct ocrdma_create_cq {
 676         struct ocrdma_mqe_hdr hdr;
 677         struct ocrdma_create_cq_cmd cmd;
 678 };
 679
 680 enum {
 681         OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
 682 };
 683
 684 struct ocrdma_create_cq_cmd_rsp {
 685         struct ocrdma_mbx_rsp rsp;
 686         u32 cq_id;
 687 };
 688
 689 struct ocrdma_create_cq_rsp {
 690         struct ocrdma_mqe_hdr hdr;
 691         struct ocrdma_create_cq_cmd_rsp rsp;
 692 };
 693
 694 enum {
 695         OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT         = 22,
 696         OCRDMA_CREATE_MQ_CQ_ID_SHIFT            = 16,
 697         OCRDMA_CREATE_MQ_RING_SIZE_SHIFT        = 16,
 698         OCRDMA_CREATE_MQ_VALID                  = Bit(31),
 699         OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = Bit(0)
 700 };
 701
 702 struct ocrdma_create_mq_req {
 703         struct ocrdma_mbx_hdr req;
 704         u32 cqid_pages;
 705         u32 async_event_bitmap;
 706         u32 async_cqid_ringsize;
 707         u32 valid;
 708         u32 async_cqid_valid;
 709         u32 rsvd;
 710         struct ocrdma_pa pa[8];
 711 };
 712
 713 struct ocrdma_create_mq_rsp {
 714         struct ocrdma_mbx_rsp rsp;
 715         u32 id;
 716 };
 717
 718 enum {
 719         OCRDMA_DESTROY_CQ_QID_SHIFT                     = 0,
 720         OCRDMA_DESTROY_CQ_QID_MASK                      = 0xFFFF,
 721         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT        = 16,
 722         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK         = 0xFFFF <<
 723                                 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
 724 };
 725
 726 struct ocrdma_destroy_cq {
 727         struct ocrdma_mqe_hdr hdr;
 728         struct ocrdma_mbx_hdr req;
 729
 730         u32 bypass_flush_qid;
 731 };
 732
 733 struct ocrdma_destroy_cq_rsp {
 734         struct ocrdma_mqe_hdr hdr;
 735         struct ocrdma_mbx_rsp rsp;
 736 };
 737
 738 enum {
 739         OCRDMA_QPT_GSI  = 1,
 740         OCRDMA_QPT_RC   = 2,
 741         OCRDMA_QPT_UD   = 4,
 742 };
 743
 744 enum {
 745         OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT        = 0,
 746         OCRDMA_CREATE_QP_REQ_PD_ID_MASK         = 0xFFFF,
 747         OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
 748         OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
 749         OCRDMA_CREATE_QP_REQ_QPT_SHIFT          = 29,
 750         OCRDMA_CREATE_QP_REQ_QPT_MASK           = Bit(31) | Bit(30) | Bit(29),
 751
 752         OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT      = 0,
 753         OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK       = 0xFFFF,
 754         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT      = 16,
 755         OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK       = 0xFFFF <<
 756                                         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
 757
 758         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT        = 0,
 759         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK         = 0xFFFF,
 760         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT         = 16,
 761         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK          = 0xFFFF <<
 762                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
 763
 764         OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT               = 0,
 765         OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = Bit(0),
 766         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT          = 1,
 767         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = Bit(1),
 768         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT          = 2,
 769         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = Bit(2),
 770         OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT             = 3,
 771         OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = Bit(3),
 772         OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT             = 4,
 773         OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = Bit(4),
 774         OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT              = 5,
 775         OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = Bit(5),
 776         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT          = 6,
 777         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = Bit(6),
 778         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT           = 7,
 779         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = Bit(7),
 780         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT        = 8,
 781         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = Bit(8),
 782         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT         = 16,
 783         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK          = 0xFFFF <<
 784                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
 785
 786         OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT              = 0,
 787         OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK               = 0xFFFF,
 788         OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT              = 16,
 789         OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK               = 0xFFFF <<
 790                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
 791
 792         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT         = 0,
 793         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK          = 0xFFFF,
 794         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT         = 16,
 795         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK          = 0xFFFF <<
 796                                 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
 797
 798         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT             = 0,
 799         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK              = 0xFFFF,
 800         OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT             = 16,
 801         OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK              = 0xFFFF <<
 802                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
 803
 804         OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT              = 0,
 805         OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK               = 0xFFFF,
 806         OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT              = 16,
 807         OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK               = 0xFFFF <<
 808                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
 809
 810         OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT            = 0,
 811         OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK             = 0xFFFF,
 812         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT           = 16,
 813         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK            = 0xFFFF <<
 814                                 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
 815 };
 816
 817 enum {
 818         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT   = 16,
 819         OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT     = 1
 820 };
 821
 822 #define MAX_OCRDMA_IRD_PAGES 4
 823
 824 enum ocrdma_qp_flags {
 825         OCRDMA_QP_MW_BIND       = 1,
 826         OCRDMA_QP_LKEY0         = (1 << 1),
 827         OCRDMA_QP_FAST_REG      = (1 << 2),
 828         OCRDMA_QP_INB_RD        = (1 << 6),
 829         OCRDMA_QP_INB_WR        = (1 << 7),
 830 };
 831
 832 enum ocrdma_qp_state {
 833         OCRDMA_QPS_RST          = 0,
 834         OCRDMA_QPS_INIT         = 1,
 835         OCRDMA_QPS_RTR          = 2,
 836         OCRDMA_QPS_RTS          = 3,
 837         OCRDMA_QPS_SQE          = 4,
 838         OCRDMA_QPS_SQ_DRAINING  = 5,
 839         OCRDMA_QPS_ERR          = 6,
 840         OCRDMA_QPS_SQD          = 7
 841 };
 842
 843 struct ocrdma_create_qp_req {
 844         struct ocrdma_mqe_hdr hdr;
 845         struct ocrdma_mbx_hdr req;
 846
 847         u32 type_pgsz_pdn;
 848         u32 max_wqe_rqe;
 849         u32 max_sge_send_write;
 850         u32 max_sge_recv_flags;
 851         u32 max_ord_ird;
 852         u32 num_wq_rq_pages;
 853         u32 wqe_rqe_size;
 854         u32 wq_rq_cqid;
 855         struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
 856         struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
 857         u32 dpp_credits_cqid;
 858         u32 rpir_lkey;
 859         struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
 860 };
 861
 862 enum {
 863         OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT                = 0,
 864         OCRDMA_CREATE_QP_RSP_QP_ID_MASK                 = 0xFFFF,
 865
 866         OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT              = 0,
 867         OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK               = 0xFFFF,
 868         OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT              = 16,
 869         OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK               = 0xFFFF <<
 870                                 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
 871
 872         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT        = 0,
 873         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK         = 0xFFFF,
 874         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT         = 16,
 875         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK          = 0xFFFF <<
 876                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
 877
 878         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT         = 16,
 879         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK          = 0xFFFF <<
 880                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
 881
 882         OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT              = 0,
 883         OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK               = 0xFFFF,
 884         OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT              = 16,
 885         OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK               = 0xFFFF <<
 886                                 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
 887
 888         OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT                = 0,
 889         OCRDMA_CREATE_QP_RSP_RQ_ID_MASK                 = 0xFFFF,
 890         OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT                = 16,
 891         OCRDMA_CREATE_QP_RSP_SQ_ID_MASK                 = 0xFFFF <<
 892                                 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
 893
 894         OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = Bit(0),
 895         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT      = 1,
 896         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK       = 0x7FFF <<
 897                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
 898         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT          = 16,
 899         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK           = 0xFFFF <<
 900                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
 901 };
 902
 903 struct ocrdma_create_qp_rsp {
 904         struct ocrdma_mqe_hdr hdr;
 905         struct ocrdma_mbx_rsp rsp;
 906
 907         u32 qp_id;
 908         u32 max_wqe_rqe;
 909         u32 max_sge_send_write;
 910         u32 max_sge_recv;
 911         u32 max_ord_ird;
 912         u32 sq_rq_id;
 913         u32 dpp_response;
 914 };
 915
 916 struct ocrdma_destroy_qp {
 917         struct ocrdma_mqe_hdr hdr;
 918         struct ocrdma_mbx_hdr req;
 919         u32 qp_id;
 920 };
 921
 922 struct ocrdma_destroy_qp_rsp {
 923         struct ocrdma_mqe_hdr hdr;
 924         struct ocrdma_mbx_rsp rsp;
 925 };
 926
 927 enum {
 928         OCRDMA_MODIFY_QP_ID_SHIFT       = 0,
 929         OCRDMA_MODIFY_QP_ID_MASK        = 0xFFFF,
 930
 931         OCRDMA_QP_PARA_QPS_VALID        = Bit(0),
 932         OCRDMA_QP_PARA_SQD_ASYNC_VALID  = Bit(1),
 933         OCRDMA_QP_PARA_PKEY_VALID       = Bit(2),
 934         OCRDMA_QP_PARA_QKEY_VALID       = Bit(3),
 935         OCRDMA_QP_PARA_PMTU_VALID       = Bit(4),
 936         OCRDMA_QP_PARA_ACK_TO_VALID     = Bit(5),
 937         OCRDMA_QP_PARA_RETRY_CNT_VALID  = Bit(6),
 938         OCRDMA_QP_PARA_RRC_VALID        = Bit(7),
 939         OCRDMA_QP_PARA_RQPSN_VALID      = Bit(8),
 940         OCRDMA_QP_PARA_MAX_IRD_VALID    = Bit(9),
 941         OCRDMA_QP_PARA_MAX_ORD_VALID    = Bit(10),
 942         OCRDMA_QP_PARA_RNT_VALID        = Bit(11),
 943         OCRDMA_QP_PARA_SQPSN_VALID      = Bit(12),
 944         OCRDMA_QP_PARA_DST_QPN_VALID    = Bit(13),
 945         OCRDMA_QP_PARA_MAX_WQE_VALID    = Bit(14),
 946         OCRDMA_QP_PARA_MAX_RQE_VALID    = Bit(15),
 947         OCRDMA_QP_PARA_SGE_SEND_VALID   = Bit(16),
 948         OCRDMA_QP_PARA_SGE_RECV_VALID   = Bit(17),
 949         OCRDMA_QP_PARA_SGE_WR_VALID     = Bit(18),
 950         OCRDMA_QP_PARA_INB_RDEN_VALID   = Bit(19),
 951         OCRDMA_QP_PARA_INB_WREN_VALID   = Bit(20),
 952         OCRDMA_QP_PARA_FLOW_LBL_VALID   = Bit(21),
 953         OCRDMA_QP_PARA_BIND_EN_VALID    = Bit(22),
 954         OCRDMA_QP_PARA_ZLKEY_EN_VALID   = Bit(23),
 955         OCRDMA_QP_PARA_FMR_EN_VALID     = Bit(24),
 956         OCRDMA_QP_PARA_INBAT_EN_VALID   = Bit(25),
 957         OCRDMA_QP_PARA_VLAN_EN_VALID    = Bit(26),
 958
 959         OCRDMA_MODIFY_QP_FLAGS_RD       = Bit(0),
 960         OCRDMA_MODIFY_QP_FLAGS_WR       = Bit(1),
 961         OCRDMA_MODIFY_QP_FLAGS_SEND     = Bit(2),
 962         OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = Bit(3)
 963 };
 964
 965 enum {
 966         OCRDMA_QP_PARAMS_SRQ_ID_SHIFT           = 0,
 967         OCRDMA_QP_PARAMS_SRQ_ID_MASK            = 0xFFFF,
 968
 969         OCRDMA_QP_PARAMS_MAX_RQE_SHIFT          = 0,
 970         OCRDMA_QP_PARAMS_MAX_RQE_MASK           = 0xFFFF,
 971         OCRDMA_QP_PARAMS_MAX_WQE_SHIFT          = 16,
 972         OCRDMA_QP_PARAMS_MAX_WQE_MASK           = 0xFFFF <<
 973             OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
 974
 975         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT    = 0,
 976         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK     = 0xFFFF,
 977         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT     = 16,
 978         OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK      = 0xFFFF <<
 979                                         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
 980
 981         OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = Bit(0),
 982         OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = Bit(1),
 983         OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = Bit(2),
 984         OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = Bit(3),
 985         OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = Bit(4),
 986         OCRDMA_QP_PARAMS_STATE_SHIFT            = 5,
 987         OCRDMA_QP_PARAMS_STATE_MASK             = Bit(5) | Bit(6) | Bit(7),
 988         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = Bit(8),
 989         OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = Bit(9),
 990         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT     = 16,
 991         OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK      = 0xFFFF <<
 992                                         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
 993
 994         OCRDMA_QP_PARAMS_MAX_IRD_SHIFT          = 0,
 995         OCRDMA_QP_PARAMS_MAX_IRD_MASK           = 0xFFFF,
 996         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT          = 16,
 997         OCRDMA_QP_PARAMS_MAX_ORD_MASK           = 0xFFFF <<
 998                                         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
 999
1000         OCRDMA_QP_PARAMS_RQ_CQID_SHIFT          = 0,
1001         OCRDMA_QP_PARAMS_RQ_CQID_MASK           = 0xFFFF,
1002         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT          = 16,
1003         OCRDMA_QP_PARAMS_WQ_CQID_MASK           = 0xFFFF <<
1004                                         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1005
1006         OCRDMA_QP_PARAMS_RQ_PSN_SHIFT           = 0,
1007         OCRDMA_QP_PARAMS_RQ_PSN_MASK            = 0xFFFFFF,
1008         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT          = 24,
1009         OCRDMA_QP_PARAMS_HOP_LMT_MASK           = 0xFF <<
1010                                         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1011
1012         OCRDMA_QP_PARAMS_SQ_PSN_SHIFT           = 0,
1013         OCRDMA_QP_PARAMS_SQ_PSN_MASK            = 0xFFFFFF,
1014         OCRDMA_QP_PARAMS_TCLASS_SHIFT           = 24,
1015         OCRDMA_QP_PARAMS_TCLASS_MASK            = 0xFF <<
1016                                         OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1017
1018         OCRDMA_QP_PARAMS_DEST_QPN_SHIFT         = 0,
1019         OCRDMA_QP_PARAMS_DEST_QPN_MASK          = 0xFFFFFF,
1020         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT    = 24,
1021         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK     = 0x7 <<
1022                                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1023         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT      = 27,
1024         OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK       = 0x1F <<
1025                                         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1026
1027         OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT       = 0,
1028         OCRDMA_QP_PARAMS_PKEY_INDEX_MASK        = 0xFFFF,
1029         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT         = 18,
1030         OCRDMA_QP_PARAMS_PATH_MTU_MASK          = 0x3FFF <<
1031                                         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1032
1033         OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT       = 0,
1034         OCRDMA_QP_PARAMS_FLOW_LABEL_MASK        = 0xFFFFF,
1035         OCRDMA_QP_PARAMS_SL_SHIFT               = 20,
1036         OCRDMA_QP_PARAMS_SL_MASK                = 0xF <<
1037                                         OCRDMA_QP_PARAMS_SL_SHIFT,
1038         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT        = 24,
1039         OCRDMA_QP_PARAMS_RETRY_CNT_MASK         = 0x7 <<
1040                                         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1041         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT    = 27,
1042         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK     = 0x1F <<
1043                                         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1044
1045         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT    = 0,
1046         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK     = 0xFFFF,
1047         OCRDMA_QP_PARAMS_VLAN_SHIFT             = 16,
1048         OCRDMA_QP_PARAMS_VLAN_MASK              = 0xFFFF <<
1049                                         OCRDMA_QP_PARAMS_VLAN_SHIFT
1050 };
1051
1052 struct ocrdma_qp_params {
1053         u32 id;
1054         u32 max_wqe_rqe;
1055         u32 max_sge_send_write;
1056         u32 max_sge_recv_flags;
1057         u32 max_ord_ird;
1058         u32 wq_rq_cqid;
1059         u32 hop_lmt_rq_psn;
1060         u32 tclass_sq_psn;
1061         u32 ack_to_rnr_rtc_dest_qpn;
1062         u32 path_mtu_pkey_indx;
1063         u32 rnt_rc_sl_fl;
1064         u8 sgid[16];
1065         u8 dgid[16];
1066         u32 dmac_b0_to_b3;
1067         u32 vlan_dmac_b4_to_b5;
1068         u32 qkey;
1069 };
1070
1071
1072 struct ocrdma_modify_qp {
1073         struct ocrdma_mqe_hdr hdr;
1074         struct ocrdma_mbx_hdr req;
1075
1076         struct ocrdma_qp_params params;
1077         u32 flags;
1078         u32 rdma_flags;
1079         u32 num_outstanding_atomic_rd;
1080 };
1081
1082 enum {
1083         OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT      = 0,
1084         OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK       = 0xFFFF,
1085         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT      = 16,
1086         OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK       = 0xFFFF <<
1087                                         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1088
1089         OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT      = 0,
1090         OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK       = 0xFFFF,
1091         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT      = 16,
1092         OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK       = 0xFFFF <<
1093                                         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1094 };
1095
1096 struct ocrdma_modify_qp_rsp {
1097         struct ocrdma_mqe_hdr hdr;
1098         struct ocrdma_mbx_rsp rsp;
1099
1100         u32 max_wqe_rqe;
1101         u32 max_ord_ird;
1102 };
1103
1104 struct ocrdma_query_qp {
1105         struct ocrdma_mqe_hdr hdr;
1106         struct ocrdma_mbx_hdr req;
1107
1108 #define OCRDMA_QUERY_UP_QP_ID_SHIFT     0
1109 #define OCRDMA_QUERY_UP_QP_ID_MASK      0xFFFFFF
1110         u32 qp_id;
1111 };
1112
1113 struct ocrdma_query_qp_rsp {
1114         struct ocrdma_mqe_hdr hdr;
1115         struct ocrdma_mbx_rsp rsp;
1116         struct ocrdma_qp_params params;
1117 };
1118
1119 enum {
1120         OCRDMA_CREATE_SRQ_PD_ID_SHIFT           = 0,
1121         OCRDMA_CREATE_SRQ_PD_ID_MASK            = 0xFFFF,
1122         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT           = 16,
1123         OCRDMA_CREATE_SRQ_PG_SZ_MASK            = 0x3 <<
1124                                         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1125
1126         OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT         = 0,
1127         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT    = 16,
1128         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK     = 0xFFFF <<
1129                                         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1130
1131         OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT        = 0,
1132         OCRDMA_CREATE_SRQ_RQE_SIZE_MASK         = 0xFFFF,
1133         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT    = 16,
1134         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK     = 0xFFFF <<
1135                                         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1136 };
1137
1138 struct ocrdma_create_srq {
1139         struct ocrdma_mqe_hdr hdr;
1140         struct ocrdma_mbx_hdr req;
1141
1142         u32 pgsz_pdid;
1143         u32 max_sge_rqe;
1144         u32 pages_rqe_sz;
1145         struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1146 };
1147
1148 enum {
1149         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT                      = 0,
1150         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK                       = 0xFFFFFF,
1151
1152         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT           = 0,
1153         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK            = 0xFFFF,
1154         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT      = 16,
1155         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK       = 0xFFFF <<
1156                         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1157 };
1158
1159 struct ocrdma_create_srq_rsp {
1160         struct ocrdma_mqe_hdr hdr;
1161         struct ocrdma_mbx_rsp rsp;
1162
1163         u32 id;
1164         u32 max_sge_rqe_allocated;
1165 };
1166
1167 enum {
1168         OCRDMA_MODIFY_SRQ_ID_SHIFT      = 0,
1169         OCRDMA_MODIFY_SRQ_ID_MASK       = 0xFFFFFF,
1170
1171         OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1172         OCRDMA_MODIFY_SRQ_MAX_RQE_MASK  = 0xFFFF,
1173         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT   = 16,
1174         OCRDMA_MODIFY_SRQ__LIMIT_MASK   = 0xFFFF <<
1175                                         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1176 };
1177
1178 struct ocrdma_modify_srq {
1179         struct ocrdma_mqe_hdr hdr;
1180         struct ocrdma_mbx_rsp rep;
1181
1182         u32 id;
1183         u32 limit_max_rqe;
1184 };
1185
1186 enum {
1187         OCRDMA_QUERY_SRQ_ID_SHIFT       = 0,
1188         OCRDMA_QUERY_SRQ_ID_MASK        = 0xFFFFFF
1189 };
1190
1191 struct ocrdma_query_srq {
1192         struct ocrdma_mqe_hdr hdr;
1193         struct ocrdma_mbx_rsp req;
1194
1195         u32 id;
1196 };
1197
1198 enum {
1199         OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT        = 0,
1200         OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK         = 0xFFFF,
1201         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT      = 16,
1202         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK       = 0xFFFF <<
1203                                         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1204
1205         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1206         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK  = 0xFFFF,
1207         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT    = 16,
1208         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK     = 0xFFFF <<
1209                                         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1210 };
1211
1212 struct ocrdma_query_srq_rsp {
1213         struct ocrdma_mqe_hdr hdr;
1214         struct ocrdma_mbx_rsp req;
1215
1216         u32 max_rqe_pdid;
1217         u32 srq_lmt_max_sge;
1218 };
1219
1220 enum {
1221         OCRDMA_DESTROY_SRQ_ID_SHIFT     = 0,
1222         OCRDMA_DESTROY_SRQ_ID_MASK      = 0xFFFFFF
1223 };
1224
1225 struct ocrdma_destroy_srq {
1226         struct ocrdma_mqe_hdr hdr;
1227         struct ocrdma_mbx_rsp req;
1228
1229         u32 id;
1230 };
1231
1232 enum {
1233         OCRDMA_ALLOC_PD_ENABLE_DPP      = BIT(16),
1234         OCRDMA_PD_MAX_DPP_ENABLED_QP    = 8,
1235         OCRDMA_DPP_PAGE_SIZE            = 4096
1236 };
1237
1238 struct ocrdma_alloc_pd {
1239         struct ocrdma_mqe_hdr hdr;
1240         struct ocrdma_mbx_hdr req;
1241         u32 enable_dpp_rsvd;
1242 };
1243
1244 enum {
1245         OCRDMA_ALLOC_PD_RSP_DPP                 = Bit(16),
1246         OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT      = 20,
1247         OCRDMA_ALLOC_PD_RSP_PDID_MASK           = 0xFFFF,
1248 };
1249
1250 struct ocrdma_alloc_pd_rsp {
1251         struct ocrdma_mqe_hdr hdr;
1252         struct ocrdma_mbx_rsp rsp;
1253         u32 dpp_page_pdid;
1254 };
1255
1256 struct ocrdma_dealloc_pd {
1257         struct ocrdma_mqe_hdr hdr;
1258         struct ocrdma_mbx_hdr req;
1259         u32 id;
1260 };
1261
1262 struct ocrdma_dealloc_pd_rsp {
1263         struct ocrdma_mqe_hdr hdr;
1264         struct ocrdma_mbx_rsp rsp;
1265 };
1266
1267 enum {
1268         OCRDMA_ADDR_CHECK_ENABLE        = 1,
1269         OCRDMA_ADDR_CHECK_DISABLE       = 0
1270 };
1271
1272 enum {
1273         OCRDMA_ALLOC_LKEY_PD_ID_SHIFT           = 0,
1274         OCRDMA_ALLOC_LKEY_PD_ID_MASK            = 0xFFFF,
1275
1276         OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT      = 0,
1277         OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = Bit(0),
1278         OCRDMA_ALLOC_LKEY_FMR_SHIFT             = 1,
1279         OCRDMA_ALLOC_LKEY_FMR_MASK              = Bit(1),
1280         OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT      = 2,
1281         OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = Bit(2),
1282         OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT       = 3,
1283         OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = Bit(3),
1284         OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT       = 4,
1285         OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = Bit(4),
1286         OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT        = 5,
1287         OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = Bit(5),
1288         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = Bit(6),
1289         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT   = 6,
1290         OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT        = 16,
1291         OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK         = 0xFFFF <<
1292                                                 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1293 };
1294
1295 struct ocrdma_alloc_lkey {
1296         struct ocrdma_mqe_hdr hdr;
1297         struct ocrdma_mbx_hdr req;
1298
1299         u32 pdid;
1300         u32 pbl_sz_flags;
1301 };
1302
1303 struct ocrdma_alloc_lkey_rsp {
1304         struct ocrdma_mqe_hdr hdr;
1305         struct ocrdma_mbx_rsp rsp;
1306
1307         u32 lrkey;
1308         u32 num_pbl_rsvd;
1309 };
1310
1311 struct ocrdma_dealloc_lkey {
1312         struct ocrdma_mqe_hdr hdr;
1313         struct ocrdma_mbx_hdr req;
1314
1315         u32 lkey;
1316         u32 rsvd_frmr;
1317 };
1318
1319 struct ocrdma_dealloc_lkey_rsp {
1320         struct ocrdma_mqe_hdr hdr;
1321         struct ocrdma_mbx_rsp rsp;
1322 };
1323
1324 #define MAX_OCRDMA_NSMR_PBL    (u32)22
1325 #define MAX_OCRDMA_PBL_SIZE     65536
1326 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1327
1328 enum {
1329         OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT       = 0,
1330         OCRDMA_REG_NSMR_LRKEY_INDEX_MASK        = 0xFFFFFF,
1331         OCRDMA_REG_NSMR_LRKEY_SHIFT             = 24,
1332         OCRDMA_REG_NSMR_LRKEY_MASK              = 0xFF <<
1333                                         OCRDMA_REG_NSMR_LRKEY_SHIFT,
1334
1335         OCRDMA_REG_NSMR_PD_ID_SHIFT             = 0,
1336         OCRDMA_REG_NSMR_PD_ID_MASK              = 0xFFFF,
1337         OCRDMA_REG_NSMR_NUM_PBL_SHIFT           = 16,
1338         OCRDMA_REG_NSMR_NUM_PBL_MASK            = 0xFFFF <<
1339                                         OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1340
1341         OCRDMA_REG_NSMR_PBE_SIZE_SHIFT          = 0,
1342         OCRDMA_REG_NSMR_PBE_SIZE_MASK           = 0xFFFF,
1343         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT        = 16,
1344         OCRDMA_REG_NSMR_HPAGE_SIZE_MASK         = 0xFF <<
1345                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1346         OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT       = 24,
1347         OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = Bit(24),
1348         OCRDMA_REG_NSMR_ZB_SHIFT                = 25,
1349         OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = Bit(25),
1350         OCRDMA_REG_NSMR_REMOTE_INV_SHIFT        = 26,
1351         OCRDMA_REG_NSMR_REMOTE_INV_MASK         = Bit(26),
1352         OCRDMA_REG_NSMR_REMOTE_WR_SHIFT         = 27,
1353         OCRDMA_REG_NSMR_REMOTE_WR_MASK          = Bit(27),
1354         OCRDMA_REG_NSMR_REMOTE_RD_SHIFT         = 28,
1355         OCRDMA_REG_NSMR_REMOTE_RD_MASK          = Bit(28),
1356         OCRDMA_REG_NSMR_LOCAL_WR_SHIFT          = 29,
1357         OCRDMA_REG_NSMR_LOCAL_WR_MASK           = Bit(29),
1358         OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT     = 30,
1359         OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = Bit(30),
1360         OCRDMA_REG_NSMR_LAST_SHIFT              = 31,
1361         OCRDMA_REG_NSMR_LAST_MASK               = Bit(31)
1362 };
1363
1364 struct ocrdma_reg_nsmr {
1365         struct ocrdma_mqe_hdr hdr;
1366         struct ocrdma_mbx_hdr cmd;
1367
1368         u32 fr_mr;
1369         u32 num_pbl_pdid;
1370         u32 flags_hpage_pbe_sz;
1371         u32 totlen_low;
1372         u32 totlen_high;
1373         u32 fbo_low;
1374         u32 fbo_high;
1375         u32 va_loaddr;
1376         u32 va_hiaddr;
1377         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1378 };
1379
1380 enum {
1381         OCRDMA_REG_NSMR_CONT_PBL_SHIFT          = 0,
1382         OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK     = 0xFFFF,
1383         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT      = 16,
1384         OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK       = 0xFFFF <<
1385                                         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1386
1387         OCRDMA_REG_NSMR_CONT_LAST_SHIFT         = 31,
1388         OCRDMA_REG_NSMR_CONT_LAST_MASK          = Bit(31)
1389 };
1390
1391 struct ocrdma_reg_nsmr_cont {
1392         struct ocrdma_mqe_hdr hdr;
1393         struct ocrdma_mbx_hdr cmd;
1394
1395         u32 lrkey;
1396         u32 num_pbl_offset;
1397         u32 last;
1398
1399         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1400 };
1401
1402 struct ocrdma_pbe {
1403         u32 pa_hi;
1404         u32 pa_lo;
1405 };
1406
1407 enum {
1408         OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT       = 16,
1409         OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK        = 0xFFFF0000
1410 };
1411 struct ocrdma_reg_nsmr_rsp {
1412         struct ocrdma_mqe_hdr hdr;
1413         struct ocrdma_mbx_rsp rsp;
1414
1415         u32 lrkey;
1416         u32 num_pbl;
1417 };
1418
1419 enum {
1420         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT      = 0,
1421         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK       = 0xFFFFFF,
1422         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT            = 24,
1423         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK             = 0xFF <<
1424                                         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1425
1426         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT          = 16,
1427         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK           = 0xFFFF <<
1428                                         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1429 };
1430
1431 struct ocrdma_reg_nsmr_cont_rsp {
1432         struct ocrdma_mqe_hdr hdr;
1433         struct ocrdma_mbx_rsp rsp;
1434
1435         u32 lrkey_key_index;
1436         u32 num_pbl;
1437 };
1438
1439 enum {
1440         OCRDMA_ALLOC_MW_PD_ID_SHIFT     = 0,
1441         OCRDMA_ALLOC_MW_PD_ID_MASK      = 0xFFFF
1442 };
1443
1444 struct ocrdma_alloc_mw {
1445         struct ocrdma_mqe_hdr hdr;
1446         struct ocrdma_mbx_hdr req;
1447
1448         u32 pdid;
1449 };
1450
1451 enum {
1452         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT   = 0,
1453         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK    = 0xFFFFFF
1454 };
1455
1456 struct ocrdma_alloc_mw_rsp {
1457         struct ocrdma_mqe_hdr hdr;
1458         struct ocrdma_mbx_rsp rsp;
1459
1460         u32 lrkey_index;
1461 };
1462
1463 struct ocrdma_attach_mcast {
1464         struct ocrdma_mqe_hdr hdr;
1465         struct ocrdma_mbx_hdr req;
1466         u32 qp_id;
1467         u8 mgid[16];
1468         u32 mac_b0_to_b3;
1469         u32 vlan_mac_b4_to_b5;
1470 };
1471
1472 struct ocrdma_attach_mcast_rsp {
1473         struct ocrdma_mqe_hdr hdr;
1474         struct ocrdma_mbx_rsp rsp;
1475 };
1476
1477 struct ocrdma_detach_mcast {
1478         struct ocrdma_mqe_hdr hdr;
1479         struct ocrdma_mbx_hdr req;
1480         u32 qp_id;
1481         u8 mgid[16];
1482         u32 mac_b0_to_b3;
1483         u32 vlan_mac_b4_to_b5;
1484 };
1485
1486 struct ocrdma_detach_mcast_rsp {
1487         struct ocrdma_mqe_hdr hdr;
1488         struct ocrdma_mbx_rsp rsp;
1489 };
1490
1491 enum {
1492         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT        = 19,
1493         OCRDMA_CREATE_AH_NUM_PAGES_MASK         = 0xF <<
1494                                         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1495
1496         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT        = 16,
1497         OCRDMA_CREATE_AH_PAGE_SIZE_MASK         = 0x7 <<
1498                                         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1499
1500         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT       = 23,
1501         OCRDMA_CREATE_AH_ENTRY_SIZE_MASK        = 0x1FF <<
1502                                         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1503 };
1504
1505 #define OCRDMA_AH_TBL_PAGES 8
1506
1507 struct ocrdma_create_ah_tbl {
1508         struct ocrdma_mqe_hdr hdr;
1509         struct ocrdma_mbx_hdr req;
1510
1511         u32 ah_conf;
1512         struct ocrdma_pa tbl_addr[8];
1513 };
1514
1515 struct ocrdma_create_ah_tbl_rsp {
1516         struct ocrdma_mqe_hdr hdr;
1517         struct ocrdma_mbx_rsp rsp;
1518         u32 ahid;
1519 };
1520
1521 struct ocrdma_delete_ah_tbl {
1522         struct ocrdma_mqe_hdr hdr;
1523         struct ocrdma_mbx_hdr req;
1524         u32 ahid;
1525 };
1526
1527 struct ocrdma_delete_ah_tbl_rsp {
1528         struct ocrdma_mqe_hdr hdr;
1529         struct ocrdma_mbx_rsp rsp;
1530 };
1531
1532 enum {
1533         OCRDMA_EQE_VALID_SHIFT          = 0,
1534         OCRDMA_EQE_VALID_MASK           = Bit(0),
1535         OCRDMA_EQE_FOR_CQE_MASK         = 0xFFFE,
1536         OCRDMA_EQE_RESOURCE_ID_SHIFT    = 16,
1537         OCRDMA_EQE_RESOURCE_ID_MASK     = 0xFFFF <<
1538                                 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1539 };
1540
1541 struct ocrdma_eqe {
1542         u32 id_valid;
1543 };
1544
1545 enum OCRDMA_CQE_STATUS {
1546         OCRDMA_CQE_SUCCESS = 0,
1547         OCRDMA_CQE_LOC_LEN_ERR,
1548         OCRDMA_CQE_LOC_QP_OP_ERR,
1549         OCRDMA_CQE_LOC_EEC_OP_ERR,
1550         OCRDMA_CQE_LOC_PROT_ERR,
1551         OCRDMA_CQE_WR_FLUSH_ERR,
1552         OCRDMA_CQE_MW_BIND_ERR,
1553         OCRDMA_CQE_BAD_RESP_ERR,
1554         OCRDMA_CQE_LOC_ACCESS_ERR,
1555         OCRDMA_CQE_REM_INV_REQ_ERR,
1556         OCRDMA_CQE_REM_ACCESS_ERR,
1557         OCRDMA_CQE_REM_OP_ERR,
1558         OCRDMA_CQE_RETRY_EXC_ERR,
1559         OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1560         OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1561         OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1562         OCRDMA_CQE_REM_ABORT_ERR,
1563         OCRDMA_CQE_INV_EECN_ERR,
1564         OCRDMA_CQE_INV_EEC_STATE_ERR,
1565         OCRDMA_CQE_FATAL_ERR,
1566         OCRDMA_CQE_RESP_TIMEOUT_ERR,
1567         OCRDMA_CQE_GENERAL_ERR
1568 };
1569
1570 enum {
1571         /* w0 */
1572         OCRDMA_CQE_WQEIDX_SHIFT         = 0,
1573         OCRDMA_CQE_WQEIDX_MASK          = 0xFFFF,
1574
1575         /* w1 */
1576         OCRDMA_CQE_UD_XFER_LEN_SHIFT    = 16,
1577         OCRDMA_CQE_PKEY_SHIFT           = 0,
1578         OCRDMA_CQE_PKEY_MASK            = 0xFFFF,
1579
1580         /* w2 */
1581         OCRDMA_CQE_QPN_SHIFT            = 0,
1582         OCRDMA_CQE_QPN_MASK             = 0x0000FFFF,
1583
1584         OCRDMA_CQE_BUFTAG_SHIFT         = 16,
1585         OCRDMA_CQE_BUFTAG_MASK          = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1586
1587         /* w3 */
1588         OCRDMA_CQE_UD_STATUS_SHIFT      = 24,
1589         OCRDMA_CQE_UD_STATUS_MASK       = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1590         OCRDMA_CQE_STATUS_SHIFT         = 16,
1591         OCRDMA_CQE_STATUS_MASK          = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1592         OCRDMA_CQE_VALID                = Bit(31),
1593         OCRDMA_CQE_INVALIDATE           = Bit(30),
1594         OCRDMA_CQE_QTYPE                = Bit(29),
1595         OCRDMA_CQE_IMM                  = Bit(28),
1596         OCRDMA_CQE_WRITE_IMM            = Bit(27),
1597         OCRDMA_CQE_QTYPE_SQ             = 0,
1598         OCRDMA_CQE_QTYPE_RQ             = 1,
1599         OCRDMA_CQE_SRCQP_MASK           = 0xFFFFFF
1600 };
1601
1602 struct ocrdma_cqe {
1603         union {
1604                 /* w0 to w2 */
1605                 struct {
1606                         u32 wqeidx;
1607                         u32 bytes_xfered;
1608                         u32 qpn;
1609                 } wq;
1610                 struct {
1611                         u32 lkey_immdt;
1612                         u32 rxlen;
1613                         u32 buftag_qpn;
1614                 } rq;
1615                 struct {
1616                         u32 lkey_immdt;
1617                         u32 rxlen_pkey;
1618                         u32 buftag_qpn;
1619                 } ud;
1620                 struct {
1621                         u32 word_0;
1622                         u32 word_1;
1623                         u32 qpn;
1624                 } cmn;
1625         };
1626         u32 flags_status_srcqpn;        /* w3 */
1627 };
1628
1629 struct ocrdma_sge {
1630         u32 addr_hi;
1631         u32 addr_lo;
1632         u32 lrkey;
1633         u32 len;
1634 };
1635
1636 enum {
1637         OCRDMA_FLAG_SIG         = 0x1,
1638         OCRDMA_FLAG_INV         = 0x2,
1639         OCRDMA_FLAG_FENCE_L     = 0x4,
1640         OCRDMA_FLAG_FENCE_R     = 0x8,
1641         OCRDMA_FLAG_SOLICIT     = 0x10,
1642         OCRDMA_FLAG_IMM         = 0x20,
1643
1644         /* Stag flags */
1645         OCRDMA_LKEY_FLAG_LOCAL_WR       = 0x1,
1646         OCRDMA_LKEY_FLAG_REMOTE_RD      = 0x2,
1647         OCRDMA_LKEY_FLAG_REMOTE_WR      = 0x4,
1648         OCRDMA_LKEY_FLAG_VATO           = 0x8,
1649 };
1650
1651 enum OCRDMA_WQE_OPCODE {
1652         OCRDMA_WRITE            = 0x06,
1653         OCRDMA_READ             = 0x0C,
1654         OCRDMA_RESV0            = 0x02,
1655         OCRDMA_SEND             = 0x00,
1656         OCRDMA_CMP_SWP          = 0x14,
1657         OCRDMA_BIND_MW          = 0x10,
1658         OCRDMA_FR_MR            = 0x11,
1659         OCRDMA_RESV1            = 0x0A,
1660         OCRDMA_LKEY_INV         = 0x15,
1661         OCRDMA_FETCH_ADD        = 0x13,
1662         OCRDMA_POST_RQ          = 0x12
1663 };
1664
1665 enum {
1666         OCRDMA_TYPE_INLINE      = 0x0,
1667         OCRDMA_TYPE_LKEY        = 0x1,
1668 };
1669
1670 enum {
1671         OCRDMA_WQE_OPCODE_SHIFT         = 0,
1672         OCRDMA_WQE_OPCODE_MASK          = 0x0000001F,
1673         OCRDMA_WQE_FLAGS_SHIFT          = 5,
1674         OCRDMA_WQE_TYPE_SHIFT           = 16,
1675         OCRDMA_WQE_TYPE_MASK            = 0x00030000,
1676         OCRDMA_WQE_SIZE_SHIFT           = 18,
1677         OCRDMA_WQE_SIZE_MASK            = 0xFF,
1678         OCRDMA_WQE_NXT_WQE_SIZE_SHIFT   = 25,
1679
1680         OCRDMA_WQE_LKEY_FLAGS_SHIFT     = 0,
1681         OCRDMA_WQE_LKEY_FLAGS_MASK      = 0xF
1682 };
1683
1684 /* header WQE for all the SQ and RQ operations */
1685 struct ocrdma_hdr_wqe {
1686         u32 cw;
1687         union {
1688                 u32 rsvd_tag;
1689                 u32 rsvd_lkey_flags;
1690         };
1691         union {
1692                 u32 immdt;
1693                 u32 lkey;
1694         };
1695         u32 total_len;
1696 };
1697
1698 struct ocrdma_ewqe_ud_hdr {
1699         u32 rsvd_dest_qpn;
1700         u32 qkey;
1701         u32 rsvd_ahid;
1702         u32 rsvd;
1703 };
1704
1705 /* extended wqe followed by hdr_wqe for Fast Memory register */
1706 struct ocrdma_ewqe_fr {
1707         u32 va_hi;
1708         u32 va_lo;
1709         u32 fbo_hi;
1710         u32 fbo_lo;
1711         u32 size_sge;
1712         u32 num_sges;
1713         u32 rsvd;
1714         u32 rsvd2;
1715 };
1716
1717 struct ocrdma_eth_basic {
1718         u8 dmac[6];
1719         u8 smac[6];
1720         __be16 eth_type;
1721 } __packed;
1722
1723 struct ocrdma_eth_vlan {
1724         u8 dmac[6];
1725         u8 smac[6];
1726         __be16 eth_type;
1727         __be16 vlan_tag;
1728 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1729         __be16 roce_eth_type;
1730 } __packed;
1731
1732 struct ocrdma_grh {
1733         __be32  tclass_flow;
1734         __be32  pdid_hoplimit;
1735         u8      sgid[16];
1736         u8      dgid[16];
1737         u16     rsvd;
1738 } __packed;
1739
1740 #define OCRDMA_AV_VALID         Bit(7)
1741 #define OCRDMA_AV_VLAN_VALID    Bit(1)
1742
1743 struct ocrdma_av {
1744         struct ocrdma_eth_vlan eth_hdr;
1745         struct ocrdma_grh grh;
1746         u32 valid;
1747 } __packed;
1748
1749 struct ocrdma_rsrc_stats {
1750         u32 dpp_pds;
1751         u32 non_dpp_pds;
1752         u32 rc_dpp_qps;
1753         u32 uc_dpp_qps;
1754         u32 ud_dpp_qps;
1755         u32 rc_non_dpp_qps;
1756         u32 rsvd;
1757         u32 uc_non_dpp_qps;
1758         u32 ud_non_dpp_qps;
1759         u32 rsvd1;
1760         u32 srqs;
1761         u32 rbqs;
1762         u32 r64K_nsmr;
1763         u32 r64K_to_2M_nsmr;
1764         u32 r2M_to_44M_nsmr;
1765         u32 r44M_to_1G_nsmr;
1766         u32 r1G_to_4G_nsmr;
1767         u32 nsmr_count_4G_to_32G;
1768         u32 r32G_to_64G_nsmr;
1769         u32 r64G_to_128G_nsmr;
1770         u32 r128G_to_higher_nsmr;
1771         u32 embedded_nsmr;
1772         u32 frmr;
1773         u32 prefetch_qps;
1774         u32 ondemand_qps;
1775         u32 phy_mr;
1776         u32 mw;
1777         u32 rsvd2[7];
1778 };
1779
1780 struct ocrdma_db_err_stats {
1781         u32 sq_doorbell_errors;
1782         u32 cq_doorbell_errors;
1783         u32 rq_srq_doorbell_errors;
1784         u32 cq_overflow_errors;
1785         u32 rsvd[4];
1786 };
1787
1788 struct ocrdma_wqe_stats {
1789         u32 large_send_rc_wqes_lo;
1790         u32 large_send_rc_wqes_hi;
1791         u32 large_write_rc_wqes_lo;
1792         u32 large_write_rc_wqes_hi;
1793         u32 rsvd[4];
1794         u32 read_wqes_lo;
1795         u32 read_wqes_hi;
1796         u32 frmr_wqes_lo;
1797         u32 frmr_wqes_hi;
1798         u32 mw_bind_wqes_lo;
1799         u32 mw_bind_wqes_hi;
1800         u32 invalidate_wqes_lo;
1801         u32 invalidate_wqes_hi;
1802         u32 rsvd1[2];
1803         u32 dpp_wqe_drops;
1804         u32 rsvd2[5];
1805 };
1806
1807 struct ocrdma_tx_stats {
1808         u32 send_pkts_lo;
1809         u32 send_pkts_hi;
1810         u32 write_pkts_lo;
1811         u32 write_pkts_hi;
1812         u32 read_pkts_lo;
1813         u32 read_pkts_hi;
1814         u32 read_rsp_pkts_lo;
1815         u32 read_rsp_pkts_hi;
1816         u32 ack_pkts_lo;
1817         u32 ack_pkts_hi;
1818         u32 send_bytes_lo;
1819         u32 send_bytes_hi;
1820         u32 write_bytes_lo;
1821         u32 write_bytes_hi;
1822         u32 read_req_bytes_lo;
1823         u32 read_req_bytes_hi;
1824         u32 read_rsp_bytes_lo;
1825         u32 read_rsp_bytes_hi;
1826         u32 ack_timeouts;
1827         u32 rsvd[5];
1828 };
1829
1830
1831 struct ocrdma_tx_qp_err_stats {
1832         u32 local_length_errors;
1833         u32 local_protection_errors;
1834         u32 local_qp_operation_errors;
1835         u32 retry_count_exceeded_errors;
1836         u32 rnr_retry_count_exceeded_errors;
1837         u32 rsvd[3];
1838 };
1839
1840 struct ocrdma_rx_stats {
1841         u32 roce_frame_bytes_lo;
1842         u32 roce_frame_bytes_hi;
1843         u32 roce_frame_icrc_drops;
1844         u32 roce_frame_payload_len_drops;
1845         u32 ud_drops;
1846         u32 qp1_drops;
1847         u32 psn_error_request_packets;
1848         u32 psn_error_resp_packets;
1849         u32 rnr_nak_timeouts;
1850         u32 rnr_nak_receives;
1851         u32 roce_frame_rxmt_drops;
1852         u32 nak_count_psn_sequence_errors;
1853         u32 rc_drop_count_lookup_errors;
1854         u32 rq_rnr_naks;
1855         u32 srq_rnr_naks;
1856         u32 roce_frames_lo;
1857         u32 roce_frames_hi;
1858         u32 rsvd;
1859 };
1860
1861 struct ocrdma_rx_qp_err_stats {
1862         u32 nak_invalid_requst_errors;
1863         u32 nak_remote_operation_errors;
1864         u32 nak_count_remote_access_errors;
1865         u32 local_length_errors;
1866         u32 local_protection_errors;
1867         u32 local_qp_operation_errors;
1868         u32 rsvd[2];
1869 };
1870
1871 struct ocrdma_tx_dbg_stats {
1872         u32 data[100];
1873 };
1874
1875 struct ocrdma_rx_dbg_stats {
1876         u32 data[200];
1877 };
1878
1879 struct ocrdma_rdma_stats_req {
1880         struct ocrdma_mbx_hdr hdr;
1881         u8 reset_stats;
1882         u8 rsvd[3];
1883 } __packed;
1884
1885 struct ocrdma_rdma_stats_resp {
1886         struct ocrdma_mbx_hdr hdr;
1887         struct ocrdma_rsrc_stats act_rsrc_stats;
1888         struct ocrdma_rsrc_stats th_rsrc_stats;
1889         struct ocrdma_db_err_stats      db_err_stats;
1890         struct ocrdma_wqe_stats         wqe_stats;
1891         struct ocrdma_tx_stats          tx_stats;
1892         struct ocrdma_tx_qp_err_stats   tx_qp_err_stats;
1893         struct ocrdma_rx_stats          rx_stats;
1894         struct ocrdma_rx_qp_err_stats   rx_qp_err_stats;
1895         struct ocrdma_tx_dbg_stats      tx_dbg_stats;
1896         struct ocrdma_rx_dbg_stats      rx_dbg_stats;
1897 } __packed;
1898
1899
1900 struct mgmt_hba_attribs {
1901         u8 flashrom_version_string[32];
1902         u8 manufacturer_name[32];
1903         u32 supported_modes;
1904         u32 rsvd0[3];
1905         u8 ncsi_ver_string[12];
1906         u32 default_extended_timeout;
1907         u8 controller_model_number[32];
1908         u8 controller_description[64];
1909         u8 controller_serial_number[32];
1910         u8 ip_version_string[32];
1911         u8 firmware_version_string[32];
1912         u8 bios_version_string[32];
1913         u8 redboot_version_string[32];
1914         u8 driver_version_string[32];
1915         u8 fw_on_flash_version_string[32];
1916         u32 functionalities_supported;
1917         u16 max_cdblength;
1918         u8 asic_revision;
1919         u8 generational_guid[16];
1920         u8 hba_port_count;
1921         u16 default_link_down_timeout;
1922         u8 iscsi_ver_min_max;
1923         u8 multifunction_device;
1924         u8 cache_valid;
1925         u8 hba_status;
1926         u8 max_domains_supported;
1927         u8 phy_port;
1928         u32 firmware_post_status;
1929         u32 hba_mtu[8];
1930         u32 rsvd1[4];
1931 };
1932
1933 struct mgmt_controller_attrib {
1934         struct mgmt_hba_attribs hba_attribs;
1935         u16 pci_vendor_id;
1936         u16 pci_device_id;
1937         u16 pci_sub_vendor_id;
1938         u16 pci_sub_system_id;
1939         u8 pci_bus_number;
1940         u8 pci_device_number;
1941         u8 pci_function_number;
1942         u8 interface_type;
1943         u64 unique_identifier;
1944         u32 rsvd0[5];
1945 };
1946
1947 struct ocrdma_get_ctrl_attribs_rsp {
1948         struct ocrdma_mbx_hdr hdr;
1949         struct mgmt_controller_attrib ctrl_attribs;
1950 };
1951
1952
1953 #endif                          /* __OCRDMA_SLI_H__ */