2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "intel_lrc_reg.h"
141 #include "intel_mocs.h"
142 #include "intel_workarounds.h"
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define GEN8_CTX_STATUS_COMPLETED_MASK \
159 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
161 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
162 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
163 #define WA_TAIL_DWORDS 2
164 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
166 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
167 struct intel_engine_cs *engine,
168 struct intel_context *ce);
169 static void execlists_init_reg_state(u32 *reg_state,
170 struct i915_gem_context *ctx,
171 struct intel_engine_cs *engine,
172 struct intel_ring *ring);
174 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
176 return rb_entry(rb, struct i915_priolist, node);
179 static inline int rq_prio(const struct i915_request *rq)
181 return rq->sched.attr.priority;
184 static inline bool need_preempt(const struct intel_engine_cs *engine,
185 const struct i915_request *last,
188 return (intel_engine_has_preemption(engine) &&
189 __execlists_need_preempt(prio, rq_prio(last)) &&
190 !i915_request_completed(last));
194 * The context descriptor encodes various attributes of a context,
195 * including its GTT address and some flags. Because it's fairly
196 * expensive to calculate, we'll just do it once and cache the result,
197 * which remains valid until the context is unpinned.
199 * This is what a descriptor looks like, from LSB to MSB::
201 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
202 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
203 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
204 * bits 53-54: mbz, reserved for use by hardware
205 * bits 55-63: group ID, currently unused and set to 0
207 * Starting from Gen11, the upper dword of the descriptor has a new format:
209 * bits 32-36: reserved
210 * bits 37-47: SW context ID
211 * bits 48:53: engine instance
212 * bit 54: mbz, reserved for use by hardware
213 * bits 55-60: SW counter
214 * bits 61-63: engine class
216 * engine info, SW context ID and SW counter need to form a unique number
217 * (Context ID) per lrc.
220 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
221 struct intel_engine_cs *engine,
222 struct intel_context *ce)
226 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
227 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
229 desc = ctx->desc_template; /* bits 0-11 */
230 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
232 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
234 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
237 * The following 32bits are copied into the OA reports (dword 2).
238 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
241 if (INTEL_GEN(ctx->i915) >= 11) {
242 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
243 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
246 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
249 /* TODO: decide what to do with SW counter (bits 55-60) */
251 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
254 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
255 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
261 static struct i915_priolist *
262 lookup_priolist(struct intel_engine_cs *engine, int prio)
264 struct intel_engine_execlists * const execlists = &engine->execlists;
265 struct i915_priolist *p;
266 struct rb_node **parent, *rb;
269 if (unlikely(execlists->no_priolist))
270 prio = I915_PRIORITY_NORMAL;
273 /* most positive priority is scheduled first, equal priorities fifo */
275 parent = &execlists->queue.rb_node;
279 if (prio > p->priority) {
280 parent = &rb->rb_left;
281 } else if (prio < p->priority) {
282 parent = &rb->rb_right;
289 if (prio == I915_PRIORITY_NORMAL) {
290 p = &execlists->default_priolist;
292 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
293 /* Convert an allocation failure to a priority bump */
295 prio = I915_PRIORITY_NORMAL; /* recurses just once */
297 /* To maintain ordering with all rendering, after an
298 * allocation failure we have to disable all scheduling.
299 * Requests will then be executed in fifo, and schedule
300 * will ensure that dependencies are emitted in fifo.
301 * There will be still some reordering with existing
302 * requests, so if userspace lied about their
303 * dependencies that reordering may be visible.
305 execlists->no_priolist = true;
311 INIT_LIST_HEAD(&p->requests);
312 rb_link_node(&p->node, rb, parent);
313 rb_insert_color(&p->node, &execlists->queue);
316 execlists->first = &p->node;
321 static void unwind_wa_tail(struct i915_request *rq)
323 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
324 assert_ring_tail_valid(rq->ring, rq->tail);
327 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
329 struct i915_request *rq, *rn;
330 struct i915_priolist *uninitialized_var(p);
331 int last_prio = I915_PRIORITY_INVALID;
333 lockdep_assert_held(&engine->timeline.lock);
335 list_for_each_entry_safe_reverse(rq, rn,
336 &engine->timeline.requests,
338 if (i915_request_completed(rq))
341 __i915_request_unsubmit(rq);
344 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
345 if (rq_prio(rq) != last_prio) {
346 last_prio = rq_prio(rq);
347 p = lookup_priolist(engine, last_prio);
350 GEM_BUG_ON(p->priority != rq_prio(rq));
351 list_add(&rq->sched.link, &p->requests);
356 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
358 struct intel_engine_cs *engine =
359 container_of(execlists, typeof(*engine), execlists);
362 spin_lock_irqsave(&engine->timeline.lock, flags);
364 __unwind_incomplete_requests(engine);
366 spin_unlock_irqrestore(&engine->timeline.lock, flags);
370 execlists_context_status_change(struct i915_request *rq, unsigned long status)
373 * Only used when GVT-g is enabled now. When GVT-g is disabled,
374 * The compiler should eliminate this function as dead-code.
376 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
379 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
384 execlists_user_begin(struct intel_engine_execlists *execlists,
385 const struct execlist_port *port)
387 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
391 execlists_user_end(struct intel_engine_execlists *execlists)
393 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
397 execlists_context_schedule_in(struct i915_request *rq)
399 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
400 intel_engine_context_in(rq->engine);
404 execlists_context_schedule_out(struct i915_request *rq, unsigned long status)
406 intel_engine_context_out(rq->engine);
407 execlists_context_status_change(rq, status);
408 trace_i915_request_out(rq);
412 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
414 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
415 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
416 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
417 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
420 static u64 execlists_update_context(struct i915_request *rq)
422 struct intel_context *ce = rq->hw_context;
423 struct i915_hw_ppgtt *ppgtt =
424 rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
425 u32 *reg_state = ce->lrc_reg_state;
427 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
429 /* True 32b PPGTT with dynamic page allocation: update PDP
430 * registers and point the unallocated PDPs to scratch page.
431 * PML4 is allocated during ppgtt init, so this is not needed
434 if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
435 execlists_update_context_pdps(ppgtt, reg_state);
440 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
442 if (execlists->ctrl_reg) {
443 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
444 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
446 writel(upper_32_bits(desc), execlists->submit_reg);
447 writel(lower_32_bits(desc), execlists->submit_reg);
451 static void execlists_submit_ports(struct intel_engine_cs *engine)
453 struct intel_engine_execlists *execlists = &engine->execlists;
454 struct execlist_port *port = execlists->port;
458 * ELSQ note: the submit queue is not cleared after being submitted
459 * to the HW so we need to make sure we always clean it up. This is
460 * currently ensured by the fact that we always write the same number
461 * of elsq entries, keep this in mind before changing the loop below.
463 for (n = execlists_num_ports(execlists); n--; ) {
464 struct i915_request *rq;
468 rq = port_unpack(&port[n], &count);
470 GEM_BUG_ON(count > !n);
472 execlists_context_schedule_in(rq);
473 port_set(&port[n], port_pack(rq, count));
474 desc = execlists_update_context(rq);
475 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
477 GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
479 port[n].context_id, count,
481 rq->fence.context, rq->fence.seqno,
482 intel_engine_get_seqno(engine),
489 write_desc(execlists, desc, n);
492 /* we need to manually load the submit queue */
493 if (execlists->ctrl_reg)
494 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
496 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
499 static bool ctx_single_port_submission(const struct intel_context *ce)
501 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
502 i915_gem_context_force_single_submission(ce->gem_context));
505 static bool can_merge_ctx(const struct intel_context *prev,
506 const struct intel_context *next)
511 if (ctx_single_port_submission(prev))
517 static void port_assign(struct execlist_port *port, struct i915_request *rq)
519 GEM_BUG_ON(rq == port_request(port));
521 if (port_isset(port))
522 i915_request_put(port_request(port));
524 port_set(port, port_pack(i915_request_get(rq), port_count(port)));
527 static void inject_preempt_context(struct intel_engine_cs *engine)
529 struct intel_engine_execlists *execlists = &engine->execlists;
530 struct intel_context *ce =
531 to_intel_context(engine->i915->preempt_context, engine);
534 GEM_BUG_ON(execlists->preempt_complete_status !=
535 upper_32_bits(ce->lrc_desc));
536 GEM_BUG_ON((ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1] &
537 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
538 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)) !=
539 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
540 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT));
543 * Switch to our empty preempt context so
544 * the state of the GPU is known (idle).
546 GEM_TRACE("%s\n", engine->name);
547 for (n = execlists_num_ports(execlists); --n; )
548 write_desc(execlists, 0, n);
550 write_desc(execlists, ce->lrc_desc, n);
552 /* we need to manually load the submit queue */
553 if (execlists->ctrl_reg)
554 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
556 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
557 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
560 static void complete_preempt_context(struct intel_engine_execlists *execlists)
562 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
564 execlists_cancel_port_requests(execlists);
565 execlists_unwind_incomplete_requests(execlists);
567 execlists_clear_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
570 static bool __execlists_dequeue(struct intel_engine_cs *engine)
572 struct intel_engine_execlists * const execlists = &engine->execlists;
573 struct execlist_port *port = execlists->port;
574 const struct execlist_port * const last_port =
575 &execlists->port[execlists->port_mask];
576 struct i915_request *last = port_request(port);
580 lockdep_assert_held(&engine->timeline.lock);
582 /* Hardware submission is through 2 ports. Conceptually each port
583 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
584 * static for a context, and unique to each, so we only execute
585 * requests belonging to a single context from each ring. RING_HEAD
586 * is maintained by the CS in the context image, it marks the place
587 * where it got up to last time, and through RING_TAIL we tell the CS
588 * where we want to execute up to this time.
590 * In this list the requests are in order of execution. Consecutive
591 * requests from the same context are adjacent in the ringbuffer. We
592 * can combine these requests into a single RING_TAIL update:
594 * RING_HEAD...req1...req2
596 * since to execute req2 the CS must first execute req1.
598 * Our goal then is to point each port to the end of a consecutive
599 * sequence of requests as being the most optimal (fewest wake ups
600 * and context switches) submission.
603 rb = execlists->first;
604 GEM_BUG_ON(rb_first(&execlists->queue) != rb);
608 * Don't resubmit or switch until all outstanding
609 * preemptions (lite-restore) are seen. Then we
610 * know the next preemption status we see corresponds
611 * to this ELSP update.
613 GEM_BUG_ON(!execlists_is_active(execlists,
614 EXECLISTS_ACTIVE_USER));
615 GEM_BUG_ON(!port_count(&port[0]));
618 * If we write to ELSP a second time before the HW has had
619 * a chance to respond to the previous write, we can confuse
620 * the HW and hit "undefined behaviour". After writing to ELSP,
621 * we must then wait until we see a context-switch event from
622 * the HW to indicate that it has had a chance to respond.
624 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
627 if (need_preempt(engine, last, execlists->queue_priority)) {
628 inject_preempt_context(engine);
633 * In theory, we could coalesce more requests onto
634 * the second port (the first port is active, with
635 * no preemptions pending). However, that means we
636 * then have to deal with the possible lite-restore
637 * of the second port (as we submit the ELSP, there
638 * may be a context-switch) but also we may complete
639 * the resubmission before the context-switch. Ergo,
640 * coalescing onto the second port will cause a
641 * preemption event, but we cannot predict whether
642 * that will affect port[0] or port[1].
644 * If the second port is already active, we can wait
645 * until the next context-switch before contemplating
646 * new requests. The GPU will be busy and we should be
647 * able to resubmit the new ELSP before it idles,
648 * avoiding pipeline bubbles (momentary pauses where
649 * the driver is unable to keep up the supply of new
650 * work). However, we have to double check that the
651 * priorities of the ports haven't been switch.
653 if (port_count(&port[1]))
657 * WaIdleLiteRestore:bdw,skl
658 * Apply the wa NOOPs to prevent
659 * ring:HEAD == rq:TAIL as we resubmit the
660 * request. See gen8_emit_breadcrumb() for
661 * where we prepare the padding after the
662 * end of the request.
664 last->tail = last->wa_tail;
668 struct i915_priolist *p = to_priolist(rb);
669 struct i915_request *rq, *rn;
671 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
673 * Can we combine this request with the current port?
674 * It has to be the same context/ringbuffer and not
675 * have any exceptions (e.g. GVT saying never to
678 * If we can combine the requests, we can execute both
679 * by updating the RING_TAIL to point to the end of the
680 * second request, and so we never need to tell the
681 * hardware about the first.
684 !can_merge_ctx(rq->hw_context, last->hw_context)) {
686 * If we are on the second port and cannot
687 * combine this request with the last, then we
690 if (port == last_port) {
691 __list_del_many(&p->requests,
697 * If GVT overrides us we only ever submit
698 * port[0], leaving port[1] empty. Note that we
699 * also have to be careful that we don't queue
700 * the same context (even though a different
701 * request) to the second port.
703 if (ctx_single_port_submission(last->hw_context) ||
704 ctx_single_port_submission(rq->hw_context)) {
705 __list_del_many(&p->requests,
710 GEM_BUG_ON(last->hw_context == rq->hw_context);
713 port_assign(port, last);
716 GEM_BUG_ON(port_isset(port));
719 INIT_LIST_HEAD(&rq->sched.link);
720 __i915_request_submit(rq);
721 trace_i915_request_in(rq, port_index(port, execlists));
727 rb_erase(&p->node, &execlists->queue);
728 INIT_LIST_HEAD(&p->requests);
729 if (p->priority != I915_PRIORITY_NORMAL)
730 kmem_cache_free(engine->i915->priorities, p);
735 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
737 * We choose queue_priority such that if we add a request of greater
738 * priority than this, we kick the submission tasklet to decide on
739 * the right order of submitting the requests to hardware. We must
740 * also be prepared to reorder requests as they are in-flight on the
741 * HW. We derive the queue_priority then as the first "hole" in
742 * the HW submission ports and if there are no available slots,
743 * the priority of the lowest executing request, i.e. last.
745 * When we do receive a higher priority request ready to run from the
746 * user, see queue_request(), the queue_priority is bumped to that
747 * request triggering preemption on the next dequeue (or subsequent
748 * interrupt for secondary ports).
750 execlists->queue_priority =
751 port != execlists->port ? rq_prio(last) : INT_MIN;
753 execlists->first = rb;
755 port_assign(port, last);
757 /* We must always keep the beast fed if we have work piled up */
758 GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
760 /* Re-evaluate the executing context setup after each preemptive kick */
762 execlists_user_begin(execlists, execlists->port);
767 static void execlists_dequeue(struct intel_engine_cs *engine)
769 struct intel_engine_execlists * const execlists = &engine->execlists;
773 spin_lock_irqsave(&engine->timeline.lock, flags);
774 submit = __execlists_dequeue(engine);
775 spin_unlock_irqrestore(&engine->timeline.lock, flags);
778 execlists_submit_ports(engine);
780 GEM_BUG_ON(port_isset(execlists->port) &&
781 !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
785 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
787 struct execlist_port *port = execlists->port;
788 unsigned int num_ports = execlists_num_ports(execlists);
790 while (num_ports-- && port_isset(port)) {
791 struct i915_request *rq = port_request(port);
793 GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n",
795 (unsigned int)(port - execlists->port),
797 rq->fence.context, rq->fence.seqno,
798 intel_engine_get_seqno(rq->engine));
800 GEM_BUG_ON(!execlists->active);
801 execlists_context_schedule_out(rq,
802 i915_request_completed(rq) ?
803 INTEL_CONTEXT_SCHEDULE_OUT :
804 INTEL_CONTEXT_SCHEDULE_PREEMPTED);
806 i915_request_put(rq);
808 memset(port, 0, sizeof(*port));
812 execlists_user_end(execlists);
815 static void clear_gtiir(struct intel_engine_cs *engine)
817 struct drm_i915_private *dev_priv = engine->i915;
821 * Clear any pending interrupt state.
823 * We do it twice out of paranoia that some of the IIR are
824 * double buffered, and so if we only reset it once there may
825 * still be an interrupt pending.
827 if (INTEL_GEN(dev_priv) >= 11) {
828 static const struct {
832 [RCS] = {0, GEN11_RCS0},
833 [BCS] = {0, GEN11_BCS},
834 [_VCS(0)] = {1, GEN11_VCS(0)},
835 [_VCS(1)] = {1, GEN11_VCS(1)},
836 [_VCS(2)] = {1, GEN11_VCS(2)},
837 [_VCS(3)] = {1, GEN11_VCS(3)},
838 [_VECS(0)] = {1, GEN11_VECS(0)},
839 [_VECS(1)] = {1, GEN11_VECS(1)},
841 unsigned long irqflags;
843 GEM_BUG_ON(engine->id >= ARRAY_SIZE(gen11_gtiir));
845 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
846 for (i = 0; i < 2; i++) {
847 gen11_reset_one_iir(dev_priv,
848 gen11_gtiir[engine->id].bank,
849 gen11_gtiir[engine->id].bit);
851 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
853 static const u8 gtiir[] = {
861 GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
863 for (i = 0; i < 2; i++) {
864 I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
865 engine->irq_keep_mask);
866 POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
868 GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
869 engine->irq_keep_mask);
873 static void reset_irq(struct intel_engine_cs *engine)
875 /* Mark all CS interrupts as complete */
876 smp_store_mb(engine->execlists.active, 0);
877 synchronize_hardirq(engine->i915->drm.irq);
882 * The port is checked prior to scheduling a tasklet, but
883 * just in case we have suspended the tasklet to do the
884 * wedging make sure that when it wakes, it decides there
885 * is no work to do by clearing the irq_posted bit.
887 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
890 static void execlists_cancel_requests(struct intel_engine_cs *engine)
892 struct intel_engine_execlists * const execlists = &engine->execlists;
893 struct i915_request *rq, *rn;
897 GEM_TRACE("%s current %d\n",
898 engine->name, intel_engine_get_seqno(engine));
901 * Before we call engine->cancel_requests(), we should have exclusive
902 * access to the submission state. This is arranged for us by the
903 * caller disabling the interrupt generation, the tasklet and other
904 * threads that may then access the same state, giving us a free hand
905 * to reset state. However, we still need to let lockdep be aware that
906 * we know this state may be accessed in hardirq context, so we
907 * disable the irq around this manipulation and we want to keep
908 * the spinlock focused on its duties and not accidentally conflate
909 * coverage to the submission's irq state. (Similarly, although we
910 * shouldn't need to disable irq around the manipulation of the
911 * submission's irq state, we also wish to remind ourselves that
914 local_irq_save(flags);
916 /* Cancel the requests on the HW and clear the ELSP tracker. */
917 execlists_cancel_port_requests(execlists);
920 spin_lock(&engine->timeline.lock);
922 /* Mark all executing requests as skipped. */
923 list_for_each_entry(rq, &engine->timeline.requests, link) {
924 GEM_BUG_ON(!rq->global_seqno);
925 if (!i915_request_completed(rq))
926 dma_fence_set_error(&rq->fence, -EIO);
929 /* Flush the queued requests to the timeline list (for retiring). */
930 rb = execlists->first;
932 struct i915_priolist *p = to_priolist(rb);
934 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
935 INIT_LIST_HEAD(&rq->sched.link);
937 dma_fence_set_error(&rq->fence, -EIO);
938 __i915_request_submit(rq);
942 rb_erase(&p->node, &execlists->queue);
943 INIT_LIST_HEAD(&p->requests);
944 if (p->priority != I915_PRIORITY_NORMAL)
945 kmem_cache_free(engine->i915->priorities, p);
948 /* Remaining _unready_ requests will be nop'ed when submitted */
950 execlists->queue_priority = INT_MIN;
951 execlists->queue = RB_ROOT;
952 execlists->first = NULL;
953 GEM_BUG_ON(port_isset(execlists->port));
955 spin_unlock(&engine->timeline.lock);
957 local_irq_restore(flags);
960 static void process_csb(struct intel_engine_cs *engine)
962 struct intel_engine_execlists * const execlists = &engine->execlists;
963 struct execlist_port *port = execlists->port;
964 struct drm_i915_private *i915 = engine->i915;
968 /* The HWSP contains a (cacheable) mirror of the CSB */
970 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
971 unsigned int head, tail;
973 /* Clear before reading to catch new interrupts */
974 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
975 smp_mb__after_atomic();
977 if (unlikely(execlists->csb_use_mmio)) {
979 intel_uncore_forcewake_get(i915, execlists->fw_domains);
983 buf = (u32 * __force)
984 (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
986 head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
987 tail = GEN8_CSB_WRITE_PTR(head);
988 head = GEN8_CSB_READ_PTR(head);
989 execlists->csb_head = head;
991 const int write_idx =
992 intel_hws_csb_write_index(i915) -
993 I915_HWS_CSB_BUF0_INDEX;
995 head = execlists->csb_head;
996 tail = READ_ONCE(buf[write_idx]);
997 rmb(); /* Hopefully paired with a wmb() in HW */
999 GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
1001 head, GEN8_CSB_READ_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?",
1002 tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?");
1004 while (head != tail) {
1005 struct i915_request *rq;
1006 unsigned int status;
1009 if (++head == GEN8_CSB_ENTRIES)
1013 * We are flying near dragons again.
1015 * We hold a reference to the request in execlist_port[]
1016 * but no more than that. We are operating in softirq
1017 * context and so cannot hold any mutex or sleep. That
1018 * prevents us stopping the requests we are processing
1019 * in port[] from being retired simultaneously (the
1020 * breadcrumb will be complete before we see the
1021 * context-switch). As we only hold the reference to the
1022 * request, any pointer chasing underneath the request
1023 * is subject to a potential use-after-free. Thus we
1024 * store all of the bookkeeping within port[] as
1025 * required, and avoid using unguarded pointers beneath
1026 * request itself. The same applies to the atomic
1030 status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
1031 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
1033 status, buf[2*head + 1],
1036 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
1037 GEN8_CTX_STATUS_PREEMPTED))
1038 execlists_set_active(execlists,
1039 EXECLISTS_ACTIVE_HWACK);
1040 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
1041 execlists_clear_active(execlists,
1042 EXECLISTS_ACTIVE_HWACK);
1044 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
1047 /* We should never get a COMPLETED | IDLE_ACTIVE! */
1048 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
1050 if (status & GEN8_CTX_STATUS_COMPLETE &&
1051 buf[2*head + 1] == execlists->preempt_complete_status) {
1052 GEM_TRACE("%s preempt-idle\n", engine->name);
1053 complete_preempt_context(execlists);
1057 if (status & GEN8_CTX_STATUS_PREEMPTED &&
1058 execlists_is_active(execlists,
1059 EXECLISTS_ACTIVE_PREEMPT))
1062 GEM_BUG_ON(!execlists_is_active(execlists,
1063 EXECLISTS_ACTIVE_USER));
1065 rq = port_unpack(port, &count);
1066 GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
1068 port->context_id, count,
1069 rq ? rq->global_seqno : 0,
1070 rq ? rq->fence.context : 0,
1071 rq ? rq->fence.seqno : 0,
1072 intel_engine_get_seqno(engine),
1073 rq ? rq_prio(rq) : 0);
1075 /* Check the context/desc id for this event matches */
1076 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
1078 GEM_BUG_ON(count == 0);
1081 * On the final event corresponding to the
1082 * submission of this context, we expect either
1083 * an element-switch event or a completion
1084 * event (and on completion, the active-idle
1085 * marker). No more preemptions, lite-restore
1088 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
1089 GEM_BUG_ON(port_isset(&port[1]) &&
1090 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
1091 GEM_BUG_ON(!port_isset(&port[1]) &&
1092 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
1095 * We rely on the hardware being strongly
1096 * ordered, that the breadcrumb write is
1097 * coherent (visible from the CPU) before the
1098 * user interrupt and CSB is processed.
1100 GEM_BUG_ON(!i915_request_completed(rq));
1102 execlists_context_schedule_out(rq,
1103 INTEL_CONTEXT_SCHEDULE_OUT);
1104 i915_request_put(rq);
1106 GEM_TRACE("%s completed ctx=%d\n",
1107 engine->name, port->context_id);
1109 port = execlists_port_complete(execlists, port);
1110 if (port_isset(port))
1111 execlists_user_begin(execlists, port);
1113 execlists_user_end(execlists);
1115 port_set(port, port_pack(rq, count));
1119 if (head != execlists->csb_head) {
1120 execlists->csb_head = head;
1121 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
1122 i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
1124 } while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted));
1127 intel_uncore_forcewake_put(i915, execlists->fw_domains);
1131 * Check the unread Context Status Buffers and manage the submission of new
1132 * contexts to the ELSP accordingly.
1134 static void execlists_submission_tasklet(unsigned long data)
1136 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1138 GEM_TRACE("%s awake?=%d, active=%x, irq-posted?=%d\n",
1140 engine->i915->gt.awake,
1141 engine->execlists.active,
1142 test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted));
1145 * We can skip acquiring intel_runtime_pm_get() here as it was taken
1146 * on our behalf by the request (see i915_gem_mark_busy()) and it will
1147 * not be relinquished until the device is idle (see
1148 * i915_gem_idle_work_handler()). As a precaution, we make sure
1149 * that all ELSP are drained i.e. we have processed the CSB,
1150 * before allowing ourselves to idle and calling intel_runtime_pm_put().
1152 GEM_BUG_ON(!engine->i915->gt.awake);
1155 * Prefer doing test_and_clear_bit() as a two stage operation to avoid
1156 * imposing the cost of a locked atomic transaction when submitting a
1157 * new request (outside of the context-switch interrupt).
1159 if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted))
1160 process_csb(engine);
1162 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
1163 execlists_dequeue(engine);
1165 /* If the engine is now idle, so should be the flag; and vice versa. */
1166 GEM_BUG_ON(execlists_is_active(&engine->execlists,
1167 EXECLISTS_ACTIVE_USER) ==
1168 !port_isset(engine->execlists.port));
1171 static void queue_request(struct intel_engine_cs *engine,
1172 struct i915_sched_node *node,
1175 list_add_tail(&node->link,
1176 &lookup_priolist(engine, prio)->requests);
1179 static void __submit_queue(struct intel_engine_cs *engine, int prio)
1181 engine->execlists.queue_priority = prio;
1182 tasklet_hi_schedule(&engine->execlists.tasklet);
1185 static void submit_queue(struct intel_engine_cs *engine, int prio)
1187 if (prio > engine->execlists.queue_priority)
1188 __submit_queue(engine, prio);
1191 static void execlists_submit_request(struct i915_request *request)
1193 struct intel_engine_cs *engine = request->engine;
1194 unsigned long flags;
1196 /* Will be called from irq-context when using foreign fences. */
1197 spin_lock_irqsave(&engine->timeline.lock, flags);
1199 queue_request(engine, &request->sched, rq_prio(request));
1200 submit_queue(engine, rq_prio(request));
1202 GEM_BUG_ON(!engine->execlists.first);
1203 GEM_BUG_ON(list_empty(&request->sched.link));
1205 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1208 static struct i915_request *sched_to_request(struct i915_sched_node *node)
1210 return container_of(node, struct i915_request, sched);
1213 static struct intel_engine_cs *
1214 sched_lock_engine(struct i915_sched_node *node, struct intel_engine_cs *locked)
1216 struct intel_engine_cs *engine = sched_to_request(node)->engine;
1218 GEM_BUG_ON(!locked);
1220 if (engine != locked) {
1221 spin_unlock(&locked->timeline.lock);
1222 spin_lock(&engine->timeline.lock);
1228 static void execlists_schedule(struct i915_request *request,
1229 const struct i915_sched_attr *attr)
1231 struct i915_priolist *uninitialized_var(pl);
1232 struct intel_engine_cs *engine, *last;
1233 struct i915_dependency *dep, *p;
1234 struct i915_dependency stack;
1235 const int prio = attr->priority;
1238 GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
1240 if (i915_request_completed(request))
1243 if (prio <= READ_ONCE(request->sched.attr.priority))
1246 /* Need BKL in order to use the temporary link inside i915_dependency */
1247 lockdep_assert_held(&request->i915->drm.struct_mutex);
1249 stack.signaler = &request->sched;
1250 list_add(&stack.dfs_link, &dfs);
1253 * Recursively bump all dependent priorities to match the new request.
1255 * A naive approach would be to use recursion:
1256 * static void update_priorities(struct i915_sched_node *node, prio) {
1257 * list_for_each_entry(dep, &node->signalers_list, signal_link)
1258 * update_priorities(dep->signal, prio)
1259 * queue_request(node);
1261 * but that may have unlimited recursion depth and so runs a very
1262 * real risk of overunning the kernel stack. Instead, we build
1263 * a flat list of all dependencies starting with the current request.
1264 * As we walk the list of dependencies, we add all of its dependencies
1265 * to the end of the list (this may include an already visited
1266 * request) and continue to walk onwards onto the new dependencies. The
1267 * end result is a topological list of requests in reverse order, the
1268 * last element in the list is the request we must execute first.
1270 list_for_each_entry(dep, &dfs, dfs_link) {
1271 struct i915_sched_node *node = dep->signaler;
1274 * Within an engine, there can be no cycle, but we may
1275 * refer to the same dependency chain multiple times
1276 * (redundant dependencies are not eliminated) and across
1279 list_for_each_entry(p, &node->signalers_list, signal_link) {
1280 GEM_BUG_ON(p == dep); /* no cycles! */
1282 if (i915_sched_node_signaled(p->signaler))
1285 GEM_BUG_ON(p->signaler->attr.priority < node->attr.priority);
1286 if (prio > READ_ONCE(p->signaler->attr.priority))
1287 list_move_tail(&p->dfs_link, &dfs);
1292 * If we didn't need to bump any existing priorities, and we haven't
1293 * yet submitted this request (i.e. there is no potential race with
1294 * execlists_submit_request()), we can set our own priority and skip
1295 * acquiring the engine locks.
1297 if (request->sched.attr.priority == I915_PRIORITY_INVALID) {
1298 GEM_BUG_ON(!list_empty(&request->sched.link));
1299 request->sched.attr = *attr;
1300 if (stack.dfs_link.next == stack.dfs_link.prev)
1302 __list_del_entry(&stack.dfs_link);
1306 engine = request->engine;
1307 spin_lock_irq(&engine->timeline.lock);
1309 /* Fifo and depth-first replacement ensure our deps execute before us */
1310 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
1311 struct i915_sched_node *node = dep->signaler;
1313 INIT_LIST_HEAD(&dep->dfs_link);
1315 engine = sched_lock_engine(node, engine);
1317 if (prio <= node->attr.priority)
1320 node->attr.priority = prio;
1321 if (!list_empty(&node->link)) {
1322 if (last != engine) {
1323 pl = lookup_priolist(engine, prio);
1326 GEM_BUG_ON(pl->priority != prio);
1327 list_move_tail(&node->link, &pl->requests);
1330 if (prio > engine->execlists.queue_priority &&
1331 i915_sw_fence_done(&sched_to_request(node)->submit))
1332 __submit_queue(engine, prio);
1335 spin_unlock_irq(&engine->timeline.lock);
1338 static void execlists_context_destroy(struct intel_context *ce)
1340 GEM_BUG_ON(!ce->state);
1341 GEM_BUG_ON(ce->pin_count);
1343 intel_ring_free(ce->ring);
1344 __i915_gem_object_release_unless_active(ce->state->obj);
1347 static void execlists_context_unpin(struct intel_context *ce)
1349 intel_ring_unpin(ce->ring);
1351 ce->state->obj->pin_global--;
1352 i915_gem_object_unpin_map(ce->state->obj);
1353 i915_vma_unpin(ce->state);
1355 i915_gem_context_put(ce->gem_context);
1358 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1364 * Clear this page out of any CPU caches for coherent swap-in/out.
1365 * We only want to do this on the first bind so that we do not stall
1366 * on an active context (which by nature is already on the GPU).
1368 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1369 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1374 flags = PIN_GLOBAL | PIN_HIGH;
1375 if (ctx->ggtt_offset_bias)
1376 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
1378 return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
1381 static struct intel_context *
1382 __execlists_context_pin(struct intel_engine_cs *engine,
1383 struct i915_gem_context *ctx,
1384 struct intel_context *ce)
1389 ret = execlists_context_deferred_alloc(ctx, engine, ce);
1392 GEM_BUG_ON(!ce->state);
1394 ret = __context_pin(ctx, ce->state);
1398 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
1399 if (IS_ERR(vaddr)) {
1400 ret = PTR_ERR(vaddr);
1404 ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
1408 intel_lr_context_descriptor_update(ctx, engine, ce);
1410 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1411 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1412 i915_ggtt_offset(ce->ring->vma);
1413 GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
1414 ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
1416 ce->state->obj->pin_global++;
1417 i915_gem_context_get(ctx);
1421 i915_gem_object_unpin_map(ce->state->obj);
1423 __i915_vma_unpin(ce->state);
1426 return ERR_PTR(ret);
1429 static const struct intel_context_ops execlists_context_ops = {
1430 .unpin = execlists_context_unpin,
1431 .destroy = execlists_context_destroy,
1434 static struct intel_context *
1435 execlists_context_pin(struct intel_engine_cs *engine,
1436 struct i915_gem_context *ctx)
1438 struct intel_context *ce = to_intel_context(ctx, engine);
1440 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1442 if (likely(ce->pin_count++))
1444 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1446 ce->ops = &execlists_context_ops;
1448 return __execlists_context_pin(engine, ctx, ce);
1451 static int execlists_request_alloc(struct i915_request *request)
1455 GEM_BUG_ON(!request->hw_context->pin_count);
1457 /* Flush enough space to reduce the likelihood of waiting after
1458 * we start building the request - in which case we will just
1459 * have to repeat work.
1461 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1463 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1467 /* Note that after this point, we have committed to using
1468 * this request as it is being used to both track the
1469 * state of engine initialisation and liveness of the
1470 * golden renderstate above. Think twice before you try
1471 * to cancel/unwind this request now.
1474 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1479 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1480 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1481 * but there is a slight complication as this is applied in WA batch where the
1482 * values are only initialized once so we cannot take register value at the
1483 * beginning and reuse it further; hence we save its value to memory, upload a
1484 * constant value with bit21 set and then we restore it back with the saved value.
1485 * To simplify the WA, a constant value is formed by using the default value
1486 * of this register. This shouldn't be a problem because we are only modifying
1487 * it for a short period and this batch in non-premptible. We can ofcourse
1488 * use additional instructions that read the actual value of the register
1489 * at that time and set our bit of interest but it makes the WA complicated.
1491 * This WA is also required for Gen9 so extracting as a function avoids
1495 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1497 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1498 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1499 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1502 *batch++ = MI_LOAD_REGISTER_IMM(1);
1503 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1504 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1506 batch = gen8_emit_pipe_control(batch,
1507 PIPE_CONTROL_CS_STALL |
1508 PIPE_CONTROL_DC_FLUSH_ENABLE,
1511 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1512 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1513 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1520 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1521 * initialized at the beginning and shared across all contexts but this field
1522 * helps us to have multiple batches at different offsets and select them based
1523 * on a criteria. At the moment this batch always start at the beginning of the page
1524 * and at this point we don't have multiple wa_ctx batch buffers.
1526 * The number of WA applied are not known at the beginning; we use this field
1527 * to return the no of DWORDS written.
1529 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1530 * so it adds NOOPs as padding to make it cacheline aligned.
1531 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1532 * makes a complete batch buffer.
1534 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1536 /* WaDisableCtxRestoreArbitration:bdw,chv */
1537 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1539 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1540 if (IS_BROADWELL(engine->i915))
1541 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1543 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1544 /* Actual scratch location is at 128 bytes offset */
1545 batch = gen8_emit_pipe_control(batch,
1546 PIPE_CONTROL_FLUSH_L3 |
1547 PIPE_CONTROL_GLOBAL_GTT_IVB |
1548 PIPE_CONTROL_CS_STALL |
1549 PIPE_CONTROL_QW_WRITE,
1550 i915_ggtt_offset(engine->scratch) +
1551 2 * CACHELINE_BYTES);
1553 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1555 /* Pad to end of cacheline */
1556 while ((unsigned long)batch % CACHELINE_BYTES)
1560 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1561 * execution depends on the length specified in terms of cache lines
1562 * in the register CTX_RCS_INDIRECT_CTX
1573 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1575 GEM_BUG_ON(!count || count > 63);
1577 *batch++ = MI_LOAD_REGISTER_IMM(count);
1579 *batch++ = i915_mmio_reg_offset(lri->reg);
1580 *batch++ = lri->value;
1581 } while (lri++, --count);
1587 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1589 static const struct lri lri[] = {
1590 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1592 COMMON_SLICE_CHICKEN2,
1593 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1600 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1601 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1607 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1608 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1612 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1614 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1615 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1617 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1619 /* WaClearSlmSpaceAtContextSwitch:kbl */
1620 /* Actual scratch location is at 128 bytes offset */
1621 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1622 batch = gen8_emit_pipe_control(batch,
1623 PIPE_CONTROL_FLUSH_L3 |
1624 PIPE_CONTROL_GLOBAL_GTT_IVB |
1625 PIPE_CONTROL_CS_STALL |
1626 PIPE_CONTROL_QW_WRITE,
1627 i915_ggtt_offset(engine->scratch)
1628 + 2 * CACHELINE_BYTES);
1631 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1632 if (HAS_POOLED_EU(engine->i915)) {
1634 * EU pool configuration is setup along with golden context
1635 * during context initialization. This value depends on
1636 * device type (2x6 or 3x6) and needs to be updated based
1637 * on which subslice is disabled especially for 2x6
1638 * devices, however it is safe to load default
1639 * configuration of 3x6 device instead of masking off
1640 * corresponding bits because HW ignores bits of a disabled
1641 * subslice and drops down to appropriate config. Please
1642 * see render_state_setup() in i915_gem_render_state.c for
1643 * possible configurations, to avoid duplication they are
1644 * not shown here again.
1646 *batch++ = GEN9_MEDIA_POOL_STATE;
1647 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1648 *batch++ = 0x00777000;
1654 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1656 /* Pad to end of cacheline */
1657 while ((unsigned long)batch % CACHELINE_BYTES)
1664 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1669 * WaPipeControlBefore3DStateSamplePattern: cnl
1671 * Ensure the engine is idle prior to programming a
1672 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1674 batch = gen8_emit_pipe_control(batch,
1675 PIPE_CONTROL_CS_STALL,
1678 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1679 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1680 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1681 * confusing. Since gen8_emit_pipe_control() already advances the
1682 * batch by 6 dwords, we advance the other 10 here, completing a
1683 * cacheline. It's not clear if the workaround requires this padding
1684 * before other commands, or if it's just the regular padding we would
1685 * already have for the workaround bb, so leave it here for now.
1687 for (i = 0; i < 10; i++)
1690 /* Pad to end of cacheline */
1691 while ((unsigned long)batch % CACHELINE_BYTES)
1697 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1699 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1701 struct drm_i915_gem_object *obj;
1702 struct i915_vma *vma;
1705 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1707 return PTR_ERR(obj);
1709 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
1715 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1719 engine->wa_ctx.vma = vma;
1723 i915_gem_object_put(obj);
1727 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1729 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1732 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1734 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1736 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1737 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1739 wa_bb_func_t wa_bb_fn[2];
1741 void *batch, *batch_ptr;
1745 if (GEM_WARN_ON(engine->id != RCS))
1748 switch (INTEL_GEN(engine->i915)) {
1752 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1756 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1760 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1764 MISSING_CASE(INTEL_GEN(engine->i915));
1768 ret = lrc_setup_wa_ctx(engine);
1770 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1774 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1775 batch = batch_ptr = kmap_atomic(page);
1778 * Emit the two workaround batch buffers, recording the offset from the
1779 * start of the workaround batch buffer object for each and their
1782 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1783 wa_bb[i]->offset = batch_ptr - batch;
1784 if (GEM_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1785 CACHELINE_BYTES))) {
1790 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1791 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1794 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1796 kunmap_atomic(batch);
1798 lrc_destroy_wa_ctx(engine);
1803 static void enable_execlists(struct intel_engine_cs *engine)
1805 struct drm_i915_private *dev_priv = engine->i915;
1807 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1810 * Make sure we're not enabling the new 12-deep CSB
1811 * FIFO as that requires a slightly updated handling
1812 * in the ctx switch irq. Since we're currently only
1813 * using only 2 elements of the enhanced execlists the
1814 * deeper FIFO it's not needed and it's not worth adding
1815 * more statements to the irq handler to support it.
1817 if (INTEL_GEN(dev_priv) >= 11)
1818 I915_WRITE(RING_MODE_GEN7(engine),
1819 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1821 I915_WRITE(RING_MODE_GEN7(engine),
1822 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1824 I915_WRITE(RING_MI_MODE(engine->mmio_base),
1825 _MASKED_BIT_DISABLE(STOP_RING));
1827 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1828 engine->status_page.ggtt_offset);
1829 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1832 static bool unexpected_starting_state(struct intel_engine_cs *engine)
1834 struct drm_i915_private *dev_priv = engine->i915;
1835 bool unexpected = false;
1837 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
1838 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
1845 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1849 ret = intel_mocs_init_engine(engine);
1853 intel_engine_reset_breadcrumbs(engine);
1854 intel_engine_init_hangcheck(engine);
1856 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
1857 struct drm_printer p = drm_debug_printer(__func__);
1859 intel_engine_dump(engine, &p, NULL);
1862 enable_execlists(engine);
1867 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1869 struct drm_i915_private *dev_priv = engine->i915;
1872 ret = gen8_init_common_ring(engine);
1876 intel_whitelist_workarounds_apply(engine);
1878 /* We need to disable the AsyncFlip performance optimisations in order
1879 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1880 * programmed to '1' on all products.
1882 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1884 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1886 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1891 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1895 ret = gen8_init_common_ring(engine);
1899 intel_whitelist_workarounds_apply(engine);
1904 static struct i915_request *
1905 execlists_reset_prepare(struct intel_engine_cs *engine)
1907 struct intel_engine_execlists * const execlists = &engine->execlists;
1908 struct i915_request *request, *active;
1910 GEM_TRACE("%s\n", engine->name);
1913 * Prevent request submission to the hardware until we have
1914 * completed the reset in i915_gem_reset_finish(). If a request
1915 * is completed by one engine, it may then queue a request
1916 * to a second via its execlists->tasklet *just* as we are
1917 * calling engine->init_hw() and also writing the ELSP.
1918 * Turning off the execlists->tasklet until the reset is over
1919 * prevents the race.
1921 __tasklet_disable_sync_once(&execlists->tasklet);
1924 * We want to flush the pending context switches, having disabled
1925 * the tasklet above, we can assume exclusive access to the execlists.
1926 * For this allows us to catch up with an inflight preemption event,
1927 * and avoid blaming an innocent request if the stall was due to the
1928 * preemption itself.
1930 if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted))
1931 process_csb(engine);
1934 * The last active request can then be no later than the last request
1935 * now in ELSP[0]. So search backwards from there, so that if the GPU
1936 * has advanced beyond the last CSB update, it will be pardoned.
1939 request = port_request(execlists->port);
1941 unsigned long flags;
1944 * Prevent the breadcrumb from advancing before we decide
1945 * which request is currently active.
1947 intel_engine_stop_cs(engine);
1949 spin_lock_irqsave(&engine->timeline.lock, flags);
1950 list_for_each_entry_from_reverse(request,
1951 &engine->timeline.requests,
1953 if (__i915_request_completed(request,
1954 request->global_seqno))
1959 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1965 static void execlists_reset(struct intel_engine_cs *engine,
1966 struct i915_request *request)
1968 struct intel_engine_execlists * const execlists = &engine->execlists;
1969 unsigned long flags;
1972 GEM_TRACE("%s request global=%x, current=%d\n",
1973 engine->name, request ? request->global_seqno : 0,
1974 intel_engine_get_seqno(engine));
1976 /* See execlists_cancel_requests() for the irq/spinlock split. */
1977 local_irq_save(flags);
1980 * Catch up with any missed context-switch interrupts.
1982 * Ideally we would just read the remaining CSB entries now that we
1983 * know the gpu is idle. However, the CSB registers are sometimes^W
1984 * often trashed across a GPU reset! Instead we have to rely on
1985 * guessing the missed context-switch events by looking at what
1986 * requests were completed.
1988 execlists_cancel_port_requests(execlists);
1991 /* Push back any incomplete requests for replay after the reset. */
1992 spin_lock(&engine->timeline.lock);
1993 __unwind_incomplete_requests(engine);
1994 spin_unlock(&engine->timeline.lock);
1996 /* Following the reset, we need to reload the CSB read/write pointers */
1997 engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
1999 local_irq_restore(flags);
2002 * If the request was innocent, we leave the request in the ELSP
2003 * and will try to replay it on restarting. The context image may
2004 * have been corrupted by the reset, in which case we may have
2005 * to service a new GPU hang, but more likely we can continue on
2008 * If the request was guilty, we presume the context is corrupt
2009 * and have to at least restore the RING register in the context
2010 * image back to the expected values to skip over the guilty request.
2012 if (!request || request->fence.error != -EIO)
2016 * We want a simple context + ring to execute the breadcrumb update.
2017 * We cannot rely on the context being intact across the GPU hang,
2018 * so clear it and rebuild just what we need for the breadcrumb.
2019 * All pending requests for this context will be zapped, and any
2020 * future request will be after userspace has had the opportunity
2021 * to recreate its own state.
2023 regs = request->hw_context->lrc_reg_state;
2024 if (engine->pinned_default_state) {
2025 memcpy(regs, /* skip restoring the vanilla PPHWSP */
2026 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
2027 engine->context_size - PAGE_SIZE);
2029 execlists_init_reg_state(regs,
2030 request->gem_context, engine, request->ring);
2032 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
2033 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
2035 request->ring->head = intel_ring_wrap(request->ring, request->postfix);
2036 regs[CTX_RING_HEAD + 1] = request->ring->head;
2038 intel_ring_update_space(request->ring);
2040 /* Reset WaIdleLiteRestore:bdw,skl as well */
2041 unwind_wa_tail(request);
2044 static void execlists_reset_finish(struct intel_engine_cs *engine)
2046 struct intel_engine_execlists * const execlists = &engine->execlists;
2048 /* After a GPU reset, we may have requests to replay */
2049 if (execlists->first)
2050 tasklet_schedule(&execlists->tasklet);
2053 * Flush the tasklet while we still have the forcewake to be sure
2054 * that it is not allowed to sleep before we restart and reload a
2057 * As before (with execlists_reset_prepare) we rely on the caller
2058 * serialising multiple attempts to reset so that we know that we
2059 * are the only one manipulating tasklet state.
2061 __tasklet_enable_sync_once(&execlists->tasklet);
2063 GEM_TRACE("%s\n", engine->name);
2066 static int intel_logical_ring_emit_pdps(struct i915_request *rq)
2068 struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
2069 struct intel_engine_cs *engine = rq->engine;
2070 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
2074 cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2);
2078 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
2079 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
2080 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
2082 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
2083 *cs++ = upper_32_bits(pd_daddr);
2084 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
2085 *cs++ = lower_32_bits(pd_daddr);
2089 intel_ring_advance(rq, cs);
2094 static int gen8_emit_bb_start(struct i915_request *rq,
2095 u64 offset, u32 len,
2096 const unsigned int flags)
2101 /* Don't rely in hw updating PDPs, specially in lite-restore.
2102 * Ideally, we should set Force PD Restore in ctx descriptor,
2103 * but we can't. Force Restore would be a second option, but
2104 * it is unsafe in case of lite-restore (because the ctx is
2105 * not idle). PML4 is allocated during ppgtt init so this is
2106 * not needed in 48-bit.*/
2107 if (rq->gem_context->ppgtt &&
2108 (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
2109 !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
2110 !intel_vgpu_active(rq->i915)) {
2111 ret = intel_logical_ring_emit_pdps(rq);
2115 rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
2118 cs = intel_ring_begin(rq, 6);
2123 * WaDisableCtxRestoreArbitration:bdw,chv
2125 * We don't need to perform MI_ARB_ENABLE as often as we do (in
2126 * particular all the gen that do not need the w/a at all!), if we
2127 * took care to make sure that on every switch into this context
2128 * (both ordinary and for preemption) that arbitrartion was enabled
2129 * we would be fine. However, there doesn't seem to be a downside to
2130 * being paranoid and making sure it is set before each batch and
2131 * every context-switch.
2133 * Note that if we fail to enable arbitration before the request
2134 * is complete, then we do not see the context-switch interrupt and
2135 * the engine hangs (with RING_HEAD == RING_TAIL).
2137 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
2139 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2141 /* FIXME(BDW): Address space and security selectors. */
2142 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2143 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
2144 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
2145 *cs++ = lower_32_bits(offset);
2146 *cs++ = upper_32_bits(offset);
2148 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2150 intel_ring_advance(rq, cs);
2155 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
2157 struct drm_i915_private *dev_priv = engine->i915;
2158 I915_WRITE_IMR(engine,
2159 ~(engine->irq_enable_mask | engine->irq_keep_mask));
2160 POSTING_READ_FW(RING_IMR(engine->mmio_base));
2163 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
2165 struct drm_i915_private *dev_priv = engine->i915;
2166 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
2169 static int gen8_emit_flush(struct i915_request *request, u32 mode)
2173 cs = intel_ring_begin(request, 4);
2177 cmd = MI_FLUSH_DW + 1;
2179 /* We always require a command barrier so that subsequent
2180 * commands, such as breadcrumb interrupts, are strictly ordered
2181 * wrt the contents of the write cache being flushed to memory
2182 * (and thus being coherent from the CPU).
2184 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2186 if (mode & EMIT_INVALIDATE) {
2187 cmd |= MI_INVALIDATE_TLB;
2188 if (request->engine->id == VCS)
2189 cmd |= MI_INVALIDATE_BSD;
2193 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2194 *cs++ = 0; /* upper addr */
2195 *cs++ = 0; /* value */
2196 intel_ring_advance(request, cs);
2201 static int gen8_emit_flush_render(struct i915_request *request,
2204 struct intel_engine_cs *engine = request->engine;
2206 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
2207 bool vf_flush_wa = false, dc_flush_wa = false;
2211 flags |= PIPE_CONTROL_CS_STALL;
2213 if (mode & EMIT_FLUSH) {
2214 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2215 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2216 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2217 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2220 if (mode & EMIT_INVALIDATE) {
2221 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2222 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2223 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2224 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2225 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2226 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2227 flags |= PIPE_CONTROL_QW_WRITE;
2228 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2231 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2234 if (IS_GEN9(request->i915))
2237 /* WaForGAMHang:kbl */
2238 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2250 cs = intel_ring_begin(request, len);
2255 cs = gen8_emit_pipe_control(cs, 0, 0);
2258 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2261 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2264 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2266 intel_ring_advance(request, cs);
2272 * Reserve space for 2 NOOPs at the end of each request to be
2273 * used as a workaround for not being allowed to do lite
2274 * restore with HEAD==TAIL (WaIdleLiteRestore).
2276 static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2278 /* Ensure there's always at least one preemption point per-request. */
2279 *cs++ = MI_ARB_CHECK;
2281 request->wa_tail = intel_ring_offset(request, cs);
2284 static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
2286 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
2287 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
2289 cs = gen8_emit_ggtt_write(cs, request->global_seqno,
2290 intel_hws_seqno_address(request->engine));
2291 *cs++ = MI_USER_INTERRUPT;
2292 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2293 request->tail = intel_ring_offset(request, cs);
2294 assert_ring_tail_valid(request->ring, request->tail);
2296 gen8_emit_wa_tail(request, cs);
2298 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
2300 static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2302 /* We're using qword write, seqno should be aligned to 8 bytes. */
2303 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
2305 cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
2306 intel_hws_seqno_address(request->engine));
2307 *cs++ = MI_USER_INTERRUPT;
2308 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2309 request->tail = intel_ring_offset(request, cs);
2310 assert_ring_tail_valid(request->ring, request->tail);
2312 gen8_emit_wa_tail(request, cs);
2314 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
2316 static int gen8_init_rcs_context(struct i915_request *rq)
2320 ret = intel_ctx_workarounds_emit(rq);
2324 ret = intel_rcs_context_init_mocs(rq);
2326 * Failing to program the MOCS is non-fatal.The system will not
2327 * run at peak performance. So generate an error and carry on.
2330 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2332 return i915_gem_render_state_emit(rq);
2336 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2337 * @engine: Engine Command Streamer.
2339 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2341 struct drm_i915_private *dev_priv;
2344 * Tasklet cannot be active at this point due intel_mark_active/idle
2345 * so this is just for documentation.
2347 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
2348 &engine->execlists.tasklet.state)))
2349 tasklet_kill(&engine->execlists.tasklet);
2351 dev_priv = engine->i915;
2353 if (engine->buffer) {
2354 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2357 if (engine->cleanup)
2358 engine->cleanup(engine);
2360 intel_engine_cleanup_common(engine);
2362 lrc_destroy_wa_ctx(engine);
2364 engine->i915 = NULL;
2365 dev_priv->engine[engine->id] = NULL;
2369 static void execlists_set_default_submission(struct intel_engine_cs *engine)
2371 engine->submit_request = execlists_submit_request;
2372 engine->cancel_requests = execlists_cancel_requests;
2373 engine->schedule = execlists_schedule;
2374 engine->execlists.tasklet.func = execlists_submission_tasklet;
2376 engine->reset.prepare = execlists_reset_prepare;
2378 engine->park = NULL;
2379 engine->unpark = NULL;
2381 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2382 if (engine->i915->preempt_context)
2383 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2385 engine->i915->caps.scheduler =
2386 I915_SCHEDULER_CAP_ENABLED |
2387 I915_SCHEDULER_CAP_PRIORITY;
2388 if (intel_engine_has_preemption(engine))
2389 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
2393 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2395 /* Default vfuncs which can be overriden by each engine. */
2396 engine->init_hw = gen8_init_common_ring;
2398 engine->reset.prepare = execlists_reset_prepare;
2399 engine->reset.reset = execlists_reset;
2400 engine->reset.finish = execlists_reset_finish;
2402 engine->context_pin = execlists_context_pin;
2403 engine->request_alloc = execlists_request_alloc;
2405 engine->emit_flush = gen8_emit_flush;
2406 engine->emit_breadcrumb = gen8_emit_breadcrumb;
2407 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
2409 engine->set_default_submission = execlists_set_default_submission;
2411 if (INTEL_GEN(engine->i915) < 11) {
2412 engine->irq_enable = gen8_logical_ring_enable_irq;
2413 engine->irq_disable = gen8_logical_ring_disable_irq;
2416 * TODO: On Gen11 interrupt masks need to be clear
2417 * to allow C6 entry. Keep interrupts enabled at
2418 * and take the hit of generating extra interrupts
2419 * until a more refined solution exists.
2422 engine->emit_bb_start = gen8_emit_bb_start;
2426 logical_ring_default_irqs(struct intel_engine_cs *engine)
2428 unsigned int shift = 0;
2430 if (INTEL_GEN(engine->i915) < 11) {
2431 const u8 irq_shifts[] = {
2432 [RCS] = GEN8_RCS_IRQ_SHIFT,
2433 [BCS] = GEN8_BCS_IRQ_SHIFT,
2434 [VCS] = GEN8_VCS1_IRQ_SHIFT,
2435 [VCS2] = GEN8_VCS2_IRQ_SHIFT,
2436 [VECS] = GEN8_VECS_IRQ_SHIFT,
2439 shift = irq_shifts[engine->id];
2442 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2443 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2447 logical_ring_setup(struct intel_engine_cs *engine)
2449 struct drm_i915_private *dev_priv = engine->i915;
2450 enum forcewake_domains fw_domains;
2452 intel_engine_setup_common(engine);
2454 /* Intentionally left blank. */
2455 engine->buffer = NULL;
2457 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
2461 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2462 RING_CONTEXT_STATUS_PTR(engine),
2463 FW_REG_READ | FW_REG_WRITE);
2465 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2466 RING_CONTEXT_STATUS_BUF_BASE(engine),
2469 engine->execlists.fw_domains = fw_domains;
2471 tasklet_init(&engine->execlists.tasklet,
2472 execlists_submission_tasklet, (unsigned long)engine);
2474 logical_ring_default_vfuncs(engine);
2475 logical_ring_default_irqs(engine);
2478 static int logical_ring_init(struct intel_engine_cs *engine)
2482 ret = intel_engine_init_common(engine);
2486 if (HAS_LOGICAL_RING_ELSQ(engine->i915)) {
2487 engine->execlists.submit_reg = engine->i915->regs +
2488 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
2489 engine->execlists.ctrl_reg = engine->i915->regs +
2490 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
2492 engine->execlists.submit_reg = engine->i915->regs +
2493 i915_mmio_reg_offset(RING_ELSP(engine));
2496 engine->execlists.preempt_complete_status = ~0u;
2497 if (engine->i915->preempt_context) {
2498 struct intel_context *ce =
2499 to_intel_context(engine->i915->preempt_context, engine);
2501 engine->execlists.preempt_complete_status =
2502 upper_32_bits(ce->lrc_desc);
2505 engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
2510 intel_logical_ring_cleanup(engine);
2514 int logical_render_ring_init(struct intel_engine_cs *engine)
2516 struct drm_i915_private *dev_priv = engine->i915;
2519 logical_ring_setup(engine);
2521 if (HAS_L3_DPF(dev_priv))
2522 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2524 /* Override some for render ring. */
2525 if (INTEL_GEN(dev_priv) >= 9)
2526 engine->init_hw = gen9_init_render_ring;
2528 engine->init_hw = gen8_init_render_ring;
2529 engine->init_context = gen8_init_rcs_context;
2530 engine->emit_flush = gen8_emit_flush_render;
2531 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2532 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2534 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2538 ret = intel_init_workaround_bb(engine);
2541 * We continue even if we fail to initialize WA batch
2542 * because we only expect rare glitches but nothing
2543 * critical to prevent us from using GPU
2545 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2549 return logical_ring_init(engine);
2552 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2554 logical_ring_setup(engine);
2556 return logical_ring_init(engine);
2560 make_rpcs(struct drm_i915_private *dev_priv)
2565 * No explicit RPCS request is needed to ensure full
2566 * slice/subslice/EU enablement prior to Gen9.
2568 if (INTEL_GEN(dev_priv) < 9)
2572 * Starting in Gen9, render power gating can leave
2573 * slice/subslice/EU in a partially enabled state. We
2574 * must make an explicit request through RPCS for full
2577 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2578 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2579 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
2580 GEN8_RPCS_S_CNT_SHIFT;
2581 rpcs |= GEN8_RPCS_ENABLE;
2584 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
2585 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2586 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) <<
2587 GEN8_RPCS_SS_CNT_SHIFT;
2588 rpcs |= GEN8_RPCS_ENABLE;
2591 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2592 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2593 GEN8_RPCS_EU_MIN_SHIFT;
2594 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2595 GEN8_RPCS_EU_MAX_SHIFT;
2596 rpcs |= GEN8_RPCS_ENABLE;
2602 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2604 u32 indirect_ctx_offset;
2606 switch (INTEL_GEN(engine->i915)) {
2608 MISSING_CASE(INTEL_GEN(engine->i915));
2611 indirect_ctx_offset =
2612 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2615 indirect_ctx_offset =
2616 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2619 indirect_ctx_offset =
2620 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2623 indirect_ctx_offset =
2624 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2628 return indirect_ctx_offset;
2631 static void execlists_init_reg_state(u32 *regs,
2632 struct i915_gem_context *ctx,
2633 struct intel_engine_cs *engine,
2634 struct intel_ring *ring)
2636 struct drm_i915_private *dev_priv = engine->i915;
2637 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2638 u32 base = engine->mmio_base;
2639 bool rcs = engine->class == RENDER_CLASS;
2641 /* A context is actually a big batch buffer with several
2642 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2643 * values we are setting here are only for the first context restore:
2644 * on a subsequent save, the GPU will recreate this batchbuffer with new
2645 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2646 * we are not initializing here).
2648 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2649 MI_LRI_FORCE_POSTED;
2651 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2652 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2653 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT) |
2654 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2655 (HAS_RESOURCE_STREAMER(dev_priv) ?
2656 CTX_CTRL_RS_CTX_ENABLE : 0)));
2657 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2658 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2659 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2660 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2661 RING_CTL_SIZE(ring->size) | RING_VALID);
2662 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2663 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2664 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2665 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2666 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2667 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2669 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2671 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2672 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2673 RING_INDIRECT_CTX_OFFSET(base), 0);
2674 if (wa_ctx->indirect_ctx.size) {
2675 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2677 regs[CTX_RCS_INDIRECT_CTX + 1] =
2678 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2679 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2681 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2682 intel_lr_indirect_ctx_offset(engine) << 6;
2685 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2686 if (wa_ctx->per_ctx.size) {
2687 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2689 regs[CTX_BB_PER_CTX_PTR + 1] =
2690 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2694 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2696 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2697 /* PDP values well be assigned later if needed */
2698 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2699 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2700 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2701 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2702 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2703 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2704 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2705 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2707 if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
2708 /* 64b PPGTT (48bit canonical)
2709 * PDP0_DESCRIPTOR contains the base address to PML4 and
2710 * other PDP Descriptors are ignored.
2712 ASSIGN_CTX_PML4(ppgtt, regs);
2716 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2717 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2718 make_rpcs(dev_priv));
2720 i915_oa_init_reg_state(engine, ctx, regs);
2725 populate_lr_context(struct i915_gem_context *ctx,
2726 struct drm_i915_gem_object *ctx_obj,
2727 struct intel_engine_cs *engine,
2728 struct intel_ring *ring)
2734 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2736 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2740 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2741 if (IS_ERR(vaddr)) {
2742 ret = PTR_ERR(vaddr);
2743 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2746 ctx_obj->mm.dirty = true;
2748 if (engine->default_state) {
2750 * We only want to copy over the template context state;
2751 * skipping over the headers reserved for GuC communication,
2752 * leaving those as zero.
2754 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2757 defaults = i915_gem_object_pin_map(engine->default_state,
2759 if (IS_ERR(defaults)) {
2760 ret = PTR_ERR(defaults);
2764 memcpy(vaddr + start, defaults + start, engine->context_size);
2765 i915_gem_object_unpin_map(engine->default_state);
2768 /* The second page of the context object contains some fields which must
2769 * be set up prior to the first execution. */
2770 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2771 execlists_init_reg_state(regs, ctx, engine, ring);
2772 if (!engine->default_state)
2773 regs[CTX_CONTEXT_CONTROL + 1] |=
2774 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2775 if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
2776 regs[CTX_CONTEXT_CONTROL + 1] |=
2777 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2778 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2781 i915_gem_object_unpin_map(ctx_obj);
2785 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2786 struct intel_engine_cs *engine,
2787 struct intel_context *ce)
2789 struct drm_i915_gem_object *ctx_obj;
2790 struct i915_vma *vma;
2791 uint32_t context_size;
2792 struct intel_ring *ring;
2793 struct i915_timeline *timeline;
2799 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2802 * Before the actual start of the context image, we insert a few pages
2803 * for our own use and for sharing with the GuC.
2805 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2807 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2808 if (IS_ERR(ctx_obj))
2809 return PTR_ERR(ctx_obj);
2811 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.vm, NULL);
2814 goto error_deref_obj;
2817 timeline = i915_timeline_create(ctx->i915, ctx->name);
2818 if (IS_ERR(timeline)) {
2819 ret = PTR_ERR(timeline);
2820 goto error_deref_obj;
2823 ring = intel_engine_create_ring(engine, timeline, ctx->ring_size);
2824 i915_timeline_put(timeline);
2826 ret = PTR_ERR(ring);
2827 goto error_deref_obj;
2830 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2832 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2833 goto error_ring_free;
2842 intel_ring_free(ring);
2844 i915_gem_object_put(ctx_obj);
2848 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2850 struct intel_engine_cs *engine;
2851 struct i915_gem_context *ctx;
2852 enum intel_engine_id id;
2854 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2855 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2856 * that stored in context. As we only write new commands from
2857 * ce->ring->tail onwards, everything before that is junk. If the GPU
2858 * starts reading from its RING_HEAD from the context, it may try to
2859 * execute that junk and die.
2861 * So to avoid that we reset the context images upon resume. For
2862 * simplicity, we just zero everything out.
2864 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
2865 for_each_engine(engine, dev_priv, id) {
2866 struct intel_context *ce =
2867 to_intel_context(ctx, engine);
2873 reg = i915_gem_object_pin_map(ce->state->obj,
2875 if (WARN_ON(IS_ERR(reg)))
2878 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2879 reg[CTX_RING_HEAD+1] = 0;
2880 reg[CTX_RING_TAIL+1] = 0;
2882 ce->state->obj->mm.dirty = true;
2883 i915_gem_object_unpin_map(ce->state->obj);
2885 intel_ring_reset(ce->ring, 0);
2890 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2891 #include "selftests/intel_lrc.c"