drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pc8.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pc8.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pc8.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pc8.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pc8.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pc8.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         u32 reg = PIPESTAT(pipe);
 239         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 240
 241         assert_spin_locked(&dev_priv->irq_lock);
 242
 243         I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 244         POSTING_READ(reg);
 245 }
 246
 247 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 248                                                  enum pipe pipe, bool enable)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 252                                           DE_PIPEB_FIFO_UNDERRUN;
 253
 254         if (enable)
 255                 ironlake_enable_display_irq(dev_priv, bit);
 256         else
 257                 ironlake_disable_display_irq(dev_priv, bit);
 258 }
 259
 260 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 261                                                   enum pipe pipe, bool enable)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         if (enable) {
 265                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 266
 267                 if (!ivb_can_enable_err_int(dev))
 268                         return;
 269
 270                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 271         } else {
 272                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 273
 274                 /* Change the state _after_ we've read out the current one. */
 275                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 276
 277                 if (!was_enabled &&
 278                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 279                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 280                                       pipe_name(pipe));
 281                 }
 282         }
 283 }
 284
 285 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 286                                                   enum pipe pipe, bool enable)
 287 {
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289
 290         assert_spin_locked(&dev_priv->irq_lock);
 291
 292         if (enable)
 293                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 294         else
 295                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 296         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 297         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 298 }
 299
 300 /**
 301  * ibx_display_interrupt_update - update SDEIMR
 302  * @dev_priv: driver private
 303  * @interrupt_mask: mask of interrupt bits to update
 304  * @enabled_irq_mask: mask of interrupt bits to enable
 305  */
 306 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 307                                          uint32_t interrupt_mask,
 308                                          uint32_t enabled_irq_mask)
 309 {
 310         uint32_t sdeimr = I915_READ(SDEIMR);
 311         sdeimr &= ~interrupt_mask;
 312         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 313
 314         assert_spin_locked(&dev_priv->irq_lock);
 315
 316         if (dev_priv->pc8.irqs_disabled &&
 317             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 318                 WARN(1, "IRQs disabled\n");
 319                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 320                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 321                                                  interrupt_mask);
 322                 return;
 323         }
 324
 325         I915_WRITE(SDEIMR, sdeimr);
 326         POSTING_READ(SDEIMR);
 327 }
 328 #define ibx_enable_display_interrupt(dev_priv, bits) \
 329         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 330 #define ibx_disable_display_interrupt(dev_priv, bits) \
 331         ibx_display_interrupt_update((dev_priv), (bits), 0)
 332
 333 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 334                                             enum transcoder pch_transcoder,
 335                                             bool enable)
 336 {
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 339                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 340
 341         if (enable)
 342                 ibx_enable_display_interrupt(dev_priv, bit);
 343         else
 344                 ibx_disable_display_interrupt(dev_priv, bit);
 345 }
 346
 347 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 348                                             enum transcoder pch_transcoder,
 349                                             bool enable)
 350 {
 351         struct drm_i915_private *dev_priv = dev->dev_private;
 352
 353         if (enable) {
 354                 I915_WRITE(SERR_INT,
 355                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 356
 357                 if (!cpt_can_enable_serr_int(dev))
 358                         return;
 359
 360                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 361         } else {
 362                 uint32_t tmp = I915_READ(SERR_INT);
 363                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 364
 365                 /* Change the state _after_ we've read out the current one. */
 366                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 367
 368                 if (!was_enabled &&
 369                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 370                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 371                                       transcoder_name(pch_transcoder));
 372                 }
 373         }
 374 }
 375
 376 /**
 377  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 378  * @dev: drm device
 379  * @pipe: pipe
 380  * @enable: true if we want to report FIFO underrun errors, false otherwise
 381  *
 382  * This function makes us disable or enable CPU fifo underruns for a specific
 383  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 384  * reporting for one pipe may also disable all the other CPU error interruts for
 385  * the other pipes, due to the fact that there's just one interrupt mask/enable
 386  * bit for all the pipes.
 387  *
 388  * Returns the previous state of underrun reporting.
 389  */
 390 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 391                                            enum pipe pipe, bool enable)
 392 {
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 396         unsigned long flags;
 397         bool ret;
 398
 399         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 400
 401         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 402
 403         if (enable == ret)
 404                 goto done;
 405
 406         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 407
 408         if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
 409                 i9xx_clear_fifo_underrun(dev, pipe);
 410         else if (IS_GEN5(dev) || IS_GEN6(dev))
 411                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 412         else if (IS_GEN7(dev))
 413                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 414         else if (IS_GEN8(dev))
 415                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 416
 417 done:
 418         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 419         return ret;
 420 }
 421
 422 /**
 423  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 424  * @dev: drm device
 425  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 426  * @enable: true if we want to report FIFO underrun errors, false otherwise
 427  *
 428  * This function makes us disable or enable PCH fifo underruns for a specific
 429  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 430  * underrun reporting for one transcoder may also disable all the other PCH
 431  * error interruts for the other transcoders, due to the fact that there's just
 432  * one interrupt mask/enable bit for all the transcoders.
 433  *
 434  * Returns the previous state of underrun reporting.
 435  */
 436 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 437                                            enum transcoder pch_transcoder,
 438                                            bool enable)
 439 {
 440         struct drm_i915_private *dev_priv = dev->dev_private;
 441         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 443         unsigned long flags;
 444         bool ret;
 445
 446         /*
 447          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 448          * has only one pch transcoder A that all pipes can use. To avoid racy
 449          * pch transcoder -> pipe lookups from interrupt code simply store the
 450          * underrun statistics in crtc A. Since we never expose this anywhere
 451          * nor use it outside of the fifo underrun code here using the "wrong"
 452          * crtc on LPT won't cause issues.
 453          */
 454
 455         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 456
 457         ret = !intel_crtc->pch_fifo_underrun_disabled;
 458
 459         if (enable == ret)
 460                 goto done;
 461
 462         intel_crtc->pch_fifo_underrun_disabled = !enable;
 463
 464         if (HAS_PCH_IBX(dev))
 465                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 466         else
 467                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 468
 469 done:
 470         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 471         return ret;
 472 }
 473
 474
 475 void
 476 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 477 {
 478         u32 reg = PIPESTAT(pipe);
 479         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 480
 481         assert_spin_locked(&dev_priv->irq_lock);
 482
 483         if ((pipestat & mask) == mask)
 484                 return;
 485
 486         /* Enable the interrupt, clear any pending status */
 487         pipestat |= mask | (mask >> 16);
 488         I915_WRITE(reg, pipestat);
 489         POSTING_READ(reg);
 490 }
 491
 492 void
 493 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 494 {
 495         u32 reg = PIPESTAT(pipe);
 496         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 497
 498         assert_spin_locked(&dev_priv->irq_lock);
 499
 500         if ((pipestat & mask) == 0)
 501                 return;
 502
 503         pipestat &= ~mask;
 504         I915_WRITE(reg, pipestat);
 505         POSTING_READ(reg);
 506 }
 507
 508 /**
 509  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 510  */
 511 static void i915_enable_asle_pipestat(struct drm_device *dev)
 512 {
 513         drm_i915_private_t *dev_priv = dev->dev_private;
 514         unsigned long irqflags;
 515
 516         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 517                 return;
 518
 519         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 520
 521         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
 522         if (INTEL_INFO(dev)->gen >= 4)
 523                 i915_enable_pipestat(dev_priv, PIPE_A,
 524                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 525
 526         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 527 }
 528
 529 /**
 530  * i915_pipe_enabled - check if a pipe is enabled
 531  * @dev: DRM device
 532  * @pipe: pipe to check
 533  *
 534  * Reading certain registers when the pipe is disabled can hang the chip.
 535  * Use this routine to make sure the PLL is running and the pipe is active
 536  * before reading such registers if unsure.
 537  */
 538 static int
 539 i915_pipe_enabled(struct drm_device *dev, int pipe)
 540 {
 541         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 542
 543         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 544                 /* Locking is horribly broken here, but whatever. */
 545                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 546                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 547
 548                 return intel_crtc->active;
 549         } else {
 550                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 551         }
 552 }
 553
 554 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 555 {
 556         /* Gen2 doesn't have a hardware frame counter */
 557         return 0;
 558 }
 559
 560 /* Called from drm generic code, passed a 'crtc', which
 561  * we use as a pipe index
 562  */
 563 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 564 {
 565         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 566         unsigned long high_frame;
 567         unsigned long low_frame;
 568         u32 high1, high2, low, pixel, vbl_start;
 569
 570         if (!i915_pipe_enabled(dev, pipe)) {
 571                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 572                                 "pipe %c\n", pipe_name(pipe));
 573                 return 0;
 574         }
 575
 576         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 577                 struct intel_crtc *intel_crtc =
 578                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 579                 const struct drm_display_mode *mode =
 580                         &intel_crtc->config.adjusted_mode;
 581
 582                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 583         } else {
 584                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 585                 u32 htotal;
 586
 587                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 588                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 589
 590                 vbl_start *= htotal;
 591         }
 592
 593         high_frame = PIPEFRAME(pipe);
 594         low_frame = PIPEFRAMEPIXEL(pipe);
 595
 596         /*
 597          * High & low register fields aren't synchronized, so make sure
 598          * we get a low value that's stable across two reads of the high
 599          * register.
 600          */
 601         do {
 602                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 603                 low   = I915_READ(low_frame);
 604                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 605         } while (high1 != high2);
 606
 607         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 608         pixel = low & PIPE_PIXEL_MASK;
 609         low >>= PIPE_FRAME_LOW_SHIFT;
 610
 611         /*
 612          * The frame counter increments at beginning of active.
 613          * Cook up a vblank counter by also checking the pixel
 614          * counter against vblank start.
 615          */
 616         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 617 }
 618
 619 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 620 {
 621         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 622         int reg = PIPE_FRMCOUNT_GM45(pipe);
 623
 624         if (!i915_pipe_enabled(dev, pipe)) {
 625                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 626                                  "pipe %c\n", pipe_name(pipe));
 627                 return 0;
 628         }
 629
 630         return I915_READ(reg);
 631 }
 632
 633 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 634 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 635 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
 636
 637 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         uint32_t status;
 641
 642         if (INTEL_INFO(dev)->gen < 7) {
 643                 status = pipe == PIPE_A ?
 644                         DE_PIPEA_VBLANK :
 645                         DE_PIPEB_VBLANK;
 646         } else {
 647                 switch (pipe) {
 648                 default:
 649                 case PIPE_A:
 650                         status = DE_PIPEA_VBLANK_IVB;
 651                         break;
 652                 case PIPE_B:
 653                         status = DE_PIPEB_VBLANK_IVB;
 654                         break;
 655                 case PIPE_C:
 656                         status = DE_PIPEC_VBLANK_IVB;
 657                         break;
 658                 }
 659         }
 660
 661         return __raw_i915_read32(dev_priv, DEISR) & status;
 662 }
 663
 664 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 665                                     unsigned int flags, int *vpos, int *hpos,
 666                                     ktime_t *stime, ktime_t *etime)
 667 {
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 671         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 672         int position;
 673         int vbl_start, vbl_end, htotal, vtotal;
 674         bool in_vbl = true;
 675         int ret = 0;
 676         unsigned long irqflags;
 677
 678         if (!intel_crtc->active) {
 679                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 680                                  "pipe %c\n", pipe_name(pipe));
 681                 return 0;
 682         }
 683
 684         htotal = mode->crtc_htotal;
 685         vtotal = mode->crtc_vtotal;
 686         vbl_start = mode->crtc_vblank_start;
 687         vbl_end = mode->crtc_vblank_end;
 688
 689         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 690                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 691                 vbl_end /= 2;
 692                 vtotal /= 2;
 693         }
 694
 695         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 696
 697         /*
 698          * Lock uncore.lock, as we will do multiple timing critical raw
 699          * register reads, potentially with preemption disabled, so the
 700          * following code must not block on uncore.lock.
 701          */
 702         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 703
 704         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 705
 706         /* Get optional system timestamp before query. */
 707         if (stime)
 708                 *stime = ktime_get();
 709
 710         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 711                 /* No obvious pixelcount register. Only query vertical
 712                  * scanout position from Display scan line register.
 713                  */
 714                 if (IS_GEN2(dev))
 715                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 716                 else
 717                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 718
 719                 if (HAS_PCH_SPLIT(dev)) {
 720                         /*
 721                          * The scanline counter increments at the leading edge
 722                          * of hsync, ie. it completely misses the active portion
 723                          * of the line. Fix up the counter at both edges of vblank
 724                          * to get a more accurate picture whether we're in vblank
 725                          * or not.
 726                          */
 727                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 728                         if ((in_vbl && position == vbl_start - 1) ||
 729                             (!in_vbl && position == vbl_end - 1))
 730                                 position = (position + 1) % vtotal;
 731                 } else {
 732                         /*
 733                          * ISR vblank status bits don't work the way we'd want
 734                          * them to work on non-PCH platforms (for
 735                          * ilk_pipe_in_vblank_locked()), and there doesn't
 736                          * appear any other way to determine if we're currently
 737                          * in vblank.
 738                          *
 739                          * Instead let's assume that we're already in vblank if
 740                          * we got called from the vblank interrupt and the
 741                          * scanline counter value indicates that we're on the
 742                          * line just prior to vblank start. This should result
 743                          * in the correct answer, unless the vblank interrupt
 744                          * delivery really got delayed for almost exactly one
 745                          * full frame/field.
 746                          */
 747                         if (flags & DRM_CALLED_FROM_VBLIRQ &&
 748                             position == vbl_start - 1) {
 749                                 position = (position + 1) % vtotal;
 750
 751                                 /* Signal this correction as "applied". */
 752                                 ret |= 0x8;
 753                         }
 754                 }
 755         } else {
 756                 /* Have access to pixelcount since start of frame.
 757                  * We can split this into vertical and horizontal
 758                  * scanout position.
 759                  */
 760                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 761
 762                 /* convert to pixel counts */
 763                 vbl_start *= htotal;
 764                 vbl_end *= htotal;
 765                 vtotal *= htotal;
 766         }
 767
 768         /* Get optional system timestamp after query. */
 769         if (etime)
 770                 *etime = ktime_get();
 771
 772         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 773
 774         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 775
 776         in_vbl = position >= vbl_start && position < vbl_end;
 777
 778         /*
 779          * While in vblank, position will be negative
 780          * counting up towards 0 at vbl_end. And outside
 781          * vblank, position will be positive counting
 782          * up since vbl_end.
 783          */
 784         if (position >= vbl_start)
 785                 position -= vbl_end;
 786         else
 787                 position += vtotal - vbl_end;
 788
 789         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 790                 *vpos = position;
 791                 *hpos = 0;
 792         } else {
 793                 *vpos = position / htotal;
 794                 *hpos = position - (*vpos * htotal);
 795         }
 796
 797         /* In vblank? */
 798         if (in_vbl)
 799                 ret |= DRM_SCANOUTPOS_INVBL;
 800
 801         return ret;
 802 }
 803
 804 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 805                               int *max_error,
 806                               struct timeval *vblank_time,
 807                               unsigned flags)
 808 {
 809         struct drm_crtc *crtc;
 810
 811         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 812                 DRM_ERROR("Invalid crtc %d\n", pipe);
 813                 return -EINVAL;
 814         }
 815
 816         /* Get drm_crtc to timestamp: */
 817         crtc = intel_get_crtc_for_pipe(dev, pipe);
 818         if (crtc == NULL) {
 819                 DRM_ERROR("Invalid crtc %d\n", pipe);
 820                 return -EINVAL;
 821         }
 822
 823         if (!crtc->enabled) {
 824                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 825                 return -EBUSY;
 826         }
 827
 828         /* Helper routine in DRM core does all the work: */
 829         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 830                                                      vblank_time, flags,
 831                                                      crtc,
 832                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 833 }
 834
 835 static bool intel_hpd_irq_event(struct drm_device *dev,
 836                                 struct drm_connector *connector)
 837 {
 838         enum drm_connector_status old_status;
 839
 840         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 841         old_status = connector->status;
 842
 843         connector->status = connector->funcs->detect(connector, false);
 844         if (old_status == connector->status)
 845                 return false;
 846
 847         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 848                       connector->base.id,
 849                       drm_get_connector_name(connector),
 850                       drm_get_connector_status_name(old_status),
 851                       drm_get_connector_status_name(connector->status));
 852
 853         return true;
 854 }
 855
 856 /*
 857  * Handle hotplug events outside the interrupt handler proper.
 858  */
 859 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 860
 861 static void i915_hotplug_work_func(struct work_struct *work)
 862 {
 863         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 864                                                     hotplug_work);
 865         struct drm_device *dev = dev_priv->dev;
 866         struct drm_mode_config *mode_config = &dev->mode_config;
 867         struct intel_connector *intel_connector;
 868         struct intel_encoder *intel_encoder;
 869         struct drm_connector *connector;
 870         unsigned long irqflags;
 871         bool hpd_disabled = false;
 872         bool changed = false;
 873         u32 hpd_event_bits;
 874
 875         /* HPD irq before everything is fully set up. */
 876         if (!dev_priv->enable_hotplug_processing)
 877                 return;
 878
 879         mutex_lock(&mode_config->mutex);
 880         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 881
 882         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 883
 884         hpd_event_bits = dev_priv->hpd_event_bits;
 885         dev_priv->hpd_event_bits = 0;
 886         list_for_each_entry(connector, &mode_config->connector_list, head) {
 887                 intel_connector = to_intel_connector(connector);
 888                 intel_encoder = intel_connector->encoder;
 889                 if (intel_encoder->hpd_pin > HPD_NONE &&
 890                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 891                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 892                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 893                                  "switching from hotplug detection to polling\n",
 894                                 drm_get_connector_name(connector));
 895                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 896                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 897                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 898                         hpd_disabled = true;
 899                 }
 900                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 901                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 902                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 903                 }
 904         }
 905          /* if there were no outputs to poll, poll was disabled,
 906           * therefore make sure it's enabled when disabling HPD on
 907           * some connectors */
 908         if (hpd_disabled) {
 909                 drm_kms_helper_poll_enable(dev);
 910                 mod_timer(&dev_priv->hotplug_reenable_timer,
 911                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 912         }
 913
 914         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 915
 916         list_for_each_entry(connector, &mode_config->connector_list, head) {
 917                 intel_connector = to_intel_connector(connector);
 918                 intel_encoder = intel_connector->encoder;
 919                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 920                         if (intel_encoder->hot_plug)
 921                                 intel_encoder->hot_plug(intel_encoder);
 922                         if (intel_hpd_irq_event(dev, connector))
 923                                 changed = true;
 924                 }
 925         }
 926         mutex_unlock(&mode_config->mutex);
 927
 928         if (changed)
 929                 drm_kms_helper_hotplug_event(dev);
 930 }
 931
 932 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
 933 {
 934         del_timer_sync(&dev_priv->hotplug_reenable_timer);
 935 }
 936
 937 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 938 {
 939         drm_i915_private_t *dev_priv = dev->dev_private;
 940         u32 busy_up, busy_down, max_avg, min_avg;
 941         u8 new_delay;
 942
 943         spin_lock(&mchdev_lock);
 944
 945         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 946
 947         new_delay = dev_priv->ips.cur_delay;
 948
 949         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 950         busy_up = I915_READ(RCPREVBSYTUPAVG);
 951         busy_down = I915_READ(RCPREVBSYTDNAVG);
 952         max_avg = I915_READ(RCBMAXAVG);
 953         min_avg = I915_READ(RCBMINAVG);
 954
 955         /* Handle RCS change request from hw */
 956         if (busy_up > max_avg) {
 957                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 958                         new_delay = dev_priv->ips.cur_delay - 1;
 959                 if (new_delay < dev_priv->ips.max_delay)
 960                         new_delay = dev_priv->ips.max_delay;
 961         } else if (busy_down < min_avg) {
 962                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 963                         new_delay = dev_priv->ips.cur_delay + 1;
 964                 if (new_delay > dev_priv->ips.min_delay)
 965                         new_delay = dev_priv->ips.min_delay;
 966         }
 967
 968         if (ironlake_set_drps(dev, new_delay))
 969                 dev_priv->ips.cur_delay = new_delay;
 970
 971         spin_unlock(&mchdev_lock);
 972
 973         return;
 974 }
 975
 976 static void notify_ring(struct drm_device *dev,
 977                         struct intel_ring_buffer *ring)
 978 {
 979         if (ring->obj == NULL)
 980                 return;
 981
 982         trace_i915_gem_request_complete(ring);
 983
 984         wake_up_all(&ring->irq_queue);
 985         i915_queue_hangcheck(dev);
 986 }
 987
 988 void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
 989                              u32 pm_iir, int new_delay)
 990 {
 991         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 992                 if (new_delay >= dev_priv->rps.max_delay) {
 993                         /* Mask UP THRESHOLD Interrupts */
 994                         I915_WRITE(GEN6_PMINTRMSK,
 995                                    I915_READ(GEN6_PMINTRMSK) |
 996                                    GEN6_PM_RP_UP_THRESHOLD);
 997                         dev_priv->rps.rp_up_masked = true;
 998                 }
 999                 if (dev_priv->rps.rp_down_masked) {
1000                         /* UnMask DOWN THRESHOLD Interrupts */
1001                         I915_WRITE(GEN6_PMINTRMSK,
1002                                    I915_READ(GEN6_PMINTRMSK) &
1003                                    ~GEN6_PM_RP_DOWN_THRESHOLD);
1004                         dev_priv->rps.rp_down_masked = false;
1005                 }
1006         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1007                 if (new_delay <= dev_priv->rps.min_delay) {
1008                         /* Mask DOWN THRESHOLD Interrupts */
1009                         I915_WRITE(GEN6_PMINTRMSK,
1010                                    I915_READ(GEN6_PMINTRMSK) |
1011                                    GEN6_PM_RP_DOWN_THRESHOLD);
1012                         dev_priv->rps.rp_down_masked = true;
1013                 }
1014
1015                 if (dev_priv->rps.rp_up_masked) {
1016                         /* UnMask UP THRESHOLD Interrupts */
1017                         I915_WRITE(GEN6_PMINTRMSK,
1018                                    I915_READ(GEN6_PMINTRMSK) &
1019                                    ~GEN6_PM_RP_UP_THRESHOLD);
1020                         dev_priv->rps.rp_up_masked = false;
1021                 }
1022         }
1023 }
1024
1025 static void gen6_pm_rps_work(struct work_struct *work)
1026 {
1027         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1028                                                     rps.work);
1029         u32 pm_iir;
1030         int new_delay, adj;
1031
1032         spin_lock_irq(&dev_priv->irq_lock);
1033         pm_iir = dev_priv->rps.pm_iir;
1034         dev_priv->rps.pm_iir = 0;
1035         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1036         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
1037         spin_unlock_irq(&dev_priv->irq_lock);
1038
1039         /* Make sure we didn't queue anything we're not going to process. */
1040         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1041
1042         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1043                 return;
1044
1045         mutex_lock(&dev_priv->rps.hw_lock);
1046
1047         adj = dev_priv->rps.last_adj;
1048         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1049                 if (adj > 0)
1050                         adj *= 2;
1051                 else
1052                         adj = 1;
1053                 new_delay = dev_priv->rps.cur_delay + adj;
1054
1055                 /*
1056                  * For better performance, jump directly
1057                  * to RPe if we're below it.
1058                  */
1059                 if (new_delay < dev_priv->rps.rpe_delay)
1060                         new_delay = dev_priv->rps.rpe_delay;
1061         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1062                 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1063                         new_delay = dev_priv->rps.rpe_delay;
1064                 else
1065                         new_delay = dev_priv->rps.min_delay;
1066                 adj = 0;
1067         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1068                 if (adj < 0)
1069                         adj *= 2;
1070                 else
1071                         adj = -1;
1072                 new_delay = dev_priv->rps.cur_delay + adj;
1073         } else { /* unknown event */
1074                 new_delay = dev_priv->rps.cur_delay;
1075         }
1076
1077         /* sysfs frequency interfaces may have snuck in while servicing the
1078          * interrupt
1079          */
1080         new_delay = clamp_t(int, new_delay,
1081                             dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1082
1083         gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
1084         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1085
1086         if (IS_VALLEYVIEW(dev_priv->dev))
1087                 valleyview_set_rps(dev_priv->dev, new_delay);
1088         else
1089                 gen6_set_rps(dev_priv->dev, new_delay);
1090
1091         mutex_unlock(&dev_priv->rps.hw_lock);
1092 }
1093
1094
1095 /**
1096  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1097  * occurred.
1098  * @work: workqueue struct
1099  *
1100  * Doesn't actually do anything except notify userspace. As a consequence of
1101  * this event, userspace should try to remap the bad rows since statistically
1102  * it is likely the same row is more likely to go bad again.
1103  */
1104 static void ivybridge_parity_work(struct work_struct *work)
1105 {
1106         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1107                                                     l3_parity.error_work);
1108         u32 error_status, row, bank, subbank;
1109         char *parity_event[6];
1110         uint32_t misccpctl;
1111         unsigned long flags;
1112         uint8_t slice = 0;
1113
1114         /* We must turn off DOP level clock gating to access the L3 registers.
1115          * In order to prevent a get/put style interface, acquire struct mutex
1116          * any time we access those registers.
1117          */
1118         mutex_lock(&dev_priv->dev->struct_mutex);
1119
1120         /* If we've screwed up tracking, just let the interrupt fire again */
1121         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1122                 goto out;
1123
1124         misccpctl = I915_READ(GEN7_MISCCPCTL);
1125         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1126         POSTING_READ(GEN7_MISCCPCTL);
1127
1128         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1129                 u32 reg;
1130
1131                 slice--;
1132                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1133                         break;
1134
1135                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1136
1137                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1138
1139                 error_status = I915_READ(reg);
1140                 row = GEN7_PARITY_ERROR_ROW(error_status);
1141                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1142                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1143
1144                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1145                 POSTING_READ(reg);
1146
1147                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1148                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1149                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1150                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1151                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1152                 parity_event[5] = NULL;
1153
1154                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1155                                    KOBJ_CHANGE, parity_event);
1156
1157                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1158                           slice, row, bank, subbank);
1159
1160                 kfree(parity_event[4]);
1161                 kfree(parity_event[3]);
1162                 kfree(parity_event[2]);
1163                 kfree(parity_event[1]);
1164         }
1165
1166         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1167
1168 out:
1169         WARN_ON(dev_priv->l3_parity.which_slice);
1170         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1171         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1172         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1173
1174         mutex_unlock(&dev_priv->dev->struct_mutex);
1175 }
1176
1177 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1178 {
1179         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1180
1181         if (!HAS_L3_DPF(dev))
1182                 return;
1183
1184         spin_lock(&dev_priv->irq_lock);
1185         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1186         spin_unlock(&dev_priv->irq_lock);
1187
1188         iir &= GT_PARITY_ERROR(dev);
1189         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1190                 dev_priv->l3_parity.which_slice |= 1 << 1;
1191
1192         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1193                 dev_priv->l3_parity.which_slice |= 1 << 0;
1194
1195         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1196 }
1197
1198 static void ilk_gt_irq_handler(struct drm_device *dev,
1199                                struct drm_i915_private *dev_priv,
1200                                u32 gt_iir)
1201 {
1202         if (gt_iir &
1203             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1204                 notify_ring(dev, &dev_priv->ring[RCS]);
1205         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1206                 notify_ring(dev, &dev_priv->ring[VCS]);
1207 }
1208
1209 static void snb_gt_irq_handler(struct drm_device *dev,
1210                                struct drm_i915_private *dev_priv,
1211                                u32 gt_iir)
1212 {
1213
1214         if (gt_iir &
1215             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1216                 notify_ring(dev, &dev_priv->ring[RCS]);
1217         if (gt_iir & GT_BSD_USER_INTERRUPT)
1218                 notify_ring(dev, &dev_priv->ring[VCS]);
1219         if (gt_iir & GT_BLT_USER_INTERRUPT)
1220                 notify_ring(dev, &dev_priv->ring[BCS]);
1221
1222         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1223                       GT_BSD_CS_ERROR_INTERRUPT |
1224                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1225                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1226                 i915_handle_error(dev, false);
1227         }
1228
1229         if (gt_iir & GT_PARITY_ERROR(dev))
1230                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1231 }
1232
1233 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1234                                        struct drm_i915_private *dev_priv,
1235                                        u32 master_ctl)
1236 {
1237         u32 rcs, bcs, vcs;
1238         uint32_t tmp = 0;
1239         irqreturn_t ret = IRQ_NONE;
1240
1241         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1242                 tmp = I915_READ(GEN8_GT_IIR(0));
1243                 if (tmp) {
1244                         ret = IRQ_HANDLED;
1245                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1246                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1247                         if (rcs & GT_RENDER_USER_INTERRUPT)
1248                                 notify_ring(dev, &dev_priv->ring[RCS]);
1249                         if (bcs & GT_RENDER_USER_INTERRUPT)
1250                                 notify_ring(dev, &dev_priv->ring[BCS]);
1251                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1252                 } else
1253                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1254         }
1255
1256         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1257                 tmp = I915_READ(GEN8_GT_IIR(1));
1258                 if (tmp) {
1259                         ret = IRQ_HANDLED;
1260                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1261                         if (vcs & GT_RENDER_USER_INTERRUPT)
1262                                 notify_ring(dev, &dev_priv->ring[VCS]);
1263                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1264                 } else
1265                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1266         }
1267
1268         if (master_ctl & GEN8_GT_VECS_IRQ) {
1269                 tmp = I915_READ(GEN8_GT_IIR(3));
1270                 if (tmp) {
1271                         ret = IRQ_HANDLED;
1272                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1273                         if (vcs & GT_RENDER_USER_INTERRUPT)
1274                                 notify_ring(dev, &dev_priv->ring[VECS]);
1275                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1276                 } else
1277                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1278         }
1279
1280         return ret;
1281 }
1282
1283 #define HPD_STORM_DETECT_PERIOD 1000
1284 #define HPD_STORM_THRESHOLD 5
1285
1286 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1287                                          u32 hotplug_trigger,
1288                                          const u32 *hpd)
1289 {
1290         drm_i915_private_t *dev_priv = dev->dev_private;
1291         int i;
1292         bool storm_detected = false;
1293
1294         if (!hotplug_trigger)
1295                 return;
1296
1297         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1298                           hotplug_trigger);
1299
1300         spin_lock(&dev_priv->irq_lock);
1301         for (i = 1; i < HPD_NUM_PINS; i++) {
1302
1303                 WARN_ONCE(hpd[i] & hotplug_trigger &&
1304                           dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1305                           "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1306                           hotplug_trigger, i, hpd[i]);
1307
1308                 if (!(hpd[i] & hotplug_trigger) ||
1309                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1310                         continue;
1311
1312                 dev_priv->hpd_event_bits |= (1 << i);
1313                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1314                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1315                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1316                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1317                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1318                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1319                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1320                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1321                         dev_priv->hpd_event_bits &= ~(1 << i);
1322                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1323                         storm_detected = true;
1324                 } else {
1325                         dev_priv->hpd_stats[i].hpd_cnt++;
1326                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1327                                       dev_priv->hpd_stats[i].hpd_cnt);
1328                 }
1329         }
1330
1331         if (storm_detected)
1332                 dev_priv->display.hpd_irq_setup(dev);
1333         spin_unlock(&dev_priv->irq_lock);
1334
1335         /*
1336          * Our hotplug handler can grab modeset locks (by calling down into the
1337          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1338          * queue for otherwise the flush_work in the pageflip code will
1339          * deadlock.
1340          */
1341         schedule_work(&dev_priv->hotplug_work);
1342 }
1343
1344 static void gmbus_irq_handler(struct drm_device *dev)
1345 {
1346         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1347
1348         wake_up_all(&dev_priv->gmbus_wait_queue);
1349 }
1350
1351 static void dp_aux_irq_handler(struct drm_device *dev)
1352 {
1353         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1354
1355         wake_up_all(&dev_priv->gmbus_wait_queue);
1356 }
1357
1358 #if defined(CONFIG_DEBUG_FS)
1359 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1360                                          uint32_t crc0, uint32_t crc1,
1361                                          uint32_t crc2, uint32_t crc3,
1362                                          uint32_t crc4)
1363 {
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1366         struct intel_pipe_crc_entry *entry;
1367         int head, tail;
1368
1369         spin_lock(&pipe_crc->lock);
1370
1371         if (!pipe_crc->entries) {
1372                 spin_unlock(&pipe_crc->lock);
1373                 DRM_ERROR("spurious interrupt\n");
1374                 return;
1375         }
1376
1377         head = pipe_crc->head;
1378         tail = pipe_crc->tail;
1379
1380         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1381                 spin_unlock(&pipe_crc->lock);
1382                 DRM_ERROR("CRC buffer overflowing\n");
1383                 return;
1384         }
1385
1386         entry = &pipe_crc->entries[head];
1387
1388         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1389         entry->crc[0] = crc0;
1390         entry->crc[1] = crc1;
1391         entry->crc[2] = crc2;
1392         entry->crc[3] = crc3;
1393         entry->crc[4] = crc4;
1394
1395         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1396         pipe_crc->head = head;
1397
1398         spin_unlock(&pipe_crc->lock);
1399
1400         wake_up_interruptible(&pipe_crc->wq);
1401 }
1402 #else
1403 static inline void
1404 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1405                              uint32_t crc0, uint32_t crc1,
1406                              uint32_t crc2, uint32_t crc3,
1407                              uint32_t crc4) {}
1408 #endif
1409
1410
1411 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1412 {
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414
1415         display_pipe_crc_irq_handler(dev, pipe,
1416                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1417                                      0, 0, 0, 0);
1418 }
1419
1420 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1421 {
1422         struct drm_i915_private *dev_priv = dev->dev_private;
1423
1424         display_pipe_crc_irq_handler(dev, pipe,
1425                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1426                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1427                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1428                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1429                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1430 }
1431
1432 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1433 {
1434         struct drm_i915_private *dev_priv = dev->dev_private;
1435         uint32_t res1, res2;
1436
1437         if (INTEL_INFO(dev)->gen >= 3)
1438                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1439         else
1440                 res1 = 0;
1441
1442         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1443                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1444         else
1445                 res2 = 0;
1446
1447         display_pipe_crc_irq_handler(dev, pipe,
1448                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1449                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1450                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1451                                      res1, res2);
1452 }
1453
1454 /* The RPS events need forcewake, so we add them to a work queue and mask their
1455  * IMR bits until the work is done. Other interrupts can be processed without
1456  * the work queue. */
1457 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1458 {
1459         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1460                 spin_lock(&dev_priv->irq_lock);
1461                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1462                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1463                 spin_unlock(&dev_priv->irq_lock);
1464
1465                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1466         }
1467
1468         if (HAS_VEBOX(dev_priv->dev)) {
1469                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1470                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1471
1472                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1473                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1474                         i915_handle_error(dev_priv->dev, false);
1475                 }
1476         }
1477 }
1478
1479 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1480 {
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         u32 pipe_stats[I915_MAX_PIPES];
1483         int pipe;
1484
1485         spin_lock(&dev_priv->irq_lock);
1486         for_each_pipe(pipe) {
1487                 int reg = PIPESTAT(pipe);
1488                 pipe_stats[pipe] = I915_READ(reg);
1489
1490                 /*
1491                  * Clear the PIPE*STAT regs before the IIR
1492                  */
1493                 if (pipe_stats[pipe] & 0x8000ffff)
1494                         I915_WRITE(reg, pipe_stats[pipe]);
1495         }
1496         spin_unlock(&dev_priv->irq_lock);
1497
1498         for_each_pipe(pipe) {
1499                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1500                         drm_handle_vblank(dev, pipe);
1501
1502                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1503                         intel_prepare_page_flip(dev, pipe);
1504                         intel_finish_page_flip(dev, pipe);
1505                 }
1506
1507                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1508                         i9xx_pipe_crc_irq_handler(dev, pipe);
1509
1510                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1511                     intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1512                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1513         }
1514
1515         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1516                 gmbus_irq_handler(dev);
1517 }
1518
1519 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1520 {
1521         struct drm_device *dev = (struct drm_device *) arg;
1522         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1523         u32 iir, gt_iir, pm_iir;
1524         irqreturn_t ret = IRQ_NONE;
1525
1526         while (true) {
1527                 iir = I915_READ(VLV_IIR);
1528                 gt_iir = I915_READ(GTIIR);
1529                 pm_iir = I915_READ(GEN6_PMIIR);
1530
1531                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1532                         goto out;
1533
1534                 ret = IRQ_HANDLED;
1535
1536                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1537
1538                 valleyview_pipestat_irq_handler(dev, iir);
1539
1540                 /* Consume port.  Then clear IIR or we'll miss events */
1541                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1542                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1543                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1544
1545                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1546
1547                         if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1548                                 dp_aux_irq_handler(dev);
1549
1550                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1551                         I915_READ(PORT_HOTPLUG_STAT);
1552                 }
1553
1554
1555                 if (pm_iir)
1556                         gen6_rps_irq_handler(dev_priv, pm_iir);
1557
1558                 I915_WRITE(GTIIR, gt_iir);
1559                 I915_WRITE(GEN6_PMIIR, pm_iir);
1560                 I915_WRITE(VLV_IIR, iir);
1561         }
1562
1563 out:
1564         return ret;
1565 }
1566
1567 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1568 {
1569         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1570         int pipe;
1571         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1572
1573         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1574
1575         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1576                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1577                                SDE_AUDIO_POWER_SHIFT);
1578                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1579                                  port_name(port));
1580         }
1581
1582         if (pch_iir & SDE_AUX_MASK)
1583                 dp_aux_irq_handler(dev);
1584
1585         if (pch_iir & SDE_GMBUS)
1586                 gmbus_irq_handler(dev);
1587
1588         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1589                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1590
1591         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1592                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1593
1594         if (pch_iir & SDE_POISON)
1595                 DRM_ERROR("PCH poison interrupt\n");
1596
1597         if (pch_iir & SDE_FDI_MASK)
1598                 for_each_pipe(pipe)
1599                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1600                                          pipe_name(pipe),
1601                                          I915_READ(FDI_RX_IIR(pipe)));
1602
1603         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1604                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1605
1606         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1607                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1608
1609         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1610                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1611                                                           false))
1612                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1613
1614         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1615                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1616                                                           false))
1617                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1618 }
1619
1620 static void ivb_err_int_handler(struct drm_device *dev)
1621 {
1622         struct drm_i915_private *dev_priv = dev->dev_private;
1623         u32 err_int = I915_READ(GEN7_ERR_INT);
1624         enum pipe pipe;
1625
1626         if (err_int & ERR_INT_POISON)
1627                 DRM_ERROR("Poison interrupt\n");
1628
1629         for_each_pipe(pipe) {
1630                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1631                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1632                                                                   false))
1633                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1634                                           pipe_name(pipe));
1635                 }
1636
1637                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1638                         if (IS_IVYBRIDGE(dev))
1639                                 ivb_pipe_crc_irq_handler(dev, pipe);
1640                         else
1641                                 hsw_pipe_crc_irq_handler(dev, pipe);
1642                 }
1643         }
1644
1645         I915_WRITE(GEN7_ERR_INT, err_int);
1646 }
1647
1648 static void cpt_serr_int_handler(struct drm_device *dev)
1649 {
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651         u32 serr_int = I915_READ(SERR_INT);
1652
1653         if (serr_int & SERR_INT_POISON)
1654                 DRM_ERROR("PCH poison interrupt\n");
1655
1656         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1657                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1658                                                           false))
1659                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1660
1661         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1662                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1663                                                           false))
1664                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1665
1666         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1667                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1668                                                           false))
1669                         DRM_ERROR("PCH transcoder C FIFO underrun\n");
1670
1671         I915_WRITE(SERR_INT, serr_int);
1672 }
1673
1674 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1675 {
1676         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1677         int pipe;
1678         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1679
1680         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1681
1682         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1683                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1684                                SDE_AUDIO_POWER_SHIFT_CPT);
1685                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1686                                  port_name(port));
1687         }
1688
1689         if (pch_iir & SDE_AUX_MASK_CPT)
1690                 dp_aux_irq_handler(dev);
1691
1692         if (pch_iir & SDE_GMBUS_CPT)
1693                 gmbus_irq_handler(dev);
1694
1695         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1696                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1697
1698         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1699                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1700
1701         if (pch_iir & SDE_FDI_MASK_CPT)
1702                 for_each_pipe(pipe)
1703                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1704                                          pipe_name(pipe),
1705                                          I915_READ(FDI_RX_IIR(pipe)));
1706
1707         if (pch_iir & SDE_ERROR_CPT)
1708                 cpt_serr_int_handler(dev);
1709 }
1710
1711 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1712 {
1713         struct drm_i915_private *dev_priv = dev->dev_private;
1714         enum pipe pipe;
1715
1716         if (de_iir & DE_AUX_CHANNEL_A)
1717                 dp_aux_irq_handler(dev);
1718
1719         if (de_iir & DE_GSE)
1720                 intel_opregion_asle_intr(dev);
1721
1722         if (de_iir & DE_POISON)
1723                 DRM_ERROR("Poison interrupt\n");
1724
1725         for_each_pipe(pipe) {
1726                 if (de_iir & DE_PIPE_VBLANK(pipe))
1727                         drm_handle_vblank(dev, pipe);
1728
1729                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1730                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1731                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1732                                           pipe_name(pipe));
1733
1734                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1735                         i9xx_pipe_crc_irq_handler(dev, pipe);
1736
1737                 /* plane/pipes map 1:1 on ilk+ */
1738                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1739                         intel_prepare_page_flip(dev, pipe);
1740                         intel_finish_page_flip_plane(dev, pipe);
1741                 }
1742         }
1743
1744         /* check event from PCH */
1745         if (de_iir & DE_PCH_EVENT) {
1746                 u32 pch_iir = I915_READ(SDEIIR);
1747
1748                 if (HAS_PCH_CPT(dev))
1749                         cpt_irq_handler(dev, pch_iir);
1750                 else
1751                         ibx_irq_handler(dev, pch_iir);
1752
1753                 /* should clear PCH hotplug event before clear CPU irq */
1754                 I915_WRITE(SDEIIR, pch_iir);
1755         }
1756
1757         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1758                 ironlake_rps_change_irq_handler(dev);
1759 }
1760
1761 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1762 {
1763         struct drm_i915_private *dev_priv = dev->dev_private;
1764         enum pipe i;
1765
1766         if (de_iir & DE_ERR_INT_IVB)
1767                 ivb_err_int_handler(dev);
1768
1769         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1770                 dp_aux_irq_handler(dev);
1771
1772         if (de_iir & DE_GSE_IVB)
1773                 intel_opregion_asle_intr(dev);
1774
1775         for_each_pipe(i) {
1776                 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1777                         drm_handle_vblank(dev, i);
1778
1779                 /* plane/pipes map 1:1 on ilk+ */
1780                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1781                         intel_prepare_page_flip(dev, i);
1782                         intel_finish_page_flip_plane(dev, i);
1783                 }
1784         }
1785
1786         /* check event from PCH */
1787         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1788                 u32 pch_iir = I915_READ(SDEIIR);
1789
1790                 cpt_irq_handler(dev, pch_iir);
1791
1792                 /* clear PCH hotplug event before clear CPU irq */
1793                 I915_WRITE(SDEIIR, pch_iir);
1794         }
1795 }
1796
1797 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1798 {
1799         struct drm_device *dev = (struct drm_device *) arg;
1800         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1801         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1802         irqreturn_t ret = IRQ_NONE;
1803
1804         /* We get interrupts on unclaimed registers, so check for this before we
1805          * do any I915_{READ,WRITE}. */
1806         intel_uncore_check_errors(dev);
1807
1808         /* disable master interrupt before clearing iir  */
1809         de_ier = I915_READ(DEIER);
1810         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1811         POSTING_READ(DEIER);
1812
1813         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1814          * interrupts will will be stored on its back queue, and then we'll be
1815          * able to process them after we restore SDEIER (as soon as we restore
1816          * it, we'll get an interrupt if SDEIIR still has something to process
1817          * due to its back queue). */
1818         if (!HAS_PCH_NOP(dev)) {
1819                 sde_ier = I915_READ(SDEIER);
1820                 I915_WRITE(SDEIER, 0);
1821                 POSTING_READ(SDEIER);
1822         }
1823
1824         gt_iir = I915_READ(GTIIR);
1825         if (gt_iir) {
1826                 if (INTEL_INFO(dev)->gen >= 6)
1827                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1828                 else
1829                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1830                 I915_WRITE(GTIIR, gt_iir);
1831                 ret = IRQ_HANDLED;
1832         }
1833
1834         de_iir = I915_READ(DEIIR);
1835         if (de_iir) {
1836                 if (INTEL_INFO(dev)->gen >= 7)
1837                         ivb_display_irq_handler(dev, de_iir);
1838                 else
1839                         ilk_display_irq_handler(dev, de_iir);
1840                 I915_WRITE(DEIIR, de_iir);
1841                 ret = IRQ_HANDLED;
1842         }
1843
1844         if (INTEL_INFO(dev)->gen >= 6) {
1845                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1846                 if (pm_iir) {
1847                         gen6_rps_irq_handler(dev_priv, pm_iir);
1848                         I915_WRITE(GEN6_PMIIR, pm_iir);
1849                         ret = IRQ_HANDLED;
1850                 }
1851         }
1852
1853         I915_WRITE(DEIER, de_ier);
1854         POSTING_READ(DEIER);
1855         if (!HAS_PCH_NOP(dev)) {
1856                 I915_WRITE(SDEIER, sde_ier);
1857                 POSTING_READ(SDEIER);
1858         }
1859
1860         return ret;
1861 }
1862
1863 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1864 {
1865         struct drm_device *dev = arg;
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         u32 master_ctl;
1868         irqreturn_t ret = IRQ_NONE;
1869         uint32_t tmp = 0;
1870         enum pipe pipe;
1871
1872         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1873         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1874         if (!master_ctl)
1875                 return IRQ_NONE;
1876
1877         I915_WRITE(GEN8_MASTER_IRQ, 0);
1878         POSTING_READ(GEN8_MASTER_IRQ);
1879
1880         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1881
1882         if (master_ctl & GEN8_DE_MISC_IRQ) {
1883                 tmp = I915_READ(GEN8_DE_MISC_IIR);
1884                 if (tmp & GEN8_DE_MISC_GSE)
1885                         intel_opregion_asle_intr(dev);
1886                 else if (tmp)
1887                         DRM_ERROR("Unexpected DE Misc interrupt\n");
1888                 else
1889                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1890
1891                 if (tmp) {
1892                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1893                         ret = IRQ_HANDLED;
1894                 }
1895         }
1896
1897         if (master_ctl & GEN8_DE_PORT_IRQ) {
1898                 tmp = I915_READ(GEN8_DE_PORT_IIR);
1899                 if (tmp & GEN8_AUX_CHANNEL_A)
1900                         dp_aux_irq_handler(dev);
1901                 else if (tmp)
1902                         DRM_ERROR("Unexpected DE Port interrupt\n");
1903                 else
1904                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1905
1906                 if (tmp) {
1907                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1908                         ret = IRQ_HANDLED;
1909                 }
1910         }
1911
1912         for_each_pipe(pipe) {
1913                 uint32_t pipe_iir;
1914
1915                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1916                         continue;
1917
1918                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1919                 if (pipe_iir & GEN8_PIPE_VBLANK)
1920                         drm_handle_vblank(dev, pipe);
1921
1922                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1923                         intel_prepare_page_flip(dev, pipe);
1924                         intel_finish_page_flip_plane(dev, pipe);
1925                 }
1926
1927                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1928                         hsw_pipe_crc_irq_handler(dev, pipe);
1929
1930                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1931                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1932                                                                   false))
1933                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1934                                           pipe_name(pipe));
1935                 }
1936
1937                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1938                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1939                                   pipe_name(pipe),
1940                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1941                 }
1942
1943                 if (pipe_iir) {
1944                         ret = IRQ_HANDLED;
1945                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1946                 } else
1947                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1948         }
1949
1950         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1951                 /*
1952                  * FIXME(BDW): Assume for now that the new interrupt handling
1953                  * scheme also closed the SDE interrupt handling race we've seen
1954                  * on older pch-split platforms. But this needs testing.
1955                  */
1956                 u32 pch_iir = I915_READ(SDEIIR);
1957
1958                 cpt_irq_handler(dev, pch_iir);
1959
1960                 if (pch_iir) {
1961                         I915_WRITE(SDEIIR, pch_iir);
1962                         ret = IRQ_HANDLED;
1963                 }
1964         }
1965
1966         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1967         POSTING_READ(GEN8_MASTER_IRQ);
1968
1969         return ret;
1970 }
1971
1972 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1973                                bool reset_completed)
1974 {
1975         struct intel_ring_buffer *ring;
1976         int i;
1977
1978         /*
1979          * Notify all waiters for GPU completion events that reset state has
1980          * been changed, and that they need to restart their wait after
1981          * checking for potential errors (and bail out to drop locks if there is
1982          * a gpu reset pending so that i915_error_work_func can acquire them).
1983          */
1984
1985         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1986         for_each_ring(ring, dev_priv, i)
1987                 wake_up_all(&ring->irq_queue);
1988
1989         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1990         wake_up_all(&dev_priv->pending_flip_queue);
1991
1992         /*
1993          * Signal tasks blocked in i915_gem_wait_for_error that the pending
1994          * reset state is cleared.
1995          */
1996         if (reset_completed)
1997                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1998 }
1999
2000 /**
2001  * i915_error_work_func - do process context error handling work
2002  * @work: work struct
2003  *
2004  * Fire an error uevent so userspace can see that a hang or error
2005  * was detected.
2006  */
2007 static void i915_error_work_func(struct work_struct *work)
2008 {
2009         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2010                                                     work);
2011         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
2012                                                     gpu_error);
2013         struct drm_device *dev = dev_priv->dev;
2014         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2015         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2016         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2017         int ret;
2018
2019         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2020
2021         /*
2022          * Note that there's only one work item which does gpu resets, so we
2023          * need not worry about concurrent gpu resets potentially incrementing
2024          * error->reset_counter twice. We only need to take care of another
2025          * racing irq/hangcheck declaring the gpu dead for a second time. A
2026          * quick check for that is good enough: schedule_work ensures the
2027          * correct ordering between hang detection and this work item, and since
2028          * the reset in-progress bit is only ever set by code outside of this
2029          * work we don't need to worry about any other races.
2030          */
2031         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2032                 DRM_DEBUG_DRIVER("resetting chip\n");
2033                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2034                                    reset_event);
2035
2036                 /*
2037                  * All state reset _must_ be completed before we update the
2038                  * reset counter, for otherwise waiters might miss the reset
2039                  * pending state and not properly drop locks, resulting in
2040                  * deadlocks with the reset work.
2041                  */
2042                 ret = i915_reset(dev);
2043
2044                 intel_display_handle_reset(dev);
2045
2046                 if (ret == 0) {
2047                         /*
2048                          * After all the gem state is reset, increment the reset
2049                          * counter and wake up everyone waiting for the reset to
2050                          * complete.
2051                          *
2052                          * Since unlock operations are a one-sided barrier only,
2053                          * we need to insert a barrier here to order any seqno
2054                          * updates before
2055                          * the counter increment.
2056                          */
2057                         smp_mb__before_atomic_inc();
2058                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2059
2060                         kobject_uevent_env(&dev->primary->kdev->kobj,
2061                                            KOBJ_CHANGE, reset_done_event);
2062                 } else {
2063                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2064                 }
2065
2066                 /*
2067                  * Note: The wake_up also serves as a memory barrier so that
2068                  * waiters see the update value of the reset counter atomic_t.
2069                  */
2070                 i915_error_wake_up(dev_priv, true);
2071         }
2072 }
2073
2074 static void i915_report_and_clear_eir(struct drm_device *dev)
2075 {
2076         struct drm_i915_private *dev_priv = dev->dev_private;
2077         uint32_t instdone[I915_NUM_INSTDONE_REG];
2078         u32 eir = I915_READ(EIR);
2079         int pipe, i;
2080
2081         if (!eir)
2082                 return;
2083
2084         pr_err("render error detected, EIR: 0x%08x\n", eir);
2085
2086         i915_get_extra_instdone(dev, instdone);
2087
2088         if (IS_G4X(dev)) {
2089                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2090                         u32 ipeir = I915_READ(IPEIR_I965);
2091
2092                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2093                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2094                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2095                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2096                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2097                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2098                         I915_WRITE(IPEIR_I965, ipeir);
2099                         POSTING_READ(IPEIR_I965);
2100                 }
2101                 if (eir & GM45_ERROR_PAGE_TABLE) {
2102                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2103                         pr_err("page table error\n");
2104                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2105                         I915_WRITE(PGTBL_ER, pgtbl_err);
2106                         POSTING_READ(PGTBL_ER);
2107                 }
2108         }
2109
2110         if (!IS_GEN2(dev)) {
2111                 if (eir & I915_ERROR_PAGE_TABLE) {
2112                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2113                         pr_err("page table error\n");
2114                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2115                         I915_WRITE(PGTBL_ER, pgtbl_err);
2116                         POSTING_READ(PGTBL_ER);
2117                 }
2118         }
2119
2120         if (eir & I915_ERROR_MEMORY_REFRESH) {
2121                 pr_err("memory refresh error:\n");
2122                 for_each_pipe(pipe)
2123                         pr_err("pipe %c stat: 0x%08x\n",
2124                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2125                 /* pipestat has already been acked */
2126         }
2127         if (eir & I915_ERROR_INSTRUCTION) {
2128                 pr_err("instruction error\n");
2129                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2130                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2131                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2132                 if (INTEL_INFO(dev)->gen < 4) {
2133                         u32 ipeir = I915_READ(IPEIR);
2134
2135                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2136                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2137                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2138                         I915_WRITE(IPEIR, ipeir);
2139                         POSTING_READ(IPEIR);
2140                 } else {
2141                         u32 ipeir = I915_READ(IPEIR_I965);
2142
2143                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2144                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2145                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2146                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2147                         I915_WRITE(IPEIR_I965, ipeir);
2148                         POSTING_READ(IPEIR_I965);
2149                 }
2150         }
2151
2152         I915_WRITE(EIR, eir);
2153         POSTING_READ(EIR);
2154         eir = I915_READ(EIR);
2155         if (eir) {
2156                 /*
2157                  * some errors might have become stuck,
2158                  * mask them.
2159                  */
2160                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2161                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2162                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2163         }
2164 }
2165
2166 /**
2167  * i915_handle_error - handle an error interrupt
2168  * @dev: drm device
2169  *
2170  * Do some basic checking of regsiter state at error interrupt time and
2171  * dump it to the syslog.  Also call i915_capture_error_state() to make
2172  * sure we get a record and make it available in debugfs.  Fire a uevent
2173  * so userspace knows something bad happened (should trigger collection
2174  * of a ring dump etc.).
2175  */
2176 void i915_handle_error(struct drm_device *dev, bool wedged)
2177 {
2178         struct drm_i915_private *dev_priv = dev->dev_private;
2179
2180         i915_capture_error_state(dev);
2181         i915_report_and_clear_eir(dev);
2182
2183         if (wedged) {
2184                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2185                                 &dev_priv->gpu_error.reset_counter);
2186
2187                 /*
2188                  * Wakeup waiting processes so that the reset work function
2189                  * i915_error_work_func doesn't deadlock trying to grab various
2190                  * locks. By bumping the reset counter first, the woken
2191                  * processes will see a reset in progress and back off,
2192                  * releasing their locks and then wait for the reset completion.
2193                  * We must do this for _all_ gpu waiters that might hold locks
2194                  * that the reset work needs to acquire.
2195                  *
2196                  * Note: The wake_up serves as the required memory barrier to
2197                  * ensure that the waiters see the updated value of the reset
2198                  * counter atomic_t.
2199                  */
2200                 i915_error_wake_up(dev_priv, false);
2201         }
2202
2203         /*
2204          * Our reset work can grab modeset locks (since it needs to reset the
2205          * state of outstanding pagelips). Hence it must not be run on our own
2206          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2207          * code will deadlock.
2208          */
2209         schedule_work(&dev_priv->gpu_error.work);
2210 }
2211
2212 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2213 {
2214         drm_i915_private_t *dev_priv = dev->dev_private;
2215         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217         struct drm_i915_gem_object *obj;
2218         struct intel_unpin_work *work;
2219         unsigned long flags;
2220         bool stall_detected;
2221
2222         /* Ignore early vblank irqs */
2223         if (intel_crtc == NULL)
2224                 return;
2225
2226         spin_lock_irqsave(&dev->event_lock, flags);
2227         work = intel_crtc->unpin_work;
2228
2229         if (work == NULL ||
2230             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2231             !work->enable_stall_check) {
2232                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2233                 spin_unlock_irqrestore(&dev->event_lock, flags);
2234                 return;
2235         }
2236
2237         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2238         obj = work->pending_flip_obj;
2239         if (INTEL_INFO(dev)->gen >= 4) {
2240                 int dspsurf = DSPSURF(intel_crtc->plane);
2241                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2242                                         i915_gem_obj_ggtt_offset(obj);
2243         } else {
2244                 int dspaddr = DSPADDR(intel_crtc->plane);
2245                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2246                                                         crtc->y * crtc->fb->pitches[0] +
2247                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2248         }
2249
2250         spin_unlock_irqrestore(&dev->event_lock, flags);
2251
2252         if (stall_detected) {
2253                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2254                 intel_prepare_page_flip(dev, intel_crtc->plane);
2255         }
2256 }
2257
2258 /* Called from drm generic code, passed 'crtc' which
2259  * we use as a pipe index
2260  */
2261 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2262 {
2263         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2264         unsigned long irqflags;
2265
2266         if (!i915_pipe_enabled(dev, pipe))
2267                 return -EINVAL;
2268
2269         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2270         if (INTEL_INFO(dev)->gen >= 4)
2271                 i915_enable_pipestat(dev_priv, pipe,
2272                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
2273         else
2274                 i915_enable_pipestat(dev_priv, pipe,
2275                                      PIPE_VBLANK_INTERRUPT_ENABLE);
2276
2277         /* maintain vblank delivery even in deep C-states */
2278         if (dev_priv->info->gen == 3)
2279                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2280         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2281
2282         return 0;
2283 }
2284
2285 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2286 {
2287         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2288         unsigned long irqflags;
2289         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2290                                                      DE_PIPE_VBLANK(pipe);
2291
2292         if (!i915_pipe_enabled(dev, pipe))
2293                 return -EINVAL;
2294
2295         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2296         ironlake_enable_display_irq(dev_priv, bit);
2297         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2298
2299         return 0;
2300 }
2301
2302 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2303 {
2304         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2305         unsigned long irqflags;
2306
2307         if (!i915_pipe_enabled(dev, pipe))
2308                 return -EINVAL;
2309
2310         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2311         i915_enable_pipestat(dev_priv, pipe,
2312                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
2313         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2314
2315         return 0;
2316 }
2317
2318 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2319 {
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321         unsigned long irqflags;
2322
2323         if (!i915_pipe_enabled(dev, pipe))
2324                 return -EINVAL;
2325
2326         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2327         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2328         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2329         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2330         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2331         return 0;
2332 }
2333
2334 /* Called from drm generic code, passed 'crtc' which
2335  * we use as a pipe index
2336  */
2337 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2338 {
2339         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2340         unsigned long irqflags;
2341
2342         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2343         if (dev_priv->info->gen == 3)
2344                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2345
2346         i915_disable_pipestat(dev_priv, pipe,
2347                               PIPE_VBLANK_INTERRUPT_ENABLE |
2348                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2349         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2350 }
2351
2352 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2353 {
2354         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2355         unsigned long irqflags;
2356         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2357                                                      DE_PIPE_VBLANK(pipe);
2358
2359         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2360         ironlake_disable_display_irq(dev_priv, bit);
2361         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2362 }
2363
2364 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2365 {
2366         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2367         unsigned long irqflags;
2368
2369         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2370         i915_disable_pipestat(dev_priv, pipe,
2371                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2372         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2373 }
2374
2375 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2376 {
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378         unsigned long irqflags;
2379
2380         if (!i915_pipe_enabled(dev, pipe))
2381                 return;
2382
2383         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2384         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2385         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2386         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2387         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2388 }
2389
2390 static u32
2391 ring_last_seqno(struct intel_ring_buffer *ring)
2392 {
2393         return list_entry(ring->request_list.prev,
2394                           struct drm_i915_gem_request, list)->seqno;
2395 }
2396
2397 static bool
2398 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2399 {
2400         return (list_empty(&ring->request_list) ||
2401                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2402 }
2403
2404 static struct intel_ring_buffer *
2405 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2406 {
2407         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2408         u32 cmd, ipehr, acthd, acthd_min;
2409
2410         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2411         if ((ipehr & ~(0x3 << 16)) !=
2412             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2413                 return NULL;
2414
2415         /* ACTHD is likely pointing to the dword after the actual command,
2416          * so scan backwards until we find the MBOX.
2417          */
2418         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2419         acthd_min = max((int)acthd - 3 * 4, 0);
2420         do {
2421                 cmd = ioread32(ring->virtual_start + acthd);
2422                 if (cmd == ipehr)
2423                         break;
2424
2425                 acthd -= 4;
2426                 if (acthd < acthd_min)
2427                         return NULL;
2428         } while (1);
2429
2430         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2431         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2432 }
2433
2434 static int semaphore_passed(struct intel_ring_buffer *ring)
2435 {
2436         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2437         struct intel_ring_buffer *signaller;
2438         u32 seqno, ctl;
2439
2440         ring->hangcheck.deadlock = true;
2441
2442         signaller = semaphore_waits_for(ring, &seqno);
2443         if (signaller == NULL || signaller->hangcheck.deadlock)
2444                 return -1;
2445
2446         /* cursory check for an unkickable deadlock */
2447         ctl = I915_READ_CTL(signaller);
2448         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2449                 return -1;
2450
2451         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2452 }
2453
2454 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2455 {
2456         struct intel_ring_buffer *ring;
2457         int i;
2458
2459         for_each_ring(ring, dev_priv, i)
2460                 ring->hangcheck.deadlock = false;
2461 }
2462
2463 static enum intel_ring_hangcheck_action
2464 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2465 {
2466         struct drm_device *dev = ring->dev;
2467         struct drm_i915_private *dev_priv = dev->dev_private;
2468         u32 tmp;
2469
2470         if (ring->hangcheck.acthd != acthd)
2471                 return HANGCHECK_ACTIVE;
2472
2473         if (IS_GEN2(dev))
2474                 return HANGCHECK_HUNG;
2475
2476         /* Is the chip hanging on a WAIT_FOR_EVENT?
2477          * If so we can simply poke the RB_WAIT bit
2478          * and break the hang. This should work on
2479          * all but the second generation chipsets.
2480          */
2481         tmp = I915_READ_CTL(ring);
2482         if (tmp & RING_WAIT) {
2483                 DRM_ERROR("Kicking stuck wait on %s\n",
2484                           ring->name);
2485                 i915_handle_error(dev, false);
2486                 I915_WRITE_CTL(ring, tmp);
2487                 return HANGCHECK_KICK;
2488         }
2489
2490         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2491                 switch (semaphore_passed(ring)) {
2492                 default:
2493                         return HANGCHECK_HUNG;
2494                 case 1:
2495                         DRM_ERROR("Kicking stuck semaphore on %s\n",
2496                                   ring->name);
2497                         i915_handle_error(dev, false);
2498                         I915_WRITE_CTL(ring, tmp);
2499                         return HANGCHECK_KICK;
2500                 case 0:
2501                         return HANGCHECK_WAIT;
2502                 }
2503         }
2504
2505         return HANGCHECK_HUNG;
2506 }
2507
2508 /**
2509  * This is called when the chip hasn't reported back with completed
2510  * batchbuffers in a long time. We keep track per ring seqno progress and
2511  * if there are no progress, hangcheck score for that ring is increased.
2512  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2513  * we kick the ring. If we see no progress on three subsequent calls
2514  * we assume chip is wedged and try to fix it by resetting the chip.
2515  */
2516 static void i915_hangcheck_elapsed(unsigned long data)
2517 {
2518         struct drm_device *dev = (struct drm_device *)data;
2519         drm_i915_private_t *dev_priv = dev->dev_private;
2520         struct intel_ring_buffer *ring;
2521         int i;
2522         int busy_count = 0, rings_hung = 0;
2523         bool stuck[I915_NUM_RINGS] = { 0 };
2524 #define BUSY 1
2525 #define KICK 5
2526 #define HUNG 20
2527
2528         if (!i915.enable_hangcheck)
2529                 return;
2530
2531         for_each_ring(ring, dev_priv, i) {
2532                 u32 seqno, acthd;
2533                 bool busy = true;
2534
2535                 semaphore_clear_deadlocks(dev_priv);
2536
2537                 seqno = ring->get_seqno(ring, false);
2538                 acthd = intel_ring_get_active_head(ring);
2539
2540                 if (ring->hangcheck.seqno == seqno) {
2541                         if (ring_idle(ring, seqno)) {
2542                                 ring->hangcheck.action = HANGCHECK_IDLE;
2543
2544                                 if (waitqueue_active(&ring->irq_queue)) {
2545                                         /* Issue a wake-up to catch stuck h/w. */
2546                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2547                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2548                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2549                                                                   ring->name);
2550                                                 else
2551                                                         DRM_INFO("Fake missed irq on %s\n",
2552                                                                  ring->name);
2553                                                 wake_up_all(&ring->irq_queue);
2554                                         }
2555                                         /* Safeguard against driver failure */
2556                                         ring->hangcheck.score += BUSY;
2557                                 } else
2558                                         busy = false;
2559                         } else {
2560                                 /* We always increment the hangcheck score
2561                                  * if the ring is busy and still processing
2562                                  * the same request, so that no single request
2563                                  * can run indefinitely (such as a chain of
2564                                  * batches). The only time we do not increment
2565                                  * the hangcheck score on this ring, if this
2566                                  * ring is in a legitimate wait for another
2567                                  * ring. In that case the waiting ring is a
2568                                  * victim and we want to be sure we catch the
2569                                  * right culprit. Then every time we do kick
2570                                  * the ring, add a small increment to the
2571                                  * score so that we can catch a batch that is
2572                                  * being repeatedly kicked and so responsible
2573                                  * for stalling the machine.
2574                                  */
2575                                 ring->hangcheck.action = ring_stuck(ring,
2576                                                                     acthd);
2577
2578                                 switch (ring->hangcheck.action) {
2579                                 case HANGCHECK_IDLE:
2580                                 case HANGCHECK_WAIT:
2581                                         break;
2582                                 case HANGCHECK_ACTIVE:
2583                                         ring->hangcheck.score += BUSY;
2584                                         break;
2585                                 case HANGCHECK_KICK:
2586                                         ring->hangcheck.score += KICK;
2587                                         break;
2588                                 case HANGCHECK_HUNG:
2589                                         ring->hangcheck.score += HUNG;
2590                                         stuck[i] = true;
2591                                         break;
2592                                 }
2593                         }
2594                 } else {
2595                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2596
2597                         /* Gradually reduce the count so that we catch DoS
2598                          * attempts across multiple batches.
2599                          */
2600                         if (ring->hangcheck.score > 0)
2601                                 ring->hangcheck.score--;
2602                 }
2603
2604                 ring->hangcheck.seqno = seqno;
2605                 ring->hangcheck.acthd = acthd;
2606                 busy_count += busy;
2607         }
2608
2609         for_each_ring(ring, dev_priv, i) {
2610                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2611                         DRM_INFO("%s on %s\n",
2612                                  stuck[i] ? "stuck" : "no progress",
2613                                  ring->name);
2614                         rings_hung++;
2615                 }
2616         }
2617
2618         if (rings_hung)
2619                 return i915_handle_error(dev, true);
2620
2621         if (busy_count)
2622                 /* Reset timer case chip hangs without another request
2623                  * being added */
2624                 i915_queue_hangcheck(dev);
2625 }
2626
2627 void i915_queue_hangcheck(struct drm_device *dev)
2628 {
2629         struct drm_i915_private *dev_priv = dev->dev_private;
2630         if (!i915.enable_hangcheck)
2631                 return;
2632
2633         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2634                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2635 }
2636
2637 static void ibx_irq_preinstall(struct drm_device *dev)
2638 {
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640
2641         if (HAS_PCH_NOP(dev))
2642                 return;
2643
2644         /* south display irq */
2645         I915_WRITE(SDEIMR, 0xffffffff);
2646         /*
2647          * SDEIER is also touched by the interrupt handler to work around missed
2648          * PCH interrupts. Hence we can't update it after the interrupt handler
2649          * is enabled - instead we unconditionally enable all PCH interrupt
2650          * sources here, but then only unmask them as needed with SDEIMR.
2651          */
2652         I915_WRITE(SDEIER, 0xffffffff);
2653         POSTING_READ(SDEIER);
2654 }
2655
2656 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2657 {
2658         struct drm_i915_private *dev_priv = dev->dev_private;
2659
2660         /* and GT */
2661         I915_WRITE(GTIMR, 0xffffffff);
2662         I915_WRITE(GTIER, 0x0);
2663         POSTING_READ(GTIER);
2664
2665         if (INTEL_INFO(dev)->gen >= 6) {
2666                 /* and PM */
2667                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2668                 I915_WRITE(GEN6_PMIER, 0x0);
2669                 POSTING_READ(GEN6_PMIER);
2670         }
2671 }
2672
2673 /* drm_dma.h hooks
2674 */
2675 static void ironlake_irq_preinstall(struct drm_device *dev)
2676 {
2677         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2678
2679         I915_WRITE(HWSTAM, 0xeffe);
2680
2681         I915_WRITE(DEIMR, 0xffffffff);
2682         I915_WRITE(DEIER, 0x0);
2683         POSTING_READ(DEIER);
2684
2685         gen5_gt_irq_preinstall(dev);
2686
2687         ibx_irq_preinstall(dev);
2688 }
2689
2690 static void valleyview_irq_preinstall(struct drm_device *dev)
2691 {
2692         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2693         int pipe;
2694
2695         /* VLV magic */
2696         I915_WRITE(VLV_IMR, 0);
2697         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2698         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2699         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2700
2701         /* and GT */
2702         I915_WRITE(GTIIR, I915_READ(GTIIR));
2703         I915_WRITE(GTIIR, I915_READ(GTIIR));
2704
2705         gen5_gt_irq_preinstall(dev);
2706
2707         I915_WRITE(DPINVGTT, 0xff);
2708
2709         I915_WRITE(PORT_HOTPLUG_EN, 0);
2710         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2711         for_each_pipe(pipe)
2712                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2713         I915_WRITE(VLV_IIR, 0xffffffff);
2714         I915_WRITE(VLV_IMR, 0xffffffff);
2715         I915_WRITE(VLV_IER, 0x0);
2716         POSTING_READ(VLV_IER);
2717 }
2718
2719 static void gen8_irq_preinstall(struct drm_device *dev)
2720 {
2721         struct drm_i915_private *dev_priv = dev->dev_private;
2722         int pipe;
2723
2724         I915_WRITE(GEN8_MASTER_IRQ, 0);
2725         POSTING_READ(GEN8_MASTER_IRQ);
2726
2727         /* IIR can theoretically queue up two events. Be paranoid */
2728 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2729                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2730                 POSTING_READ(GEN8_##type##_IMR(which)); \
2731                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2732                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2733                 POSTING_READ(GEN8_##type##_IIR(which)); \
2734                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2735         } while (0)
2736
2737 #define GEN8_IRQ_INIT(type) do { \
2738                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2739                 POSTING_READ(GEN8_##type##_IMR); \
2740                 I915_WRITE(GEN8_##type##_IER, 0); \
2741                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2742                 POSTING_READ(GEN8_##type##_IIR); \
2743                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2744         } while (0)
2745
2746         GEN8_IRQ_INIT_NDX(GT, 0);
2747         GEN8_IRQ_INIT_NDX(GT, 1);
2748         GEN8_IRQ_INIT_NDX(GT, 2);
2749         GEN8_IRQ_INIT_NDX(GT, 3);
2750
2751         for_each_pipe(pipe) {
2752                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2753         }
2754
2755         GEN8_IRQ_INIT(DE_PORT);
2756         GEN8_IRQ_INIT(DE_MISC);
2757         GEN8_IRQ_INIT(PCU);
2758 #undef GEN8_IRQ_INIT
2759 #undef GEN8_IRQ_INIT_NDX
2760
2761         POSTING_READ(GEN8_PCU_IIR);
2762
2763         ibx_irq_preinstall(dev);
2764 }
2765
2766 static void ibx_hpd_irq_setup(struct drm_device *dev)
2767 {
2768         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2769         struct drm_mode_config *mode_config = &dev->mode_config;
2770         struct intel_encoder *intel_encoder;
2771         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2772
2773         if (HAS_PCH_IBX(dev)) {
2774                 hotplug_irqs = SDE_HOTPLUG_MASK;
2775                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2776                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2777                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2778         } else {
2779                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2780                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2781                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2782                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2783         }
2784
2785         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2786
2787         /*
2788          * Enable digital hotplug on the PCH, and configure the DP short pulse
2789          * duration to 2ms (which is the minimum in the Display Port spec)
2790          *
2791          * This register is the same on all known PCH chips.
2792          */
2793         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2794         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2795         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2796         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2797         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2798         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2799 }
2800
2801 static void ibx_irq_postinstall(struct drm_device *dev)
2802 {
2803         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2804         u32 mask;
2805
2806         if (HAS_PCH_NOP(dev))
2807                 return;
2808
2809         if (HAS_PCH_IBX(dev)) {
2810                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2811                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2812         } else {
2813                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2814
2815                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2816         }
2817
2818         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2819         I915_WRITE(SDEIMR, ~mask);
2820 }
2821
2822 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2823 {
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         u32 pm_irqs, gt_irqs;
2826
2827         pm_irqs = gt_irqs = 0;
2828
2829         dev_priv->gt_irq_mask = ~0;
2830         if (HAS_L3_DPF(dev)) {
2831                 /* L3 parity interrupt is always unmasked. */
2832                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2833                 gt_irqs |= GT_PARITY_ERROR(dev);
2834         }
2835
2836         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2837         if (IS_GEN5(dev)) {
2838                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2839                            ILK_BSD_USER_INTERRUPT;
2840         } else {
2841                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2842         }
2843
2844         I915_WRITE(GTIIR, I915_READ(GTIIR));
2845         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2846         I915_WRITE(GTIER, gt_irqs);
2847         POSTING_READ(GTIER);
2848
2849         if (INTEL_INFO(dev)->gen >= 6) {
2850                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2851
2852                 if (HAS_VEBOX(dev))
2853                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2854
2855                 dev_priv->pm_irq_mask = 0xffffffff;
2856                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2857                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2858                 I915_WRITE(GEN6_PMIER, pm_irqs);
2859                 POSTING_READ(GEN6_PMIER);
2860         }
2861 }
2862
2863 static int ironlake_irq_postinstall(struct drm_device *dev)
2864 {
2865         unsigned long irqflags;
2866         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2867         u32 display_mask, extra_mask;
2868
2869         if (INTEL_INFO(dev)->gen >= 7) {
2870                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2871                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2872                                 DE_PLANEB_FLIP_DONE_IVB |
2873                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2874                                 DE_ERR_INT_IVB);
2875                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2876                               DE_PIPEA_VBLANK_IVB);
2877
2878                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2879         } else {
2880                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2881                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2882                                 DE_AUX_CHANNEL_A |
2883                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2884                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2885                                 DE_POISON);
2886                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2887         }
2888
2889         dev_priv->irq_mask = ~display_mask;
2890
2891         /* should always can generate irq */
2892         I915_WRITE(DEIIR, I915_READ(DEIIR));
2893         I915_WRITE(DEIMR, dev_priv->irq_mask);
2894         I915_WRITE(DEIER, display_mask | extra_mask);
2895         POSTING_READ(DEIER);
2896
2897         gen5_gt_irq_postinstall(dev);
2898
2899         ibx_irq_postinstall(dev);
2900
2901         if (IS_IRONLAKE_M(dev)) {
2902                 /* Enable PCU event interrupts
2903                  *
2904                  * spinlocking not required here for correctness since interrupt
2905                  * setup is guaranteed to run in single-threaded context. But we
2906                  * need it to make the assert_spin_locked happy. */
2907                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2908                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2909                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2910         }
2911
2912         return 0;
2913 }
2914
2915 static int valleyview_irq_postinstall(struct drm_device *dev)
2916 {
2917         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2918         u32 enable_mask;
2919         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2920                 PIPE_CRC_DONE_ENABLE;
2921         unsigned long irqflags;
2922
2923         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2924         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2925                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2926                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2927                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2928
2929         /*
2930          *Leave vblank interrupts masked initially.  enable/disable will
2931          * toggle them based on usage.
2932          */
2933         dev_priv->irq_mask = (~enable_mask) |
2934                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2935                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2936
2937         I915_WRITE(PORT_HOTPLUG_EN, 0);
2938         POSTING_READ(PORT_HOTPLUG_EN);
2939
2940         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2941         I915_WRITE(VLV_IER, enable_mask);
2942         I915_WRITE(VLV_IIR, 0xffffffff);
2943         I915_WRITE(PIPESTAT(0), 0xffff);
2944         I915_WRITE(PIPESTAT(1), 0xffff);
2945         POSTING_READ(VLV_IER);
2946
2947         /* Interrupt setup is already guaranteed to be single-threaded, this is
2948          * just to make the assert_spin_locked check happy. */
2949         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2950         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2951         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2952         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2953         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2954
2955         I915_WRITE(VLV_IIR, 0xffffffff);
2956         I915_WRITE(VLV_IIR, 0xffffffff);
2957
2958         gen5_gt_irq_postinstall(dev);
2959
2960         /* ack & enable invalid PTE error interrupts */
2961 #if 0 /* FIXME: add support to irq handler for checking these bits */
2962         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2963         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2964 #endif
2965
2966         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2967
2968         return 0;
2969 }
2970
2971 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2972 {
2973         int i;
2974
2975         /* These are interrupts we'll toggle with the ring mask register */
2976         uint32_t gt_interrupts[] = {
2977                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2978                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2979                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2980                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2981                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2982                 0,
2983                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2984                 };
2985
2986         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2987                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2988                 if (tmp)
2989                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2990                                   i, tmp);
2991                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2992                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2993         }
2994         POSTING_READ(GEN8_GT_IER(0));
2995 }
2996
2997 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2998 {
2999         struct drm_device *dev = dev_priv->dev;
3000         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3001                 GEN8_PIPE_CDCLK_CRC_DONE |
3002                 GEN8_PIPE_FIFO_UNDERRUN |
3003                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3004         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
3005         int pipe;
3006         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3007         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3008         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3009
3010         for_each_pipe(pipe) {
3011                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
3012                 if (tmp)
3013                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3014                                   pipe, tmp);
3015                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3016                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3017         }
3018         POSTING_READ(GEN8_DE_PIPE_ISR(0));
3019
3020         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3021         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3022         POSTING_READ(GEN8_DE_PORT_IER);
3023 }
3024
3025 static int gen8_irq_postinstall(struct drm_device *dev)
3026 {
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028
3029         gen8_gt_irq_postinstall(dev_priv);
3030         gen8_de_irq_postinstall(dev_priv);
3031
3032         ibx_irq_postinstall(dev);
3033
3034         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3035         POSTING_READ(GEN8_MASTER_IRQ);
3036
3037         return 0;
3038 }
3039
3040 static void gen8_irq_uninstall(struct drm_device *dev)
3041 {
3042         struct drm_i915_private *dev_priv = dev->dev_private;
3043         int pipe;
3044
3045         if (!dev_priv)
3046                 return;
3047
3048         I915_WRITE(GEN8_MASTER_IRQ, 0);
3049
3050 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3051                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3052                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3053                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3054         } while (0)
3055
3056 #define GEN8_IRQ_FINI(type) do { \
3057                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3058                 I915_WRITE(GEN8_##type##_IER, 0); \
3059                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3060         } while (0)
3061
3062         GEN8_IRQ_FINI_NDX(GT, 0);
3063         GEN8_IRQ_FINI_NDX(GT, 1);
3064         GEN8_IRQ_FINI_NDX(GT, 2);
3065         GEN8_IRQ_FINI_NDX(GT, 3);
3066
3067         for_each_pipe(pipe) {
3068                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3069         }
3070
3071         GEN8_IRQ_FINI(DE_PORT);
3072         GEN8_IRQ_FINI(DE_MISC);
3073         GEN8_IRQ_FINI(PCU);
3074 #undef GEN8_IRQ_FINI
3075 #undef GEN8_IRQ_FINI_NDX
3076
3077         POSTING_READ(GEN8_PCU_IIR);
3078 }
3079
3080 static void valleyview_irq_uninstall(struct drm_device *dev)
3081 {
3082         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3083         int pipe;
3084
3085         if (!dev_priv)
3086                 return;
3087
3088         intel_hpd_irq_uninstall(dev_priv);
3089
3090         for_each_pipe(pipe)
3091                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3092
3093         I915_WRITE(HWSTAM, 0xffffffff);
3094         I915_WRITE(PORT_HOTPLUG_EN, 0);
3095         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3096         for_each_pipe(pipe)
3097                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3098         I915_WRITE(VLV_IIR, 0xffffffff);
3099         I915_WRITE(VLV_IMR, 0xffffffff);
3100         I915_WRITE(VLV_IER, 0x0);
3101         POSTING_READ(VLV_IER);
3102 }
3103
3104 static void ironlake_irq_uninstall(struct drm_device *dev)
3105 {
3106         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3107
3108         if (!dev_priv)
3109                 return;
3110
3111         intel_hpd_irq_uninstall(dev_priv);
3112
3113         I915_WRITE(HWSTAM, 0xffffffff);
3114
3115         I915_WRITE(DEIMR, 0xffffffff);
3116         I915_WRITE(DEIER, 0x0);
3117         I915_WRITE(DEIIR, I915_READ(DEIIR));
3118         if (IS_GEN7(dev))
3119                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3120
3121         I915_WRITE(GTIMR, 0xffffffff);
3122         I915_WRITE(GTIER, 0x0);
3123         I915_WRITE(GTIIR, I915_READ(GTIIR));
3124
3125         if (HAS_PCH_NOP(dev))
3126                 return;
3127
3128         I915_WRITE(SDEIMR, 0xffffffff);
3129         I915_WRITE(SDEIER, 0x0);
3130         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3131         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3132                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3133 }
3134
3135 static void i8xx_irq_preinstall(struct drm_device * dev)
3136 {
3137         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3138         int pipe;
3139
3140         for_each_pipe(pipe)
3141                 I915_WRITE(PIPESTAT(pipe), 0);
3142         I915_WRITE16(IMR, 0xffff);
3143         I915_WRITE16(IER, 0x0);
3144         POSTING_READ16(IER);
3145 }
3146
3147 static int i8xx_irq_postinstall(struct drm_device *dev)
3148 {
3149         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3150         unsigned long irqflags;
3151
3152         I915_WRITE16(EMR,
3153                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3154
3155         /* Unmask the interrupts that we always want on. */
3156         dev_priv->irq_mask =
3157                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3158                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3159                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3160                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3161                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3162         I915_WRITE16(IMR, dev_priv->irq_mask);
3163
3164         I915_WRITE16(IER,
3165                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3166                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3167                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3168                      I915_USER_INTERRUPT);
3169         POSTING_READ16(IER);
3170
3171         /* Interrupt setup is already guaranteed to be single-threaded, this is
3172          * just to make the assert_spin_locked check happy. */
3173         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3174         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3175         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3176         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3177
3178         return 0;
3179 }
3180
3181 /*
3182  * Returns true when a page flip has completed.
3183  */
3184 static bool i8xx_handle_vblank(struct drm_device *dev,
3185                                int plane, int pipe, u32 iir)
3186 {
3187         drm_i915_private_t *dev_priv = dev->dev_private;
3188         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3189
3190         if (!drm_handle_vblank(dev, pipe))
3191                 return false;
3192
3193         if ((iir & flip_pending) == 0)
3194                 return false;
3195
3196         intel_prepare_page_flip(dev, plane);
3197
3198         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3199          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3200          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3201          * the flip is completed (no longer pending). Since this doesn't raise
3202          * an interrupt per se, we watch for the change at vblank.
3203          */
3204         if (I915_READ16(ISR) & flip_pending)
3205                 return false;
3206
3207         intel_finish_page_flip(dev, pipe);
3208
3209         return true;
3210 }
3211
3212 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3213 {
3214         struct drm_device *dev = (struct drm_device *) arg;
3215         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3216         u16 iir, new_iir;
3217         u32 pipe_stats[2];
3218         unsigned long irqflags;
3219         int pipe;
3220         u16 flip_mask =
3221                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3222                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3223
3224         iir = I915_READ16(IIR);
3225         if (iir == 0)
3226                 return IRQ_NONE;
3227
3228         while (iir & ~flip_mask) {
3229                 /* Can't rely on pipestat interrupt bit in iir as it might
3230                  * have been cleared after the pipestat interrupt was received.
3231                  * It doesn't set the bit in iir again, but it still produces
3232                  * interrupts (for non-MSI).
3233                  */
3234                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3235                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3236                         i915_handle_error(dev, false);
3237
3238                 for_each_pipe(pipe) {
3239                         int reg = PIPESTAT(pipe);
3240                         pipe_stats[pipe] = I915_READ(reg);
3241
3242                         /*
3243                          * Clear the PIPE*STAT regs before the IIR
3244                          */
3245                         if (pipe_stats[pipe] & 0x8000ffff)
3246                                 I915_WRITE(reg, pipe_stats[pipe]);
3247                 }
3248                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3249
3250                 I915_WRITE16(IIR, iir & ~flip_mask);
3251                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3252
3253                 i915_update_dri1_breadcrumb(dev);
3254
3255                 if (iir & I915_USER_INTERRUPT)
3256                         notify_ring(dev, &dev_priv->ring[RCS]);
3257
3258                 for_each_pipe(pipe) {
3259                         int plane = pipe;
3260                         if (HAS_FBC(dev))
3261                                 plane = !plane;
3262
3263                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3264                             i8xx_handle_vblank(dev, plane, pipe, iir))
3265                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3266
3267                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3268                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3269
3270                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3271                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3272                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3273                 }
3274
3275                 iir = new_iir;
3276         }
3277
3278         return IRQ_HANDLED;
3279 }
3280
3281 static void i8xx_irq_uninstall(struct drm_device * dev)
3282 {
3283         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3284         int pipe;
3285
3286         for_each_pipe(pipe) {
3287                 /* Clear enable bits; then clear status bits */
3288                 I915_WRITE(PIPESTAT(pipe), 0);
3289                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3290         }
3291         I915_WRITE16(IMR, 0xffff);
3292         I915_WRITE16(IER, 0x0);
3293         I915_WRITE16(IIR, I915_READ16(IIR));
3294 }
3295
3296 static void i915_irq_preinstall(struct drm_device * dev)
3297 {
3298         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3299         int pipe;
3300
3301         if (I915_HAS_HOTPLUG(dev)) {
3302                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3303                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3304         }
3305
3306         I915_WRITE16(HWSTAM, 0xeffe);
3307         for_each_pipe(pipe)
3308                 I915_WRITE(PIPESTAT(pipe), 0);
3309         I915_WRITE(IMR, 0xffffffff);
3310         I915_WRITE(IER, 0x0);
3311         POSTING_READ(IER);
3312 }
3313
3314 static int i915_irq_postinstall(struct drm_device *dev)
3315 {
3316         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3317         u32 enable_mask;
3318         unsigned long irqflags;
3319
3320         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3321
3322         /* Unmask the interrupts that we always want on. */
3323         dev_priv->irq_mask =
3324                 ~(I915_ASLE_INTERRUPT |
3325                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3326                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3327                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3328                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3329                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3330
3331         enable_mask =
3332                 I915_ASLE_INTERRUPT |
3333                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3334                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3335                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3336                 I915_USER_INTERRUPT;
3337
3338         if (I915_HAS_HOTPLUG(dev)) {
3339                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3340                 POSTING_READ(PORT_HOTPLUG_EN);
3341
3342                 /* Enable in IER... */
3343                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3344                 /* and unmask in IMR */
3345                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3346         }
3347
3348         I915_WRITE(IMR, dev_priv->irq_mask);
3349         I915_WRITE(IER, enable_mask);
3350         POSTING_READ(IER);
3351
3352         i915_enable_asle_pipestat(dev);
3353
3354         /* Interrupt setup is already guaranteed to be single-threaded, this is
3355          * just to make the assert_spin_locked check happy. */
3356         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3357         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3358         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3359         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3360
3361         return 0;
3362 }
3363
3364 /*
3365  * Returns true when a page flip has completed.
3366  */
3367 static bool i915_handle_vblank(struct drm_device *dev,
3368                                int plane, int pipe, u32 iir)
3369 {
3370         drm_i915_private_t *dev_priv = dev->dev_private;
3371         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3372
3373         if (!drm_handle_vblank(dev, pipe))
3374                 return false;
3375
3376         if ((iir & flip_pending) == 0)
3377                 return false;
3378
3379         intel_prepare_page_flip(dev, plane);
3380
3381         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3382          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3383          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3384          * the flip is completed (no longer pending). Since this doesn't raise
3385          * an interrupt per se, we watch for the change at vblank.
3386          */
3387         if (I915_READ(ISR) & flip_pending)
3388                 return false;
3389
3390         intel_finish_page_flip(dev, pipe);
3391
3392         return true;
3393 }
3394
3395 static irqreturn_t i915_irq_handler(int irq, void *arg)
3396 {
3397         struct drm_device *dev = (struct drm_device *) arg;
3398         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3399         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3400         unsigned long irqflags;
3401         u32 flip_mask =
3402                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3403                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3404         int pipe, ret = IRQ_NONE;
3405
3406         iir = I915_READ(IIR);
3407         do {
3408                 bool irq_received = (iir & ~flip_mask) != 0;
3409                 bool blc_event = false;
3410
3411                 /* Can't rely on pipestat interrupt bit in iir as it might
3412                  * have been cleared after the pipestat interrupt was received.
3413                  * It doesn't set the bit in iir again, but it still produces
3414                  * interrupts (for non-MSI).
3415                  */
3416                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3417                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3418                         i915_handle_error(dev, false);
3419
3420                 for_each_pipe(pipe) {
3421                         int reg = PIPESTAT(pipe);
3422                         pipe_stats[pipe] = I915_READ(reg);
3423
3424                         /* Clear the PIPE*STAT regs before the IIR */
3425                         if (pipe_stats[pipe] & 0x8000ffff) {
3426                                 I915_WRITE(reg, pipe_stats[pipe]);
3427                                 irq_received = true;
3428                         }
3429                 }
3430                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3431
3432                 if (!irq_received)
3433                         break;
3434
3435                 /* Consume port.  Then clear IIR or we'll miss events */
3436                 if ((I915_HAS_HOTPLUG(dev)) &&
3437                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3438                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3439                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3440
3441                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3442
3443                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3444                         POSTING_READ(PORT_HOTPLUG_STAT);
3445                 }
3446
3447                 I915_WRITE(IIR, iir & ~flip_mask);
3448                 new_iir = I915_READ(IIR); /* Flush posted writes */
3449
3450                 if (iir & I915_USER_INTERRUPT)
3451                         notify_ring(dev, &dev_priv->ring[RCS]);
3452
3453                 for_each_pipe(pipe) {
3454                         int plane = pipe;
3455                         if (HAS_FBC(dev))
3456                                 plane = !plane;
3457
3458                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3459                             i915_handle_vblank(dev, plane, pipe, iir))
3460                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3461
3462                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3463                                 blc_event = true;
3464
3465                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3466                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3467
3468                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3469                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3470                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3471                 }
3472
3473                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3474                         intel_opregion_asle_intr(dev);
3475
3476                 /* With MSI, interrupts are only generated when iir
3477                  * transitions from zero to nonzero.  If another bit got
3478                  * set while we were handling the existing iir bits, then
3479                  * we would never get another interrupt.
3480                  *
3481                  * This is fine on non-MSI as well, as if we hit this path
3482                  * we avoid exiting the interrupt handler only to generate
3483                  * another one.
3484                  *
3485                  * Note that for MSI this could cause a stray interrupt report
3486                  * if an interrupt landed in the time between writing IIR and
3487                  * the posting read.  This should be rare enough to never
3488                  * trigger the 99% of 100,000 interrupts test for disabling
3489                  * stray interrupts.
3490                  */
3491                 ret = IRQ_HANDLED;
3492                 iir = new_iir;
3493         } while (iir & ~flip_mask);
3494
3495         i915_update_dri1_breadcrumb(dev);
3496
3497         return ret;
3498 }
3499
3500 static void i915_irq_uninstall(struct drm_device * dev)
3501 {
3502         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3503         int pipe;
3504
3505         intel_hpd_irq_uninstall(dev_priv);
3506
3507         if (I915_HAS_HOTPLUG(dev)) {
3508                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3509                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3510         }
3511
3512         I915_WRITE16(HWSTAM, 0xffff);
3513         for_each_pipe(pipe) {
3514                 /* Clear enable bits; then clear status bits */
3515                 I915_WRITE(PIPESTAT(pipe), 0);
3516                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3517         }
3518         I915_WRITE(IMR, 0xffffffff);
3519         I915_WRITE(IER, 0x0);
3520
3521         I915_WRITE(IIR, I915_READ(IIR));
3522 }
3523
3524 static void i965_irq_preinstall(struct drm_device * dev)
3525 {
3526         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3527         int pipe;
3528
3529         I915_WRITE(PORT_HOTPLUG_EN, 0);
3530         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3531
3532         I915_WRITE(HWSTAM, 0xeffe);
3533         for_each_pipe(pipe)
3534                 I915_WRITE(PIPESTAT(pipe), 0);
3535         I915_WRITE(IMR, 0xffffffff);
3536         I915_WRITE(IER, 0x0);
3537         POSTING_READ(IER);
3538 }
3539
3540 static int i965_irq_postinstall(struct drm_device *dev)
3541 {
3542         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3543         u32 enable_mask;
3544         u32 error_mask;
3545         unsigned long irqflags;
3546
3547         /* Unmask the interrupts that we always want on. */
3548         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3549                                I915_DISPLAY_PORT_INTERRUPT |
3550                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3551                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3552                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3553                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3554                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3555
3556         enable_mask = ~dev_priv->irq_mask;
3557         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3558                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3559         enable_mask |= I915_USER_INTERRUPT;
3560
3561         if (IS_G4X(dev))
3562                 enable_mask |= I915_BSD_USER_INTERRUPT;
3563
3564         /* Interrupt setup is already guaranteed to be single-threaded, this is
3565          * just to make the assert_spin_locked check happy. */
3566         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3567         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3568         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3569         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3570         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3571
3572         /*
3573          * Enable some error detection, note the instruction error mask
3574          * bit is reserved, so we leave it masked.
3575          */
3576         if (IS_G4X(dev)) {
3577                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3578                                GM45_ERROR_MEM_PRIV |
3579                                GM45_ERROR_CP_PRIV |
3580                                I915_ERROR_MEMORY_REFRESH);
3581         } else {
3582                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3583                                I915_ERROR_MEMORY_REFRESH);
3584         }
3585         I915_WRITE(EMR, error_mask);
3586
3587         I915_WRITE(IMR, dev_priv->irq_mask);
3588         I915_WRITE(IER, enable_mask);
3589         POSTING_READ(IER);
3590
3591         I915_WRITE(PORT_HOTPLUG_EN, 0);
3592         POSTING_READ(PORT_HOTPLUG_EN);
3593
3594         i915_enable_asle_pipestat(dev);
3595
3596         return 0;
3597 }
3598
3599 static void i915_hpd_irq_setup(struct drm_device *dev)
3600 {
3601         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3602         struct drm_mode_config *mode_config = &dev->mode_config;
3603         struct intel_encoder *intel_encoder;
3604         u32 hotplug_en;
3605
3606         assert_spin_locked(&dev_priv->irq_lock);
3607
3608         if (I915_HAS_HOTPLUG(dev)) {
3609                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3610                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3611                 /* Note HDMI and DP share hotplug bits */
3612                 /* enable bits are the same for all generations */
3613                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3614                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3615                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3616                 /* Programming the CRT detection parameters tends
3617                    to generate a spurious hotplug event about three
3618                    seconds later.  So just do it once.
3619                 */
3620                 if (IS_G4X(dev))
3621                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3622                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3623                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3624
3625                 /* Ignore TV since it's buggy */
3626                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3627         }
3628 }
3629
3630 static irqreturn_t i965_irq_handler(int irq, void *arg)
3631 {
3632         struct drm_device *dev = (struct drm_device *) arg;
3633         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3634         u32 iir, new_iir;
3635         u32 pipe_stats[I915_MAX_PIPES];
3636         unsigned long irqflags;
3637         int ret = IRQ_NONE, pipe;
3638         u32 flip_mask =
3639                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3640                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3641
3642         iir = I915_READ(IIR);
3643
3644         for (;;) {
3645                 bool irq_received = (iir & ~flip_mask) != 0;
3646                 bool blc_event = false;
3647
3648                 /* Can't rely on pipestat interrupt bit in iir as it might
3649                  * have been cleared after the pipestat interrupt was received.
3650                  * It doesn't set the bit in iir again, but it still produces
3651                  * interrupts (for non-MSI).
3652                  */
3653                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3654                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3655                         i915_handle_error(dev, false);
3656
3657                 for_each_pipe(pipe) {
3658                         int reg = PIPESTAT(pipe);
3659                         pipe_stats[pipe] = I915_READ(reg);
3660
3661                         /*
3662                          * Clear the PIPE*STAT regs before the IIR
3663                          */
3664                         if (pipe_stats[pipe] & 0x8000ffff) {
3665                                 I915_WRITE(reg, pipe_stats[pipe]);
3666                                 irq_received = true;
3667                         }
3668                 }
3669                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3670
3671                 if (!irq_received)
3672                         break;
3673
3674                 ret = IRQ_HANDLED;
3675
3676                 /* Consume port.  Then clear IIR or we'll miss events */
3677                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3678                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3679                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3680                                                                   HOTPLUG_INT_STATUS_G4X :
3681                                                                   HOTPLUG_INT_STATUS_I915);
3682
3683                         intel_hpd_irq_handler(dev, hotplug_trigger,
3684                                               IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3685
3686                         if (IS_G4X(dev) &&
3687                             (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3688                                 dp_aux_irq_handler(dev);
3689
3690                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3691                         I915_READ(PORT_HOTPLUG_STAT);
3692                 }
3693
3694                 I915_WRITE(IIR, iir & ~flip_mask);
3695                 new_iir = I915_READ(IIR); /* Flush posted writes */
3696
3697                 if (iir & I915_USER_INTERRUPT)
3698                         notify_ring(dev, &dev_priv->ring[RCS]);
3699                 if (iir & I915_BSD_USER_INTERRUPT)
3700                         notify_ring(dev, &dev_priv->ring[VCS]);
3701
3702                 for_each_pipe(pipe) {
3703                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3704                             i915_handle_vblank(dev, pipe, pipe, iir))
3705                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3706
3707                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3708                                 blc_event = true;
3709
3710                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3711                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3712
3713                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3714                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3715                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3716                 }
3717
3718                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3719                         intel_opregion_asle_intr(dev);
3720
3721                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3722                         gmbus_irq_handler(dev);
3723
3724                 /* With MSI, interrupts are only generated when iir
3725                  * transitions from zero to nonzero.  If another bit got
3726                  * set while we were handling the existing iir bits, then
3727                  * we would never get another interrupt.
3728                  *
3729                  * This is fine on non-MSI as well, as if we hit this path
3730                  * we avoid exiting the interrupt handler only to generate
3731                  * another one.
3732                  *
3733                  * Note that for MSI this could cause a stray interrupt report
3734                  * if an interrupt landed in the time between writing IIR and
3735                  * the posting read.  This should be rare enough to never
3736                  * trigger the 99% of 100,000 interrupts test for disabling
3737                  * stray interrupts.
3738                  */
3739                 iir = new_iir;
3740         }
3741
3742         i915_update_dri1_breadcrumb(dev);
3743
3744         return ret;
3745 }
3746
3747 static void i965_irq_uninstall(struct drm_device * dev)
3748 {
3749         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3750         int pipe;
3751
3752         if (!dev_priv)
3753                 return;
3754
3755         intel_hpd_irq_uninstall(dev_priv);
3756
3757         I915_WRITE(PORT_HOTPLUG_EN, 0);
3758         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3759
3760         I915_WRITE(HWSTAM, 0xffffffff);
3761         for_each_pipe(pipe)
3762                 I915_WRITE(PIPESTAT(pipe), 0);
3763         I915_WRITE(IMR, 0xffffffff);
3764         I915_WRITE(IER, 0x0);
3765
3766         for_each_pipe(pipe)
3767                 I915_WRITE(PIPESTAT(pipe),
3768                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3769         I915_WRITE(IIR, I915_READ(IIR));
3770 }
3771
3772 static void intel_hpd_irq_reenable(unsigned long data)
3773 {
3774         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3775         struct drm_device *dev = dev_priv->dev;
3776         struct drm_mode_config *mode_config = &dev->mode_config;
3777         unsigned long irqflags;
3778         int i;
3779
3780         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3781         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3782                 struct drm_connector *connector;
3783
3784                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3785                         continue;
3786
3787                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3788
3789                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3790                         struct intel_connector *intel_connector = to_intel_connector(connector);
3791
3792                         if (intel_connector->encoder->hpd_pin == i) {
3793                                 if (connector->polled != intel_connector->polled)
3794                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3795                                                          drm_get_connector_name(connector));
3796                                 connector->polled = intel_connector->polled;
3797                                 if (!connector->polled)
3798                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3799                         }
3800                 }
3801         }
3802         if (dev_priv->display.hpd_irq_setup)
3803                 dev_priv->display.hpd_irq_setup(dev);
3804         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3805 }
3806
3807 void intel_irq_init(struct drm_device *dev)
3808 {
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810
3811         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3812         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3813         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3814         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3815
3816         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3817                     i915_hangcheck_elapsed,
3818                     (unsigned long) dev);
3819         setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
3820                     (unsigned long) dev_priv);
3821
3822         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3823
3824         if (IS_GEN2(dev)) {
3825                 dev->max_vblank_count = 0;
3826                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3827         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3828                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3829                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3830         } else {
3831                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3832                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3833         }
3834
3835         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3836                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3837                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3838         }
3839
3840         if (IS_VALLEYVIEW(dev)) {
3841                 dev->driver->irq_handler = valleyview_irq_handler;
3842                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3843                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3844                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3845                 dev->driver->enable_vblank = valleyview_enable_vblank;
3846                 dev->driver->disable_vblank = valleyview_disable_vblank;
3847                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3848         } else if (IS_GEN8(dev)) {
3849                 dev->driver->irq_handler = gen8_irq_handler;
3850                 dev->driver->irq_preinstall = gen8_irq_preinstall;
3851                 dev->driver->irq_postinstall = gen8_irq_postinstall;
3852                 dev->driver->irq_uninstall = gen8_irq_uninstall;
3853                 dev->driver->enable_vblank = gen8_enable_vblank;
3854                 dev->driver->disable_vblank = gen8_disable_vblank;
3855                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3856         } else if (HAS_PCH_SPLIT(dev)) {
3857                 dev->driver->irq_handler = ironlake_irq_handler;
3858                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3859                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3860                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3861                 dev->driver->enable_vblank = ironlake_enable_vblank;
3862                 dev->driver->disable_vblank = ironlake_disable_vblank;
3863                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3864         } else {
3865                 if (INTEL_INFO(dev)->gen == 2) {
3866                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3867                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3868                         dev->driver->irq_handler = i8xx_irq_handler;
3869                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3870                 } else if (INTEL_INFO(dev)->gen == 3) {
3871                         dev->driver->irq_preinstall = i915_irq_preinstall;
3872                         dev->driver->irq_postinstall = i915_irq_postinstall;
3873                         dev->driver->irq_uninstall = i915_irq_uninstall;
3874                         dev->driver->irq_handler = i915_irq_handler;
3875                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3876                 } else {
3877                         dev->driver->irq_preinstall = i965_irq_preinstall;
3878                         dev->driver->irq_postinstall = i965_irq_postinstall;
3879                         dev->driver->irq_uninstall = i965_irq_uninstall;
3880                         dev->driver->irq_handler = i965_irq_handler;
3881                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3882                 }
3883                 dev->driver->enable_vblank = i915_enable_vblank;
3884                 dev->driver->disable_vblank = i915_disable_vblank;
3885         }
3886 }
3887
3888 void intel_hpd_init(struct drm_device *dev)
3889 {
3890         struct drm_i915_private *dev_priv = dev->dev_private;
3891         struct drm_mode_config *mode_config = &dev->mode_config;
3892         struct drm_connector *connector;
3893         unsigned long irqflags;
3894         int i;
3895
3896         for (i = 1; i < HPD_NUM_PINS; i++) {
3897                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3898                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3899         }
3900         list_for_each_entry(connector, &mode_config->connector_list, head) {
3901                 struct intel_connector *intel_connector = to_intel_connector(connector);
3902                 connector->polled = intel_connector->polled;
3903                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3904                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3905         }
3906
3907         /* Interrupt setup is already guaranteed to be single-threaded, this is
3908          * just to make the assert_spin_locked checks happy. */
3909         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3910         if (dev_priv->display.hpd_irq_setup)
3911                 dev_priv->display.hpd_irq_setup(dev);
3912         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3913 }
3914
3915 /* Disable interrupts so we can allow Package C8+. */
3916 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3917 {
3918         struct drm_i915_private *dev_priv = dev->dev_private;
3919         unsigned long irqflags;
3920
3921         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3922
3923         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3924         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3925         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3926         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3927         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3928
3929         ironlake_disable_display_irq(dev_priv, 0xffffffff);
3930         ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3931         ilk_disable_gt_irq(dev_priv, 0xffffffff);
3932         snb_disable_pm_irq(dev_priv, 0xffffffff);
3933
3934         dev_priv->pc8.irqs_disabled = true;
3935
3936         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3937 }
3938
3939 /* Restore interrupts so we can recover from Package C8+. */
3940 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3941 {
3942         struct drm_i915_private *dev_priv = dev->dev_private;
3943         unsigned long irqflags;
3944         uint32_t val;
3945
3946         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3947
3948         val = I915_READ(DEIMR);
3949         WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3950
3951         val = I915_READ(SDEIMR);
3952         WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3953
3954         val = I915_READ(GTIMR);
3955         WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3956
3957         val = I915_READ(GEN6_PMIMR);
3958         WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3959
3960         dev_priv->pc8.irqs_disabled = false;
3961
3962         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3963         ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3964         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3965         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3966         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3967
3968         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3969 }