2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - CPUFreq support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 enum cpufreq_level_index {
15 L10, L11, L12, L13, L14,
16 L15, L16, L17, L18, L19,
20 enum exynos_soc_type {
27 #define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
30 .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
31 (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \
32 .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
33 .mps = ((m) << 16 | (p) << 8 | (s)), \
43 struct exynos_dvfs_info {
44 enum exynos_soc_type type;
45 unsigned long mpll_freq_khz;
46 unsigned int pll_safe_idx;
48 unsigned int *volt_table;
49 struct cpufreq_frequency_table *freq_table;
50 void (*set_freq)(unsigned int, unsigned int);
51 bool (*need_apll_change)(unsigned int, unsigned int);
54 #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
55 extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
57 static inline int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
62 #ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ
63 extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
65 static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
70 #ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ
71 extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
73 static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
82 #define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200)
83 #define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400)
85 #define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500)
86 #define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504)
87 #define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600)
88 #define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604)
90 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
91 #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
93 #define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000)
94 #define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100)
95 #define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400)
96 #define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500)
97 #define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504)
98 #define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600)
99 #define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604)