drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl / GPIO driver for StarFive JH7100 SoC
   4  *
   5  * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
   6  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
   7  */
   8
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/io.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reset.h>
  18 #include <linux/spinlock.h>
  19
  20 #include <linux/pinctrl/pinctrl.h>
  21 #include <linux/pinctrl/pinmux.h>
  22
  23 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
  24
  25 #include "../core.h"
  26 #include "../pinctrl-utils.h"
  27 #include "../pinmux.h"
  28 #include "../pinconf.h"
  29
  30 #define DRIVER_NAME "pinctrl-starfive"
  31
  32 /*
  33  * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
  34  * https://github.com/starfive-tech/JH7100_Docs
  35  */
  36 #define NR_GPIOS        64
  37
  38 /*
  39  * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
  40  * are enabled. If set to 0 the GPIO interrupts are disabled.
  41  */
  42 #define GPIOEN          0x000
  43
  44 /*
  45  * The following 32-bit registers come in pairs, but only the offset of the
  46  * first register is defined. The first controls (interrupts for) GPIO 0-31 and
  47  * the second GPIO 32-63.
  48  */
  49
  50 /*
  51  * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
  52  * interrupt is level-triggered.
  53  */
  54 #define GPIOIS          0x010
  55
  56 /*
  57  * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
  58  * both positive and negative edges. If set to 0 the interrupt is triggered by a
  59  * single edge.
  60  */
  61 #define GPIOIBE         0x018
  62
  63 /*
  64  * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
  65  * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
  66  * interrupt is triggered on a falling edge (edge-triggered) or low level
  67  * (level-triggered).
  68  */
  69 #define GPIOIEV         0x020
  70
  71 /*
  72  * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
  73  * the interrupt is disabled (masked). Note that the current documentation is
  74  * wrong and says the exct opposite of this.
  75  */
  76 #define GPIOIE          0x028
  77
  78 /*
  79  * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
  80  * interrupt.
  81  */
  82 #define GPIOIC          0x030
  83
  84 /*
  85  * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
  86  */
  87 #define GPIORIS         0x038
  88
  89 /*
  90  * Interrupt Status after Masking. A 1 means the configured edge or level was
  91  * detected and not masked.
  92  */
  93 #define GPIOMIS         0x040
  94
  95 /*
  96  * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
  97  * a digital 1 and if 0 the pin is a digital 0.
  98  */
  99 #define GPIODIN         0x048
 100
 101 /*
 102  * From the data sheet section 12.2, there are 64 32-bit output data registers
 103  * and 64 output enable registers. Output data and output enable registers for
 104  * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
 105  * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c.  The stride
 106  * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
 107  * and GPOn_DOEN_CFG is 0x54 + 8n.
 108  */
 109 #define GPON_DOUT_CFG   0x050
 110 #define GPON_DOEN_CFG   0x054
 111
 112 /*
 113  * From Section 12.3, there are 75 input signal configuration registers which
 114  * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
 115  * GPI_USB_OVER_CURRENT_CFG 0x378
 116  */
 117 #define GPI_CFG_OFFSET  0x250
 118
 119 /*
 120  * Pad Control Bits. There are 16 pad control bits for each pin located in 103
 121  * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
 122  * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
 123  * bit of each register.
 124  */
 125 #define PAD_SLEW_RATE_MASK              GENMASK(11, 9)
 126 #define PAD_SLEW_RATE_POS               9
 127 #define PAD_BIAS_STRONG_PULL_UP         BIT(8)
 128 #define PAD_INPUT_ENABLE                BIT(7)
 129 #define PAD_INPUT_SCHMITT_ENABLE        BIT(6)
 130 #define PAD_BIAS_DISABLE                BIT(5)
 131 #define PAD_BIAS_PULL_DOWN              BIT(4)
 132 #define PAD_BIAS_MASK \
 133         (PAD_BIAS_STRONG_PULL_UP | \
 134          PAD_BIAS_DISABLE | \
 135          PAD_BIAS_PULL_DOWN)
 136 #define PAD_DRIVE_STRENGTH_MASK         GENMASK(3, 0)
 137 #define PAD_DRIVE_STRENGTH_POS          0
 138
 139 /*
 140  * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
 141  * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
 142  * PAD_GPIO pads. This is a global setting.
 143  */
 144 #define IO_PADSHARE_SEL                 0x1a0
 145
 146 /*
 147  * This just needs to be some number such that when
 148  * sfp->gpio.pin_base = PAD_INVALID_GPIO then
 149  * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
 150  * That is it should underflow and return something >= NR_GPIOS.
 151  */
 152 #define PAD_INVALID_GPIO                0x10000
 153
 154 /*
 155  * The packed pinmux values from the device tree look like this:
 156  *
 157  *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
 158  *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
 159  *
 160  * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
 161  *
 162  *  |      31       | 30 - 8 |   7 - 0   |
 163  *  | dout/doen rev | unused | dout/doen |
 164  */
 165 static unsigned int starfive_pinmux_to_gpio(u32 v)
 166 {
 167         return v & (NR_GPIOS - 1);
 168 }
 169
 170 static u32 starfive_pinmux_to_dout(u32 v)
 171 {
 172         return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
 173 }
 174
 175 static u32 starfive_pinmux_to_doen(u32 v)
 176 {
 177         return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
 178 }
 179
 180 static u32 starfive_pinmux_to_din(u32 v)
 181 {
 182         return (v >> 8) & GENMASK(7, 0);
 183 }
 184
 185 /*
 186  * The maximum GPIO output current depends on the chosen drive strength:
 187  *
 188  *  DS:   0     1     2     3     4     5     6     7
 189  *  mA:  14.2  21.2  28.2  35.2  42.2  49.1  56.0  62.8
 190  *
 191  * After rounding that is 7*DS + 14 mA
 192  */
 193 static u32 starfive_drive_strength_to_max_mA(u16 ds)
 194 {
 195         return 7 * ds + 14;
 196 }
 197
 198 static u16 starfive_drive_strength_from_max_mA(u32 i)
 199 {
 200         return (clamp(i, 14U, 63U) - 14) / 7;
 201 }
 202
 203 struct starfive_pinctrl {
 204         struct gpio_chip gc;
 205         struct pinctrl_gpio_range gpios;
 206         raw_spinlock_t lock;
 207         void __iomem *base;
 208         void __iomem *padctl;
 209         struct pinctrl_dev *pctl;
 210         struct mutex mutex; /* serialize adding groups and functions */
 211 };
 212
 213 static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
 214                                                 unsigned int pin)
 215 {
 216         return pin - sfp->gpios.pin_base;
 217 }
 218
 219 static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
 220                                                 unsigned int gpio)
 221 {
 222         return sfp->gpios.pin_base + gpio;
 223 }
 224
 225 static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
 226 {
 227         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 228
 229         return container_of(gc, struct starfive_pinctrl, gc);
 230 }
 231
 232 static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
 233 {
 234         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 235
 236         return container_of(gc, struct starfive_pinctrl, gc);
 237 }
 238
 239 static const struct pinctrl_pin_desc starfive_pins[] = {
 240         PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
 241         PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
 242         PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
 243         PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
 244         PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
 245         PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
 246         PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
 247         PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
 248         PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
 249         PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
 250         PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
 251         PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
 252         PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
 253         PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
 254         PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
 255         PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
 256         PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
 257         PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
 258         PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
 259         PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
 260         PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
 261         PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
 262         PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
 263         PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
 264         PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
 265         PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
 266         PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
 267         PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
 268         PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
 269         PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
 270         PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
 271         PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
 272         PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
 273         PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
 274         PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
 275         PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
 276         PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
 277         PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
 278         PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
 279         PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
 280         PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
 281         PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
 282         PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
 283         PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
 284         PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
 285         PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
 286         PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
 287         PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
 288         PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
 289         PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
 290         PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
 291         PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
 292         PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
 293         PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
 294         PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
 295         PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
 296         PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
 297         PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
 298         PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
 299         PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
 300         PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
 301         PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
 302         PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
 303         PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
 304         PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
 305         PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
 306         PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
 307         PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
 308         PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
 309         PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
 310         PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
 311         PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
 312         PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
 313         PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
 314         PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
 315         PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
 316         PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
 317         PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
 318         PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
 319         PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
 320         PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
 321         PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
 322         PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
 323         PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
 324         PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
 325         PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
 326         PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
 327         PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
 328         PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
 329         PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
 330         PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
 331         PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
 332         PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
 333         PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
 334         PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
 335         PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
 336         PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
 337         PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
 338         PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
 339         PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
 340         PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
 341         PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
 342         PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
 343         PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
 344         PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
 345         PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
 346         PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
 347         PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
 348         PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
 349         PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
 350         PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
 351         PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
 352         PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
 353         PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
 354         PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
 355         PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
 356         PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
 357         PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
 358         PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
 359         PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
 360         PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
 361         PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
 362         PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
 363         PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
 364         PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
 365         PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
 366         PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
 367         PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
 368         PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
 369         PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
 370         PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
 371         PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
 372         PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
 373         PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
 374         PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
 375         PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
 376         PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
 377         PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
 378         PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
 379         PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
 380         PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
 381         PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
 382         PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
 383         PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
 384         PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
 385         PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
 386         PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
 387         PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
 388         PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
 389         PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
 390         PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
 391         PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
 392         PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
 393         PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
 394         PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
 395         PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
 396         PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
 397         PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
 398         PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
 399         PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
 400         PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
 401         PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
 402         PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
 403         PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
 404         PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
 405         PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
 406         PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
 407         PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
 408         PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
 409         PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
 410         PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
 411         PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
 412         PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
 413         PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
 414         PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
 415         PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
 416         PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
 417         PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
 418         PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
 419         PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
 420         PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
 421         PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
 422         PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
 423         PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
 424         PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
 425         PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
 426         PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
 427         PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
 428         PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
 429         PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
 430         PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
 431         PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
 432         PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
 433         PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
 434         PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
 435         PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
 436         PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
 437         PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
 438         PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
 439         PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
 440         PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
 441         PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
 442         PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
 443         PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
 444         PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
 445         PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
 446 };
 447
 448 #ifdef CONFIG_DEBUG_FS
 449 static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
 450                                   struct seq_file *s,
 451                                   unsigned int pin)
 452 {
 453         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 454         unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
 455         void __iomem *reg;
 456         u32 dout, doen;
 457
 458         if (gpio >= NR_GPIOS)
 459                 return;
 460
 461         reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 462         dout = readl_relaxed(reg + 0x000);
 463         doen = readl_relaxed(reg + 0x004);
 464
 465         seq_printf(s, "dout=%lu%s doen=%lu%s",
 466                    dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
 467                    doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
 468 }
 469 #else
 470 #define starfive_pin_dbg_show NULL
 471 #endif
 472
 473 static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
 474                                    struct device_node *np,
 475                                    struct pinctrl_map **maps,
 476                                    unsigned int *num_maps)
 477 {
 478         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 479         struct device *dev = sfp->gc.parent;
 480         struct device_node *child;
 481         struct pinctrl_map *map;
 482         const char **pgnames;
 483         const char *grpname;
 484         u32 *pinmux;
 485         int ngroups;
 486         int *pins;
 487         int nmaps;
 488         int ret;
 489
 490         nmaps = 0;
 491         ngroups = 0;
 492         for_each_child_of_node(np, child) {
 493                 int npinmux = of_property_count_u32_elems(child, "pinmux");
 494                 int npins   = of_property_count_u32_elems(child, "pins");
 495
 496                 if (npinmux > 0 && npins > 0) {
 497                         dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
 498                                 np, child);
 499                         of_node_put(child);
 500                         return -EINVAL;
 501                 }
 502                 if (npinmux == 0 && npins == 0) {
 503                         dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
 504                                 np, child);
 505                         of_node_put(child);
 506                         return -EINVAL;
 507                 }
 508
 509                 if (npinmux > 0)
 510                         nmaps += 2;
 511                 else
 512                         nmaps += 1;
 513                 ngroups += 1;
 514         }
 515
 516         pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
 517         if (!pgnames)
 518                 return -ENOMEM;
 519
 520         map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
 521         if (!map)
 522                 return -ENOMEM;
 523
 524         nmaps = 0;
 525         ngroups = 0;
 526         mutex_lock(&sfp->mutex);
 527         for_each_child_of_node(np, child) {
 528                 int npins;
 529                 int i;
 530
 531                 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
 532                 if (!grpname) {
 533                         ret = -ENOMEM;
 534                         goto put_child;
 535                 }
 536
 537                 pgnames[ngroups++] = grpname;
 538
 539                 if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
 540                         pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
 541                         if (!pins) {
 542                                 ret = -ENOMEM;
 543                                 goto put_child;
 544                         }
 545
 546                         pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
 547                         if (!pinmux) {
 548                                 ret = -ENOMEM;
 549                                 goto put_child;
 550                         }
 551
 552                         ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
 553                         if (ret)
 554                                 goto put_child;
 555
 556                         for (i = 0; i < npins; i++) {
 557                                 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
 558
 559                                 pins[i] = starfive_gpio_to_pin(sfp, gpio);
 560                         }
 561
 562                         map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
 563                         map[nmaps].data.mux.function = np->name;
 564                         map[nmaps].data.mux.group = grpname;
 565                         nmaps += 1;
 566                 } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
 567                         pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
 568                         if (!pins) {
 569                                 ret = -ENOMEM;
 570                                 goto put_child;
 571                         }
 572
 573                         pinmux = NULL;
 574
 575                         for (i = 0; i < npins; i++) {
 576                                 u32 v;
 577
 578                                 ret = of_property_read_u32_index(child, "pins", i, &v);
 579                                 if (ret)
 580                                         goto put_child;
 581                                 pins[i] = v;
 582                         }
 583                 } else {
 584                         ret = -EINVAL;
 585                         goto put_child;
 586                 }
 587
 588                 ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
 589                 if (ret < 0) {
 590                         dev_err(dev, "error adding group %s: %d\n", grpname, ret);
 591                         goto put_child;
 592                 }
 593
 594                 ret = pinconf_generic_parse_dt_config(child, pctldev,
 595                                                       &map[nmaps].data.configs.configs,
 596                                                       &map[nmaps].data.configs.num_configs);
 597                 if (ret) {
 598                         dev_err(dev, "error parsing pin config of group %s: %d\n",
 599                                 grpname, ret);
 600                         goto put_child;
 601                 }
 602
 603                 /* don't create a map if there are no pinconf settings */
 604                 if (map[nmaps].data.configs.num_configs == 0)
 605                         continue;
 606
 607                 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 608                 map[nmaps].data.configs.group_or_pin = grpname;
 609                 nmaps += 1;
 610         }
 611
 612         ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
 613         if (ret < 0) {
 614                 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
 615                 goto free_map;
 616         }
 617
 618         *maps = map;
 619         *num_maps = nmaps;
 620         mutex_unlock(&sfp->mutex);
 621         return 0;
 622
 623 put_child:
 624         of_node_put(child);
 625 free_map:
 626         pinctrl_utils_free_map(pctldev, map, nmaps);
 627         mutex_unlock(&sfp->mutex);
 628         return ret;
 629 }
 630
 631 static const struct pinctrl_ops starfive_pinctrl_ops = {
 632         .get_groups_count = pinctrl_generic_get_group_count,
 633         .get_group_name = pinctrl_generic_get_group_name,
 634         .get_group_pins = pinctrl_generic_get_group_pins,
 635         .pin_dbg_show = starfive_pin_dbg_show,
 636         .dt_node_to_map = starfive_dt_node_to_map,
 637         .dt_free_map = pinctrl_utils_free_map,
 638 };
 639
 640 static int starfive_set_mux(struct pinctrl_dev *pctldev,
 641                             unsigned int fsel, unsigned int gsel)
 642 {
 643         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 644         struct device *dev = sfp->gc.parent;
 645         const struct group_desc *group;
 646         const u32 *pinmux;
 647         unsigned int i;
 648
 649         group = pinctrl_generic_get_group(pctldev, gsel);
 650         if (!group)
 651                 return -EINVAL;
 652
 653         pinmux = group->data;
 654         for (i = 0; i < group->num_pins; i++) {
 655                 u32 v = pinmux[i];
 656                 unsigned int gpio = starfive_pinmux_to_gpio(v);
 657                 u32 dout = starfive_pinmux_to_dout(v);
 658                 u32 doen = starfive_pinmux_to_doen(v);
 659                 u32 din = starfive_pinmux_to_din(v);
 660                 void __iomem *reg_dout;
 661                 void __iomem *reg_doen;
 662                 void __iomem *reg_din;
 663                 unsigned long flags;
 664
 665                 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
 666                         gpio, dout, doen, din);
 667
 668                 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 669                 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 670                 if (din != GPI_NONE)
 671                         reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
 672                 else
 673                         reg_din = NULL;
 674
 675                 raw_spin_lock_irqsave(&sfp->lock, flags);
 676                 writel_relaxed(dout, reg_dout);
 677                 writel_relaxed(doen, reg_doen);
 678                 if (reg_din)
 679                         writel_relaxed(gpio + 2, reg_din);
 680                 raw_spin_unlock_irqrestore(&sfp->lock, flags);
 681         }
 682
 683         return 0;
 684 }
 685
 686 static const struct pinmux_ops starfive_pinmux_ops = {
 687         .get_functions_count = pinmux_generic_get_function_count,
 688         .get_function_name = pinmux_generic_get_function_name,
 689         .get_function_groups = pinmux_generic_get_function_groups,
 690         .set_mux = starfive_set_mux,
 691         .strict = true,
 692 };
 693
 694 static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
 695                                unsigned int pin)
 696 {
 697         void __iomem *reg = sfp->padctl + 4 * (pin / 2);
 698         int shift = 16 * (pin % 2);
 699
 700         return readl_relaxed(reg) >> shift;
 701 }
 702
 703 static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
 704                                 unsigned int pin,
 705                                 u16 _mask, u16 _value)
 706 {
 707         void __iomem *reg = sfp->padctl + 4 * (pin / 2);
 708         int shift = 16 * (pin % 2);
 709         u32 mask = (u32)_mask << shift;
 710         u32 value = (u32)_value << shift;
 711         unsigned long flags;
 712
 713         dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
 714
 715         raw_spin_lock_irqsave(&sfp->lock, flags);
 716         value |= readl_relaxed(reg) & ~mask;
 717         writel_relaxed(value, reg);
 718         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 719 }
 720
 721 #define PIN_CONFIG_STARFIVE_STRONG_PULL_UP      (PIN_CONFIG_END + 1)
 722
 723 static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
 724         { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
 725 };
 726
 727 #ifdef CONFIG_DEBUG_FS
 728 static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
 729         PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
 730 };
 731
 732 static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
 733               ARRAY_SIZE(starfive_pinconf_custom_params));
 734 #else
 735 #define starfive_pinconf_custom_conf_items NULL
 736 #endif
 737
 738 static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
 739                                 unsigned int pin, unsigned long *config)
 740 {
 741         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 742         int param = pinconf_to_config_param(*config);
 743         u16 value = starfive_padctl_get(sfp, pin);
 744         bool enabled;
 745         u32 arg;
 746
 747         switch (param) {
 748         case PIN_CONFIG_BIAS_DISABLE:
 749                 enabled = value & PAD_BIAS_DISABLE;
 750                 arg = 0;
 751                 break;
 752         case PIN_CONFIG_BIAS_PULL_DOWN:
 753                 enabled = value & PAD_BIAS_PULL_DOWN;
 754                 arg = 1;
 755                 break;
 756         case PIN_CONFIG_BIAS_PULL_UP:
 757                 enabled = !(value & PAD_BIAS_MASK);
 758                 arg = 1;
 759                 break;
 760         case PIN_CONFIG_DRIVE_STRENGTH:
 761                 enabled = value & PAD_DRIVE_STRENGTH_MASK;
 762                 arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
 763                 break;
 764         case PIN_CONFIG_INPUT_ENABLE:
 765                 enabled = value & PAD_INPUT_ENABLE;
 766                 arg = enabled;
 767                 break;
 768         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 769                 enabled = value & PAD_INPUT_SCHMITT_ENABLE;
 770                 arg = enabled;
 771                 break;
 772         case PIN_CONFIG_SLEW_RATE:
 773                 enabled = value & PAD_SLEW_RATE_MASK;
 774                 arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
 775                 break;
 776         case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
 777                 enabled = value & PAD_BIAS_STRONG_PULL_UP;
 778                 arg = enabled;
 779                 break;
 780         default:
 781                 return -ENOTSUPP;
 782         }
 783
 784         *config = pinconf_to_config_packed(param, arg);
 785         return enabled ? 0 : -EINVAL;
 786 }
 787
 788 static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
 789                                       unsigned int gsel, unsigned long *config)
 790 {
 791         const struct group_desc *group;
 792
 793         group = pinctrl_generic_get_group(pctldev, gsel);
 794         if (!group)
 795                 return -EINVAL;
 796
 797         return starfive_pinconf_get(pctldev, group->pins[0], config);
 798 }
 799
 800 static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
 801                                       unsigned int gsel,
 802                                       unsigned long *configs,
 803                                       unsigned int num_configs)
 804 {
 805         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 806         const struct group_desc *group;
 807         u16 mask, value;
 808         int i;
 809
 810         group = pinctrl_generic_get_group(pctldev, gsel);
 811         if (!group)
 812                 return -EINVAL;
 813
 814         mask = 0;
 815         value = 0;
 816         for (i = 0; i < num_configs; i++) {
 817                 int param = pinconf_to_config_param(configs[i]);
 818                 u32 arg = pinconf_to_config_argument(configs[i]);
 819
 820                 switch (param) {
 821                 case PIN_CONFIG_BIAS_DISABLE:
 822                         mask |= PAD_BIAS_MASK;
 823                         value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
 824                         break;
 825                 case PIN_CONFIG_BIAS_PULL_DOWN:
 826                         if (arg == 0)
 827                                 return -ENOTSUPP;
 828                         mask |= PAD_BIAS_MASK;
 829                         value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
 830                         break;
 831                 case PIN_CONFIG_BIAS_PULL_UP:
 832                         if (arg == 0)
 833                                 return -ENOTSUPP;
 834                         mask |= PAD_BIAS_MASK;
 835                         value = value & ~PAD_BIAS_MASK;
 836                         break;
 837                 case PIN_CONFIG_DRIVE_STRENGTH:
 838                         mask |= PAD_DRIVE_STRENGTH_MASK;
 839                         value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
 840                                 starfive_drive_strength_from_max_mA(arg);
 841                         break;
 842                 case PIN_CONFIG_INPUT_ENABLE:
 843                         mask |= PAD_INPUT_ENABLE;
 844                         if (arg)
 845                                 value |= PAD_INPUT_ENABLE;
 846                         else
 847                                 value &= ~PAD_INPUT_ENABLE;
 848                         break;
 849                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 850                         mask |= PAD_INPUT_SCHMITT_ENABLE;
 851                         if (arg)
 852                                 value |= PAD_INPUT_SCHMITT_ENABLE;
 853                         else
 854                                 value &= ~PAD_INPUT_SCHMITT_ENABLE;
 855                         break;
 856                 case PIN_CONFIG_SLEW_RATE:
 857                         mask |= PAD_SLEW_RATE_MASK;
 858                         value = (value & ~PAD_SLEW_RATE_MASK) |
 859                                 ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
 860                         break;
 861                 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
 862                         if (arg) {
 863                                 mask |= PAD_BIAS_MASK;
 864                                 value = (value & ~PAD_BIAS_MASK) |
 865                                         PAD_BIAS_STRONG_PULL_UP;
 866                         } else {
 867                                 mask |= PAD_BIAS_STRONG_PULL_UP;
 868                                 value = value & ~PAD_BIAS_STRONG_PULL_UP;
 869                         }
 870                         break;
 871                 default:
 872                         return -ENOTSUPP;
 873                 }
 874         }
 875
 876         for (i = 0; i < group->num_pins; i++)
 877                 starfive_padctl_rmw(sfp, group->pins[i], mask, value);
 878
 879         return 0;
 880 }
 881
 882 #ifdef CONFIG_DEBUG_FS
 883 static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 884                                       struct seq_file *s, unsigned int pin)
 885 {
 886         struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
 887         u16 value = starfive_padctl_get(sfp, pin);
 888
 889         seq_printf(s, " (0x%03x)", value);
 890 }
 891 #else
 892 #define starfive_pinconf_dbg_show NULL
 893 #endif
 894
 895 static const struct pinconf_ops starfive_pinconf_ops = {
 896         .pin_config_get = starfive_pinconf_get,
 897         .pin_config_group_get = starfive_pinconf_group_get,
 898         .pin_config_group_set = starfive_pinconf_group_set,
 899         .pin_config_dbg_show = starfive_pinconf_dbg_show,
 900         .is_generic = true,
 901 };
 902
 903 static struct pinctrl_desc starfive_desc = {
 904         .name = DRIVER_NAME,
 905         .pins = starfive_pins,
 906         .npins = ARRAY_SIZE(starfive_pins),
 907         .pctlops = &starfive_pinctrl_ops,
 908         .pmxops = &starfive_pinmux_ops,
 909         .confops = &starfive_pinconf_ops,
 910         .owner = THIS_MODULE,
 911         .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
 912         .custom_params = starfive_pinconf_custom_params,
 913         .custom_conf_items = starfive_pinconf_custom_conf_items,
 914 };
 915
 916 static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
 917 {
 918         return pinctrl_gpio_request(gc->base + gpio);
 919 }
 920
 921 static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
 922 {
 923         pinctrl_gpio_free(gc->base + gpio);
 924 }
 925
 926 static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
 927 {
 928         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 929         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 930
 931         if (readl_relaxed(doen) == GPO_ENABLE)
 932                 return GPIO_LINE_DIRECTION_OUT;
 933
 934         return GPIO_LINE_DIRECTION_IN;
 935 }
 936
 937 static int starfive_gpio_direction_input(struct gpio_chip *gc,
 938                                          unsigned int gpio)
 939 {
 940         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 941         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 942         unsigned long flags;
 943
 944         /* enable input and schmitt trigger */
 945         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
 946                             PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
 947                             PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
 948
 949         raw_spin_lock_irqsave(&sfp->lock, flags);
 950         writel_relaxed(GPO_DISABLE, doen);
 951         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 952         return 0;
 953 }
 954
 955 static int starfive_gpio_direction_output(struct gpio_chip *gc,
 956                                           unsigned int gpio, int value)
 957 {
 958         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 959         void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 960         void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
 961         unsigned long flags;
 962
 963         raw_spin_lock_irqsave(&sfp->lock, flags);
 964         writel_relaxed(value, dout);
 965         writel_relaxed(GPO_ENABLE, doen);
 966         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 967
 968         /* disable input, schmitt trigger and bias */
 969         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
 970                             PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
 971                             PAD_BIAS_DISABLE);
 972
 973         return 0;
 974 }
 975
 976 static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 977 {
 978         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 979         void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
 980
 981         return !!(readl_relaxed(din) & BIT(gpio % 32));
 982 }
 983
 984 static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
 985                               int value)
 986 {
 987         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
 988         void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
 989         unsigned long flags;
 990
 991         raw_spin_lock_irqsave(&sfp->lock, flags);
 992         writel_relaxed(value, dout);
 993         raw_spin_unlock_irqrestore(&sfp->lock, flags);
 994 }
 995
 996 static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
 997                                     unsigned long config)
 998 {
 999         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1000         u32 arg = pinconf_to_config_argument(config);
1001         u16 value;
1002         u16 mask;
1003
1004         switch (pinconf_to_config_param(config)) {
1005         case PIN_CONFIG_BIAS_DISABLE:
1006                 mask  = PAD_BIAS_MASK;
1007                 value = PAD_BIAS_DISABLE;
1008                 break;
1009         case PIN_CONFIG_BIAS_PULL_DOWN:
1010                 if (arg == 0)
1011                         return -ENOTSUPP;
1012                 mask  = PAD_BIAS_MASK;
1013                 value = PAD_BIAS_PULL_DOWN;
1014                 break;
1015         case PIN_CONFIG_BIAS_PULL_UP:
1016                 if (arg == 0)
1017                         return -ENOTSUPP;
1018                 mask  = PAD_BIAS_MASK;
1019                 value = 0;
1020                 break;
1021         case PIN_CONFIG_DRIVE_PUSH_PULL:
1022                 return 0;
1023         case PIN_CONFIG_INPUT_ENABLE:
1024                 mask  = PAD_INPUT_ENABLE;
1025                 value = arg ? PAD_INPUT_ENABLE : 0;
1026                 break;
1027         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1028                 mask  = PAD_INPUT_SCHMITT_ENABLE;
1029                 value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
1030                 break;
1031         default:
1032                 return -ENOTSUPP;
1033         }
1034
1035         starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
1036         return 0;
1037 }
1038
1039 static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
1040 {
1041         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1042
1043         sfp->gpios.name = sfp->gc.label;
1044         sfp->gpios.base = sfp->gc.base;
1045         /*
1046          * sfp->gpios.pin_base depends on the chosen signal group
1047          * and is set in starfive_probe()
1048          */
1049         sfp->gpios.npins = NR_GPIOS;
1050         sfp->gpios.gc = &sfp->gc;
1051         pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1052         return 0;
1053 }
1054
1055 static void starfive_irq_ack(struct irq_data *d)
1056 {
1057         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1058         irq_hw_number_t gpio = irqd_to_hwirq(d);
1059         void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1060         u32 mask = BIT(gpio % 32);
1061         unsigned long flags;
1062
1063         raw_spin_lock_irqsave(&sfp->lock, flags);
1064         writel_relaxed(mask, ic);
1065         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1066 }
1067
1068 static void starfive_irq_mask(struct irq_data *d)
1069 {
1070         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1071         irq_hw_number_t gpio = irqd_to_hwirq(d);
1072         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1073         u32 mask = BIT(gpio % 32);
1074         unsigned long flags;
1075         u32 value;
1076
1077         raw_spin_lock_irqsave(&sfp->lock, flags);
1078         value = readl_relaxed(ie) & ~mask;
1079         writel_relaxed(value, ie);
1080         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1081
1082         gpiochip_disable_irq(&sfp->gc, d->hwirq);
1083 }
1084
1085 static void starfive_irq_mask_ack(struct irq_data *d)
1086 {
1087         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1088         irq_hw_number_t gpio = irqd_to_hwirq(d);
1089         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1090         void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1091         u32 mask = BIT(gpio % 32);
1092         unsigned long flags;
1093         u32 value;
1094
1095         raw_spin_lock_irqsave(&sfp->lock, flags);
1096         value = readl_relaxed(ie) & ~mask;
1097         writel_relaxed(value, ie);
1098         writel_relaxed(mask, ic);
1099         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1100 }
1101
1102 static void starfive_irq_unmask(struct irq_data *d)
1103 {
1104         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1105         irq_hw_number_t gpio = irqd_to_hwirq(d);
1106         void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1107         u32 mask = BIT(gpio % 32);
1108         unsigned long flags;
1109         u32 value;
1110
1111         gpiochip_enable_irq(&sfp->gc, d->hwirq);
1112
1113         raw_spin_lock_irqsave(&sfp->lock, flags);
1114         value = readl_relaxed(ie) | mask;
1115         writel_relaxed(value, ie);
1116         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1117 }
1118
1119 static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
1120 {
1121         struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1122         irq_hw_number_t gpio = irqd_to_hwirq(d);
1123         void __iomem *base = sfp->base + 4 * (gpio / 32);
1124         u32 mask = BIT(gpio % 32);
1125         u32 irq_type, edge_both, polarity;
1126         unsigned long flags;
1127
1128         switch (trigger) {
1129         case IRQ_TYPE_EDGE_RISING:
1130                 irq_type  = mask; /* 1: edge triggered */
1131                 edge_both = 0;    /* 0: single edge */
1132                 polarity  = mask; /* 1: rising edge */
1133                 break;
1134         case IRQ_TYPE_EDGE_FALLING:
1135                 irq_type  = mask; /* 1: edge triggered */
1136                 edge_both = 0;    /* 0: single edge */
1137                 polarity  = 0;    /* 0: falling edge */
1138                 break;
1139         case IRQ_TYPE_EDGE_BOTH:
1140                 irq_type  = mask; /* 1: edge triggered */
1141                 edge_both = mask; /* 1: both edges */
1142                 polarity  = 0;    /* 0: ignored */
1143                 break;
1144         case IRQ_TYPE_LEVEL_HIGH:
1145                 irq_type  = 0;    /* 0: level triggered */
1146                 edge_both = 0;    /* 0: ignored */
1147                 polarity  = mask; /* 1: high level */
1148                 break;
1149         case IRQ_TYPE_LEVEL_LOW:
1150                 irq_type  = 0;    /* 0: level triggered */
1151                 edge_both = 0;    /* 0: ignored */
1152                 polarity  = 0;    /* 0: low level */
1153                 break;
1154         default:
1155                 return -EINVAL;
1156         }
1157
1158         if (trigger & IRQ_TYPE_EDGE_BOTH)
1159                 irq_set_handler_locked(d, handle_edge_irq);
1160         else
1161                 irq_set_handler_locked(d, handle_level_irq);
1162
1163         raw_spin_lock_irqsave(&sfp->lock, flags);
1164         irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
1165         writel_relaxed(irq_type, base + GPIOIS);
1166         edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
1167         writel_relaxed(edge_both, base + GPIOIBE);
1168         polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
1169         writel_relaxed(polarity, base + GPIOIEV);
1170         raw_spin_unlock_irqrestore(&sfp->lock, flags);
1171         return 0;
1172 }
1173
1174 static const struct irq_chip starfive_irq_chip = {
1175         .name = "StarFive GPIO",
1176         .irq_ack = starfive_irq_ack,
1177         .irq_mask = starfive_irq_mask,
1178         .irq_mask_ack = starfive_irq_mask_ack,
1179         .irq_unmask = starfive_irq_unmask,
1180         .irq_set_type = starfive_irq_set_type,
1181         .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
1182         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1183 };
1184
1185 static void starfive_gpio_irq_handler(struct irq_desc *desc)
1186 {
1187         struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
1188         struct irq_chip *chip = irq_desc_get_chip(desc);
1189         unsigned long mis;
1190         unsigned int pin;
1191
1192         chained_irq_enter(chip, desc);
1193
1194         mis = readl_relaxed(sfp->base + GPIOMIS + 0);
1195         for_each_set_bit(pin, &mis, 32)
1196                 generic_handle_domain_irq(sfp->gc.irq.domain, pin);
1197
1198         mis = readl_relaxed(sfp->base + GPIOMIS + 4);
1199         for_each_set_bit(pin, &mis, 32)
1200                 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
1201
1202         chained_irq_exit(chip, desc);
1203 }
1204
1205 static int starfive_gpio_init_hw(struct gpio_chip *gc)
1206 {
1207         struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1208
1209         /* mask all GPIO interrupts */
1210         writel(0, sfp->base + GPIOIE + 0);
1211         writel(0, sfp->base + GPIOIE + 4);
1212         /* clear edge interrupt flags */
1213         writel(~0U, sfp->base + GPIOIC + 0);
1214         writel(~0U, sfp->base + GPIOIC + 4);
1215         /* enable GPIO interrupts */
1216         writel(1, sfp->base + GPIOEN);
1217         return 0;
1218 }
1219
1220 static void starfive_disable_clock(void *data)
1221 {
1222         clk_disable_unprepare(data);
1223 }
1224
1225 static int starfive_probe(struct platform_device *pdev)
1226 {
1227         struct device *dev = &pdev->dev;
1228         struct starfive_pinctrl *sfp;
1229         struct reset_control *rst;
1230         struct clk *clk;
1231         u32 value;
1232         int ret;
1233
1234         sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1235         if (!sfp)
1236                 return -ENOMEM;
1237
1238         sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
1239         if (IS_ERR(sfp->base))
1240                 return PTR_ERR(sfp->base);
1241
1242         sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
1243         if (IS_ERR(sfp->padctl))
1244                 return PTR_ERR(sfp->padctl);
1245
1246         clk = devm_clk_get(dev, NULL);
1247         if (IS_ERR(clk))
1248                 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
1249
1250         rst = devm_reset_control_get_exclusive(dev, NULL);
1251         if (IS_ERR(rst))
1252                 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
1253
1254         ret = clk_prepare_enable(clk);
1255         if (ret)
1256                 return dev_err_probe(dev, ret, "could not enable clock\n");
1257
1258         ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
1259         if (ret)
1260                 return ret;
1261
1262         /*
1263          * We don't want to assert reset and risk undoing pin muxing for the
1264          * early boot serial console, but let's make sure the reset line is
1265          * deasserted in case someone runs a really minimal bootloader.
1266          */
1267         ret = reset_control_deassert(rst);
1268         if (ret)
1269                 return dev_err_probe(dev, ret, "could not deassert reset\n");
1270
1271         platform_set_drvdata(pdev, sfp);
1272         sfp->gc.parent = dev;
1273         raw_spin_lock_init(&sfp->lock);
1274         mutex_init(&sfp->mutex);
1275
1276         ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
1277         if (ret)
1278                 return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
1279
1280         if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
1281                 if (value > 6)
1282                         return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1283                 writel(value, sfp->padctl + IO_PADSHARE_SEL);
1284         }
1285
1286         value = readl(sfp->padctl + IO_PADSHARE_SEL);
1287         switch (value) {
1288         case 0:
1289                 sfp->gpios.pin_base = PAD_INVALID_GPIO;
1290                 goto out_pinctrl_enable;
1291         case 1:
1292                 sfp->gpios.pin_base = PAD_GPIO(0);
1293                 break;
1294         case 2:
1295                 sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
1296                 break;
1297         case 3:
1298                 sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
1299                 break;
1300         case 4: case 5: case 6:
1301                 sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
1302                 break;
1303         default:
1304                 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1305         }
1306
1307         sfp->gc.label = dev_name(dev);
1308         sfp->gc.owner = THIS_MODULE;
1309         sfp->gc.request = starfive_gpio_request;
1310         sfp->gc.free = starfive_gpio_free;
1311         sfp->gc.get_direction = starfive_gpio_get_direction;
1312         sfp->gc.direction_input = starfive_gpio_direction_input;
1313         sfp->gc.direction_output = starfive_gpio_direction_output;
1314         sfp->gc.get = starfive_gpio_get;
1315         sfp->gc.set = starfive_gpio_set;
1316         sfp->gc.set_config = starfive_gpio_set_config;
1317         sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
1318         sfp->gc.base = -1;
1319         sfp->gc.ngpio = NR_GPIOS;
1320
1321         gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
1322         sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
1323         sfp->gc.irq.num_parents = 1;
1324         sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1325                                            sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
1326         if (!sfp->gc.irq.parents)
1327                 return -ENOMEM;
1328         sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1329         sfp->gc.irq.handler = handle_bad_irq;
1330         sfp->gc.irq.init_hw = starfive_gpio_init_hw;
1331
1332         ret = platform_get_irq(pdev, 0);
1333         if (ret < 0)
1334                 return ret;
1335         sfp->gc.irq.parents[0] = ret;
1336
1337         ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1338         if (ret)
1339                 return dev_err_probe(dev, ret, "could not register gpiochip\n");
1340
1341         irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1342
1343 out_pinctrl_enable:
1344         return pinctrl_enable(sfp->pctl);
1345 }
1346
1347 static const struct of_device_id starfive_of_match[] = {
1348         { .compatible = "starfive,jh7100-pinctrl" },
1349         { /* sentinel */ }
1350 };
1351 MODULE_DEVICE_TABLE(of, starfive_of_match);
1352
1353 static struct platform_driver starfive_pinctrl_driver = {
1354         .probe = starfive_probe,
1355         .driver = {
1356                 .name = DRIVER_NAME,
1357                 .of_match_table = starfive_of_match,
1358         },
1359 };
1360 module_platform_driver(starfive_pinctrl_driver);
1361
1362 MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
1363 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1364 MODULE_LICENSE("GPL v2");