1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
15 #define pr_fmt(fmt) "AER: " fmt
16 #define dev_fmt pr_fmt
18 #include <linux/bitops.h>
19 #include <linux/cper.h>
20 #include <linux/pci.h>
21 #include <linux/pci-acpi.h>
22 #include <linux/sched.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/kfifo.h>
30 #include <linux/slab.h>
31 #include <acpi/apei.h>
32 #include <acpi/ghes.h>
33 #include <ras/ras_event.h>
38 #define AER_ERROR_SOURCES_MAX 128
40 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
41 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
43 struct aer_err_source {
49 struct pci_dev *rpd; /* Root Port device */
50 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
53 /* AER stats for the device */
57 * Fields for all AER capable devices. They indicate the errors
58 * "as seen by this device". Note that this may mean that if an
59 * end point is causing problems, the AER counters may increment
60 * at its link partner (e.g. root port) because the errors will be
61 * "seen" by the link partner and not the problematic end point
62 * itself (which may report all counters as 0 as it never saw any
65 /* Counters for different type of correctable errors */
66 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
67 /* Counters for different type of fatal uncorrectable errors */
68 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
69 /* Counters for different type of nonfatal uncorrectable errors */
70 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
71 /* Total number of ERR_COR sent by this device */
72 u64 dev_total_cor_errs;
73 /* Total number of ERR_FATAL sent by this device */
74 u64 dev_total_fatal_errs;
75 /* Total number of ERR_NONFATAL sent by this device */
76 u64 dev_total_nonfatal_errs;
79 * Fields for Root ports & root complex event collectors only, these
80 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
81 * messages received by the root port / event collector, INCLUDING the
82 * ones that are generated internally (by the rootport itself)
84 u64 rootport_total_cor_errs;
85 u64 rootport_total_fatal_errs;
86 u64 rootport_total_nonfatal_errs;
89 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
92 PCI_ERR_UNC_COMP_ABORT| \
93 PCI_ERR_UNC_UNX_COMP| \
96 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
97 PCI_EXP_RTCTL_SENFEE| \
99 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
100 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
101 PCI_ERR_ROOT_CMD_FATAL_EN)
102 #define ERR_COR_ID(d) (d & 0xffff)
103 #define ERR_UNCOR_ID(d) (d >> 16)
105 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \
106 PCI_ERR_ROOT_COR_RCV | \
107 PCI_ERR_ROOT_MULTI_COR_RCV | \
108 PCI_ERR_ROOT_MULTI_UNCOR_RCV)
110 static int pcie_aer_disable;
111 static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
113 void pci_no_aer(void)
115 pcie_aer_disable = 1;
118 bool pci_aer_available(void)
120 return !pcie_aer_disable && pci_msi_enabled();
123 #ifdef CONFIG_PCIE_ECRC
125 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
126 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
127 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
129 static int ecrc_policy = ECRC_POLICY_DEFAULT;
131 static const char * const ecrc_policy_str[] = {
132 [ECRC_POLICY_DEFAULT] = "bios",
133 [ECRC_POLICY_OFF] = "off",
134 [ECRC_POLICY_ON] = "on"
138 * enable_ecrc_checking - enable PCIe ECRC checking for a device
139 * @dev: the PCI device
141 * Returns 0 on success, or negative on failure.
143 static int enable_ecrc_checking(struct pci_dev *dev)
145 int aer = dev->aer_cap;
151 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
152 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
153 reg32 |= PCI_ERR_CAP_ECRC_GENE;
154 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
155 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
156 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
162 * disable_ecrc_checking - disables PCIe ECRC checking for a device
163 * @dev: the PCI device
165 * Returns 0 on success, or negative on failure.
167 static int disable_ecrc_checking(struct pci_dev *dev)
169 int aer = dev->aer_cap;
175 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
176 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
177 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
183 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
184 * @dev: the PCI device
186 void pcie_set_ecrc_checking(struct pci_dev *dev)
188 if (!pcie_aer_is_native(dev))
191 switch (ecrc_policy) {
192 case ECRC_POLICY_DEFAULT:
194 case ECRC_POLICY_OFF:
195 disable_ecrc_checking(dev);
198 enable_ecrc_checking(dev);
206 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
207 * @str: ECRC policy from kernel command line to use
209 void pcie_ecrc_get_policy(char *str)
213 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
219 #endif /* CONFIG_PCIE_ECRC */
221 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
222 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
224 int pcie_aer_is_native(struct pci_dev *dev)
226 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
231 return pcie_ports_native || host->native_aer;
233 EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, CXL);
235 static int pci_enable_pcie_error_reporting(struct pci_dev *dev)
239 if (!pcie_aer_is_native(dev))
242 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
243 return pcibios_err_to_errno(rc);
246 int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
248 int aer = dev->aer_cap;
251 if (!pcie_aer_is_native(dev))
254 /* Clear status bits for ERR_NONFATAL errors only */
255 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
256 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
259 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
263 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
265 void pci_aer_clear_fatal_status(struct pci_dev *dev)
267 int aer = dev->aer_cap;
270 if (!pcie_aer_is_native(dev))
273 /* Clear status bits for ERR_FATAL errors only */
274 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
275 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
278 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
282 * pci_aer_raw_clear_status - Clear AER error registers.
283 * @dev: the PCI device
285 * Clearing AER error status registers unconditionally, regardless of
286 * whether they're owned by firmware or the OS.
288 * Returns 0 on success, or negative on failure.
290 int pci_aer_raw_clear_status(struct pci_dev *dev)
292 int aer = dev->aer_cap;
299 port_type = pci_pcie_type(dev);
300 if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
301 port_type == PCI_EXP_TYPE_RC_EC) {
302 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
303 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
306 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
307 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
309 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
310 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
315 int pci_aer_clear_status(struct pci_dev *dev)
317 if (!pcie_aer_is_native(dev))
320 return pci_aer_raw_clear_status(dev);
323 void pci_save_aer_state(struct pci_dev *dev)
325 int aer = dev->aer_cap;
326 struct pci_cap_saved_state *save_state;
332 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
336 cap = &save_state->cap.data[0];
337 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
338 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
339 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
340 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
341 if (pcie_cap_has_rtctl(dev))
342 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
345 void pci_restore_aer_state(struct pci_dev *dev)
347 int aer = dev->aer_cap;
348 struct pci_cap_saved_state *save_state;
354 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
358 cap = &save_state->cap.data[0];
359 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
360 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
361 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
362 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
363 if (pcie_cap_has_rtctl(dev))
364 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
367 void pci_aer_init(struct pci_dev *dev)
371 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
375 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
378 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
379 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
380 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
383 n = pcie_cap_has_rtctl(dev) ? 5 : 4;
384 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
386 pci_aer_clear_status(dev);
388 if (pci_aer_available())
389 pci_enable_pcie_error_reporting(dev);
391 pcie_set_ecrc_checking(dev);
394 void pci_aer_exit(struct pci_dev *dev)
396 kfree(dev->aer_stats);
397 dev->aer_stats = NULL;
400 #define AER_AGENT_RECEIVER 0
401 #define AER_AGENT_REQUESTER 1
402 #define AER_AGENT_COMPLETER 2
403 #define AER_AGENT_TRANSMITTER 3
405 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
406 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
407 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
408 0 : PCI_ERR_UNC_COMP_ABORT)
409 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
410 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
412 #define AER_GET_AGENT(t, e) \
413 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
414 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
415 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
418 #define AER_PHYSICAL_LAYER_ERROR 0
419 #define AER_DATA_LINK_LAYER_ERROR 1
420 #define AER_TRANSACTION_LAYER_ERROR 2
422 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
423 PCI_ERR_COR_RCVR : 0)
424 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
425 (PCI_ERR_COR_BAD_TLP| \
426 PCI_ERR_COR_BAD_DLLP| \
427 PCI_ERR_COR_REP_ROLL| \
428 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
430 #define AER_GET_LAYER_ERROR(t, e) \
431 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
432 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
433 AER_TRANSACTION_LAYER_ERROR)
438 static const char *aer_error_severity_string[] = {
439 "Uncorrected (Non-Fatal)",
440 "Uncorrected (Fatal)",
444 static const char *aer_error_layer[] = {
450 static const char *aer_correctable_error_string[] = {
451 "RxErr", /* Bit Position 0 */
457 "BadTLP", /* Bit Position 6 */
458 "BadDLLP", /* Bit Position 7 */
459 "Rollover", /* Bit Position 8 */
463 "Timeout", /* Bit Position 12 */
464 "NonFatalErr", /* Bit Position 13 */
465 "CorrIntErr", /* Bit Position 14 */
466 "HeaderOF", /* Bit Position 15 */
467 NULL, /* Bit Position 16 */
468 NULL, /* Bit Position 17 */
469 NULL, /* Bit Position 18 */
470 NULL, /* Bit Position 19 */
471 NULL, /* Bit Position 20 */
472 NULL, /* Bit Position 21 */
473 NULL, /* Bit Position 22 */
474 NULL, /* Bit Position 23 */
475 NULL, /* Bit Position 24 */
476 NULL, /* Bit Position 25 */
477 NULL, /* Bit Position 26 */
478 NULL, /* Bit Position 27 */
479 NULL, /* Bit Position 28 */
480 NULL, /* Bit Position 29 */
481 NULL, /* Bit Position 30 */
482 NULL, /* Bit Position 31 */
485 static const char *aer_uncorrectable_error_string[] = {
486 "Undefined", /* Bit Position 0 */
490 "DLP", /* Bit Position 4 */
491 "SDES", /* Bit Position 5 */
498 "TLP", /* Bit Position 12 */
499 "FCP", /* Bit Position 13 */
500 "CmpltTO", /* Bit Position 14 */
501 "CmpltAbrt", /* Bit Position 15 */
502 "UnxCmplt", /* Bit Position 16 */
503 "RxOF", /* Bit Position 17 */
504 "MalfTLP", /* Bit Position 18 */
505 "ECRC", /* Bit Position 19 */
506 "UnsupReq", /* Bit Position 20 */
507 "ACSViol", /* Bit Position 21 */
508 "UncorrIntErr", /* Bit Position 22 */
509 "BlockedTLP", /* Bit Position 23 */
510 "AtomicOpBlocked", /* Bit Position 24 */
511 "TLPBlockedErr", /* Bit Position 25 */
512 "PoisonTLPBlocked", /* Bit Position 26 */
513 NULL, /* Bit Position 27 */
514 NULL, /* Bit Position 28 */
515 NULL, /* Bit Position 29 */
516 NULL, /* Bit Position 30 */
517 NULL, /* Bit Position 31 */
520 static const char *aer_agent_string[] = {
527 #define aer_stats_dev_attr(name, stats_array, strings_array, \
528 total_string, total_field) \
530 name##_show(struct device *dev, struct device_attribute *attr, \
534 struct pci_dev *pdev = to_pci_dev(dev); \
535 u64 *stats = pdev->aer_stats->stats_array; \
538 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\
539 if (strings_array[i]) \
540 len += sysfs_emit_at(buf, len, "%s %llu\n", \
544 len += sysfs_emit_at(buf, len, \
545 #stats_array "_bit[%d] %llu\n",\
548 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \
549 pdev->aer_stats->total_field); \
552 static DEVICE_ATTR_RO(name)
554 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
555 aer_correctable_error_string, "ERR_COR",
557 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
558 aer_uncorrectable_error_string, "ERR_FATAL",
559 dev_total_fatal_errs);
560 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
561 aer_uncorrectable_error_string, "ERR_NONFATAL",
562 dev_total_nonfatal_errs);
564 #define aer_stats_rootport_attr(name, field) \
566 name##_show(struct device *dev, struct device_attribute *attr, \
569 struct pci_dev *pdev = to_pci_dev(dev); \
570 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \
572 static DEVICE_ATTR_RO(name)
574 aer_stats_rootport_attr(aer_rootport_total_err_cor,
575 rootport_total_cor_errs);
576 aer_stats_rootport_attr(aer_rootport_total_err_fatal,
577 rootport_total_fatal_errs);
578 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
579 rootport_total_nonfatal_errs);
581 static struct attribute *aer_stats_attrs[] __ro_after_init = {
582 &dev_attr_aer_dev_correctable.attr,
583 &dev_attr_aer_dev_fatal.attr,
584 &dev_attr_aer_dev_nonfatal.attr,
585 &dev_attr_aer_rootport_total_err_cor.attr,
586 &dev_attr_aer_rootport_total_err_fatal.attr,
587 &dev_attr_aer_rootport_total_err_nonfatal.attr,
591 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
592 struct attribute *a, int n)
594 struct device *dev = kobj_to_dev(kobj);
595 struct pci_dev *pdev = to_pci_dev(dev);
597 if (!pdev->aer_stats)
600 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
601 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
602 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
603 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
604 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC)))
610 const struct attribute_group aer_stats_attr_group = {
611 .attrs = aer_stats_attrs,
612 .is_visible = aer_stats_attrs_are_visible,
615 static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
616 struct aer_err_info *info)
618 unsigned long status = info->status & ~info->mask;
621 struct aer_stats *aer_stats = pdev->aer_stats;
626 switch (info->severity) {
627 case AER_CORRECTABLE:
628 aer_stats->dev_total_cor_errs++;
629 counter = &aer_stats->dev_cor_errs[0];
630 max = AER_MAX_TYPEOF_COR_ERRS;
633 aer_stats->dev_total_nonfatal_errs++;
634 counter = &aer_stats->dev_nonfatal_errs[0];
635 max = AER_MAX_TYPEOF_UNCOR_ERRS;
638 aer_stats->dev_total_fatal_errs++;
639 counter = &aer_stats->dev_fatal_errs[0];
640 max = AER_MAX_TYPEOF_UNCOR_ERRS;
644 for_each_set_bit(i, &status, max)
648 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
649 struct aer_err_source *e_src)
651 struct aer_stats *aer_stats = pdev->aer_stats;
656 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
657 aer_stats->rootport_total_cor_errs++;
659 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
660 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
661 aer_stats->rootport_total_fatal_errs++;
663 aer_stats->rootport_total_nonfatal_errs++;
667 static void __print_tlp_header(struct pci_dev *dev,
668 struct aer_header_log_regs *t)
670 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
671 t->dw0, t->dw1, t->dw2, t->dw3);
674 static void __aer_print_error(struct pci_dev *dev,
675 struct aer_err_info *info)
677 const char **strings;
678 unsigned long status = info->status & ~info->mask;
679 const char *level, *errmsg;
682 if (info->severity == AER_CORRECTABLE) {
683 strings = aer_correctable_error_string;
684 level = KERN_WARNING;
686 strings = aer_uncorrectable_error_string;
690 for_each_set_bit(i, &status, 32) {
693 errmsg = "Unknown Error Bit";
695 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
696 info->first_error == i ? " (First)" : "");
698 pci_dev_aer_stats_incr(dev, info);
701 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
704 int id = pci_dev_id(dev);
708 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
709 aer_error_severity_string[info->severity]);
713 layer = AER_GET_LAYER_ERROR(info->severity, info->status);
714 agent = AER_GET_AGENT(info->severity, info->status);
716 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
718 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
719 aer_error_severity_string[info->severity],
720 aer_error_layer[layer], aer_agent_string[agent]);
722 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
723 dev->vendor, dev->device, info->status, info->mask);
725 __aer_print_error(dev, info);
727 if (info->tlp_header_valid)
728 __print_tlp_header(dev, &info->tlp);
731 if (info->id && info->error_dev_num > 1 && info->id == id)
732 pci_err(dev, " Error of this Agent is reported first\n");
734 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
735 info->severity, info->tlp_header_valid, &info->tlp);
738 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
740 u8 bus = info->id >> 8;
741 u8 devfn = info->id & 0xff;
743 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
744 info->multi_error_valid ? "Multiple " : "",
745 aer_error_severity_string[info->severity],
746 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
750 #ifdef CONFIG_ACPI_APEI_PCIEAER
751 int cper_severity_to_aer(int cper_severity)
753 switch (cper_severity) {
754 case CPER_SEV_RECOVERABLE:
759 return AER_CORRECTABLE;
762 EXPORT_SYMBOL_GPL(cper_severity_to_aer);
765 void pci_print_aer(struct pci_dev *dev, int aer_severity,
766 struct aer_capability_regs *aer)
768 int layer, agent, tlp_header_valid = 0;
770 struct aer_err_info info;
772 if (aer_severity == AER_CORRECTABLE) {
773 status = aer->cor_status;
774 mask = aer->cor_mask;
776 status = aer->uncor_status;
777 mask = aer->uncor_mask;
778 tlp_header_valid = status & AER_LOG_TLP_MASKS;
781 layer = AER_GET_LAYER_ERROR(aer_severity, status);
782 agent = AER_GET_AGENT(aer_severity, status);
784 memset(&info, 0, sizeof(info));
785 info.severity = aer_severity;
786 info.status = status;
788 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
790 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
791 __aer_print_error(dev, &info);
792 pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
793 aer_error_layer[layer], aer_agent_string[agent]);
795 if (aer_severity != AER_CORRECTABLE)
796 pci_err(dev, "aer_uncor_severity: 0x%08x\n",
797 aer->uncor_severity);
799 if (tlp_header_valid)
800 __print_tlp_header(dev, &aer->header_log);
802 trace_aer_event(dev_name(&dev->dev), (status & ~mask),
803 aer_severity, tlp_header_valid, &aer->header_log);
805 EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL);
808 * add_error_device - list device to be handled
809 * @e_info: pointer to error info
810 * @dev: pointer to pci_dev to be added
812 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
814 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
815 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
816 e_info->error_dev_num++;
823 * is_error_source - check whether the device is source of reported error
824 * @dev: pointer to pci_dev to be checked
825 * @e_info: pointer to reported error info
827 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
829 int aer = dev->aer_cap;
834 * When bus id is equal to 0, it might be a bad id
835 * reported by root port.
837 if ((PCI_BUS_NUM(e_info->id) != 0) &&
838 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
839 /* Device ID match? */
840 if (e_info->id == pci_dev_id(dev))
843 /* Continue id comparing if there is no multiple error */
844 if (!e_info->multi_error_valid)
850 * 1) bus id is equal to 0. Some ports might lose the bus
851 * id of error source id;
852 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
853 * 3) There are multiple errors and prior ID comparing fails;
854 * We check AER status registers to find possible reporter.
856 if (atomic_read(&dev->enable_cnt) == 0)
859 /* Check if AER is enabled */
860 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
861 if (!(reg16 & PCI_EXP_AER_FLAGS))
867 /* Check if error is recorded */
868 if (e_info->severity == AER_CORRECTABLE) {
869 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
870 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
872 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
873 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
881 static int find_device_iter(struct pci_dev *dev, void *data)
883 struct aer_err_info *e_info = (struct aer_err_info *)data;
885 if (is_error_source(dev, e_info)) {
886 /* List this device */
887 if (add_error_device(e_info, dev)) {
888 /* We cannot handle more... Stop iteration */
889 /* TODO: Should print error message here? */
893 /* If there is only a single error, stop iteration */
894 if (!e_info->multi_error_valid)
901 * find_source_device - search through device hierarchy for source device
902 * @parent: pointer to Root Port pci_dev data structure
903 * @e_info: including detailed error information such like id
905 * Return true if found.
907 * Invoked by DPC when error is detected at the Root Port.
908 * Caller of this function must set id, severity, and multi_error_valid of
909 * struct aer_err_info pointed by @e_info properly. This function must fill
910 * e_info->error_dev_num and e_info->dev[], based on the given information.
912 static bool find_source_device(struct pci_dev *parent,
913 struct aer_err_info *e_info)
915 struct pci_dev *dev = parent;
918 /* Must reset in this function */
919 e_info->error_dev_num = 0;
921 /* Is Root Port an agent that sends error message? */
922 result = find_device_iter(dev, e_info);
926 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC)
927 pcie_walk_rcec(parent, find_device_iter, e_info);
929 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
931 if (!e_info->error_dev_num) {
932 pci_info(parent, "can't find device of ID%04x\n", e_info->id);
938 #ifdef CONFIG_PCIEAER_CXL
941 * pci_aer_unmask_internal_errors - unmask internal errors
942 * @dev: pointer to the pcie_dev data structure
944 * Unmasks internal errors in the Uncorrectable and Correctable Error
947 * Note: AER must be enabled and supported by the device which must be
948 * checked in advance, e.g. with pcie_aer_is_native().
950 static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
952 int aer = dev->aer_cap;
955 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
956 mask &= ~PCI_ERR_UNC_INTN;
957 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
959 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
960 mask &= ~PCI_ERR_COR_INTERNAL;
961 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
964 static bool is_cxl_mem_dev(struct pci_dev *dev)
967 * The capability, status, and control fields in Device 0,
968 * Function 0 DVSEC control the CXL functionality of the
969 * entire device (CXL 3.0, 8.1.3).
971 if (dev->devfn != PCI_DEVFN(0, 0))
975 * CXL Memory Devices must have the 502h class code set (CXL
978 if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL)
984 static bool cxl_error_is_native(struct pci_dev *dev)
986 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
988 return (pcie_ports_native || host->native_aer);
991 static bool is_internal_error(struct aer_err_info *info)
993 if (info->severity == AER_CORRECTABLE)
994 return info->status & PCI_ERR_COR_INTERNAL;
996 return info->status & PCI_ERR_UNC_INTN;
999 static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
1001 struct aer_err_info *info = (struct aer_err_info *)data;
1002 const struct pci_error_handlers *err_handler;
1004 if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
1007 /* protect dev->driver */
1008 device_lock(&dev->dev);
1010 err_handler = dev->driver ? dev->driver->err_handler : NULL;
1014 if (info->severity == AER_CORRECTABLE) {
1015 if (err_handler->cor_error_detected)
1016 err_handler->cor_error_detected(dev);
1017 } else if (err_handler->error_detected) {
1018 if (info->severity == AER_NONFATAL)
1019 err_handler->error_detected(dev, pci_channel_io_normal);
1020 else if (info->severity == AER_FATAL)
1021 err_handler->error_detected(dev, pci_channel_io_frozen);
1024 device_unlock(&dev->dev);
1028 static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
1031 * Internal errors of an RCEC indicate an AER error in an
1032 * RCH's downstream port. Check and handle them in the CXL.mem
1035 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
1036 is_internal_error(info))
1037 pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
1040 static int handles_cxl_error_iter(struct pci_dev *dev, void *data)
1042 bool *handles_cxl = data;
1045 *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev);
1047 /* Non-zero terminates iteration */
1048 return *handles_cxl;
1051 static bool handles_cxl_errors(struct pci_dev *rcec)
1053 bool handles_cxl = false;
1055 if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC &&
1056 pcie_aer_is_native(rcec))
1057 pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl);
1062 static void cxl_rch_enable_rcec(struct pci_dev *rcec)
1064 if (!handles_cxl_errors(rcec))
1067 pci_aer_unmask_internal_errors(rcec);
1068 pci_info(rcec, "CXL: Internal errors unmasked");
1072 static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { }
1073 static inline void cxl_rch_handle_error(struct pci_dev *dev,
1074 struct aer_err_info *info) { }
1078 * pci_aer_handle_error - handle logging error into an event log
1079 * @dev: pointer to pci_dev data structure of error source device
1080 * @info: comprehensive error information
1082 * Invoked when an error being detected by Root Port.
1084 static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info)
1086 int aer = dev->aer_cap;
1088 if (info->severity == AER_CORRECTABLE) {
1090 * Correctable error does not need software intervention.
1091 * No need to go through error recovery process.
1094 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1096 if (pcie_aer_is_native(dev)) {
1097 struct pci_driver *pdrv = dev->driver;
1099 if (pdrv && pdrv->err_handler &&
1100 pdrv->err_handler->cor_error_detected)
1101 pdrv->err_handler->cor_error_detected(dev);
1102 pcie_clear_device_status(dev);
1104 } else if (info->severity == AER_NONFATAL)
1105 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
1106 else if (info->severity == AER_FATAL)
1107 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
1110 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
1112 cxl_rch_handle_error(dev, info);
1113 pci_aer_handle_error(dev, info);
1117 #ifdef CONFIG_ACPI_APEI_PCIEAER
1119 #define AER_RECOVER_RING_SIZE 16
1121 struct aer_recover_entry {
1126 struct aer_capability_regs *regs;
1129 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
1130 AER_RECOVER_RING_SIZE);
1132 static void aer_recover_work_func(struct work_struct *work)
1134 struct aer_recover_entry entry;
1135 struct pci_dev *pdev;
1137 while (kfifo_get(&aer_recover_ring, &entry)) {
1138 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
1141 pr_err("no pci_dev for %04x:%02x:%02x.%x\n",
1142 entry.domain, entry.bus,
1143 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
1146 pci_print_aer(pdev, entry.severity, entry.regs);
1148 * Memory for aer_capability_regs(entry.regs) is being allocated from the
1149 * ghes_estatus_pool to protect it from overwriting when multiple sections
1150 * are present in the error status. Thus free the same after processing
1153 ghes_estatus_pool_region_free((unsigned long)entry.regs,
1154 sizeof(struct aer_capability_regs));
1156 if (entry.severity == AER_NONFATAL)
1157 pcie_do_recovery(pdev, pci_channel_io_normal,
1159 else if (entry.severity == AER_FATAL)
1160 pcie_do_recovery(pdev, pci_channel_io_frozen,
1167 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1168 * need lock, because there is only one reader and lock is not needed
1169 * between reader and writer.
1171 static DEFINE_SPINLOCK(aer_recover_ring_lock);
1172 static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
1174 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
1175 int severity, struct aer_capability_regs *aer_regs)
1177 struct aer_recover_entry entry = {
1181 .severity = severity,
1185 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
1186 &aer_recover_ring_lock))
1187 schedule_work(&aer_recover_work);
1189 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n",
1190 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1192 EXPORT_SYMBOL_GPL(aer_recover_queue);
1196 * aer_get_device_error_info - read error status from dev and store it to info
1197 * @dev: pointer to the device expected to have a error record
1198 * @info: pointer to structure to store the error record
1200 * Return 1 on success, 0 on error.
1202 * Note that @info is reused among all error devices. Clear fields properly.
1204 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
1206 int type = pci_pcie_type(dev);
1207 int aer = dev->aer_cap;
1210 /* Must reset in this function */
1212 info->tlp_header_valid = 0;
1214 /* The device might not support AER */
1218 if (info->severity == AER_CORRECTABLE) {
1219 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1221 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
1223 if (!(info->status & ~info->mask))
1225 } else if (type == PCI_EXP_TYPE_ROOT_PORT ||
1226 type == PCI_EXP_TYPE_RC_EC ||
1227 type == PCI_EXP_TYPE_DOWNSTREAM ||
1228 info->severity == AER_NONFATAL) {
1230 /* Link is still healthy for IO reads */
1231 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
1233 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
1235 if (!(info->status & ~info->mask))
1238 /* Get First Error Pointer */
1239 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
1240 info->first_error = PCI_ERR_CAP_FEP(temp);
1242 if (info->status & AER_LOG_TLP_MASKS) {
1243 info->tlp_header_valid = 1;
1244 pci_read_config_dword(dev,
1245 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1246 pci_read_config_dword(dev,
1247 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1248 pci_read_config_dword(dev,
1249 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1250 pci_read_config_dword(dev,
1251 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1258 static inline void aer_process_err_devices(struct aer_err_info *e_info)
1262 /* Report all before handle them, not to lost records by reset etc. */
1263 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1264 if (aer_get_device_error_info(e_info->dev[i], e_info))
1265 aer_print_error(e_info->dev[i], e_info);
1267 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1268 if (aer_get_device_error_info(e_info->dev[i], e_info))
1269 handle_error_source(e_info->dev[i], e_info);
1274 * aer_isr_one_error - consume an error detected by root port
1275 * @rpc: pointer to the root port which holds an error
1276 * @e_src: pointer to an error source
1278 static void aer_isr_one_error(struct aer_rpc *rpc,
1279 struct aer_err_source *e_src)
1281 struct pci_dev *pdev = rpc->rpd;
1282 struct aer_err_info e_info;
1284 pci_rootport_aer_stats_incr(pdev, e_src);
1287 * There is a possibility that both correctable error and
1288 * uncorrectable error being logged. Report correctable error first.
1290 if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
1291 e_info.id = ERR_COR_ID(e_src->id);
1292 e_info.severity = AER_CORRECTABLE;
1294 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
1295 e_info.multi_error_valid = 1;
1297 e_info.multi_error_valid = 0;
1298 aer_print_port_info(pdev, &e_info);
1300 if (find_source_device(pdev, &e_info))
1301 aer_process_err_devices(&e_info);
1304 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
1305 e_info.id = ERR_UNCOR_ID(e_src->id);
1307 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
1308 e_info.severity = AER_FATAL;
1310 e_info.severity = AER_NONFATAL;
1312 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
1313 e_info.multi_error_valid = 1;
1315 e_info.multi_error_valid = 0;
1317 aer_print_port_info(pdev, &e_info);
1319 if (find_source_device(pdev, &e_info))
1320 aer_process_err_devices(&e_info);
1325 * aer_isr - consume errors detected by root port
1326 * @irq: IRQ assigned to Root Port
1327 * @context: pointer to Root Port data structure
1329 * Invoked, as DPC, when root port records new detected error
1331 static irqreturn_t aer_isr(int irq, void *context)
1333 struct pcie_device *dev = (struct pcie_device *)context;
1334 struct aer_rpc *rpc = get_service_data(dev);
1335 struct aer_err_source e_src;
1337 if (kfifo_is_empty(&rpc->aer_fifo))
1340 while (kfifo_get(&rpc->aer_fifo, &e_src))
1341 aer_isr_one_error(rpc, &e_src);
1346 * aer_irq - Root Port's ISR
1347 * @irq: IRQ assigned to Root Port
1348 * @context: pointer to Root Port data structure
1350 * Invoked when Root Port detects AER messages.
1352 static irqreturn_t aer_irq(int irq, void *context)
1354 struct pcie_device *pdev = (struct pcie_device *)context;
1355 struct aer_rpc *rpc = get_service_data(pdev);
1356 struct pci_dev *rp = rpc->rpd;
1357 int aer = rp->aer_cap;
1358 struct aer_err_source e_src = {};
1360 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
1361 if (!(e_src.status & AER_ERR_STATUS_MASK))
1364 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
1365 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
1367 if (!kfifo_put(&rpc->aer_fifo, e_src))
1370 return IRQ_WAKE_THREAD;
1373 static void aer_enable_irq(struct pci_dev *pdev)
1375 int aer = pdev->aer_cap;
1378 /* Enable Root Port's interrupt in response to error messages */
1379 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1380 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1381 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1384 static void aer_disable_irq(struct pci_dev *pdev)
1386 int aer = pdev->aer_cap;
1389 /* Disable Root's interrupt in response to error messages */
1390 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1391 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1392 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1396 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1397 * @rpc: pointer to a Root Port data structure
1399 * Invoked when PCIe bus loads AER service driver.
1401 static void aer_enable_rootport(struct aer_rpc *rpc)
1403 struct pci_dev *pdev = rpc->rpd;
1404 int aer = pdev->aer_cap;
1408 /* Clear PCIe Capability's Device Status */
1409 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
1410 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
1412 /* Disable system error generation in response to error messages */
1413 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1414 SYSTEM_ERROR_INTR_ON_MESG_MASK);
1416 /* Clear error status */
1417 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1418 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1419 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
1420 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
1421 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
1422 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
1424 aer_enable_irq(pdev);
1428 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1429 * @rpc: pointer to a Root Port data structure
1431 * Invoked when PCIe bus unloads AER service driver.
1433 static void aer_disable_rootport(struct aer_rpc *rpc)
1435 struct pci_dev *pdev = rpc->rpd;
1436 int aer = pdev->aer_cap;
1439 aer_disable_irq(pdev);
1441 /* Clear Root's error status reg */
1442 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1443 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1447 * aer_remove - clean up resources
1448 * @dev: pointer to the pcie_dev data structure
1450 * Invoked when PCI Express bus unloads or AER probe fails.
1452 static void aer_remove(struct pcie_device *dev)
1454 struct aer_rpc *rpc = get_service_data(dev);
1456 aer_disable_rootport(rpc);
1460 * aer_probe - initialize resources
1461 * @dev: pointer to the pcie_dev data structure
1463 * Invoked when PCI Express bus loads AER service driver.
1465 static int aer_probe(struct pcie_device *dev)
1468 struct aer_rpc *rpc;
1469 struct device *device = &dev->device;
1470 struct pci_dev *port = dev->port;
1472 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) <
1473 AER_MAX_TYPEOF_COR_ERRS);
1474 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) <
1475 AER_MAX_TYPEOF_UNCOR_ERRS);
1477 /* Limit to Root Ports or Root Complex Event Collectors */
1478 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) &&
1479 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT))
1482 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
1487 INIT_KFIFO(rpc->aer_fifo);
1488 set_service_data(dev, rpc);
1490 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
1491 IRQF_SHARED, "aerdrv", dev);
1493 pci_err(port, "request AER IRQ %d failed\n", dev->irq);
1497 cxl_rch_enable_rcec(port);
1498 aer_enable_rootport(rpc);
1499 pci_info(port, "enabled with IRQ %d\n", dev->irq);
1504 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP
1505 * @dev: pointer to Root Port, RCEC, or RCiEP
1507 * Invoked by Port Bus driver when performing reset.
1509 static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1511 int type = pci_pcie_type(dev);
1512 struct pci_dev *root;
1514 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
1519 * Only Root Ports and RCECs have AER Root Command and Root Status
1520 * registers. If "dev" is an RCiEP, the relevant registers are in
1523 if (type == PCI_EXP_TYPE_RC_END)
1526 root = pcie_find_root_port(dev);
1529 * If the platform retained control of AER, an RCiEP may not have
1530 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In
1531 * that case, firmware is responsible for these registers.
1533 aer = root ? root->aer_cap : 0;
1535 if ((host->native_aer || pcie_ports_native) && aer)
1536 aer_disable_irq(root);
1538 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) {
1539 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET);
1541 pci_info(dev, "has been reset\n");
1543 pci_info(dev, "not reset (no FLR support: %d)\n", rc);
1545 rc = pci_bus_error_reset(dev);
1546 pci_info(dev, "%s Port link has been reset (%d)\n",
1547 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc);
1550 if ((host->native_aer || pcie_ports_native) && aer) {
1551 /* Clear Root Error Status */
1552 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32);
1553 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);
1555 aer_enable_irq(root);
1558 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1561 static struct pcie_port_service_driver aerdriver = {
1563 .port_type = PCIE_ANY_PORT,
1564 .service = PCIE_PORT_SERVICE_AER,
1567 .remove = aer_remove,
1571 * pcie_aer_init - register AER root service driver
1573 * Invoked when AER root service driver is loaded.
1575 int __init pcie_aer_init(void)
1577 if (!pci_aer_available())
1579 return pcie_port_service_register(&aerdriver);