1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
4 #ifndef __MLX5_LIB_ASO_H__
5 #define __MLX5_LIB_ASO_H__
7 #include <linux/mlx5/qp.h>
10 #define MLX5_ASO_WQEBBS \
11 (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_BB))
12 #define MLX5_ASO_WQEBBS_DATA \
13 (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe_data), MLX5_SEND_WQE_BB))
14 #define ASO_CTRL_READ_EN BIT(0)
15 #define MLX5_WQE_CTRL_WQE_OPC_MOD_SHIFT 24
16 #define MLX5_MACSEC_ASO_DS_CNT (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_DS))
18 struct mlx5_wqe_aso_ctrl_seg {
20 __be32 va_l; /* include read_enable */
23 u8 condition_1_0_operand;
24 u8 condition_1_0_offset;
25 u8 data_offset_condition_operand;
26 __be32 condition_0_data;
27 __be32 condition_0_mask;
28 __be32 condition_1_data;
29 __be32 condition_1_mask;
34 struct mlx5_wqe_aso_data_seg {
35 __be32 bytewise_data[16];
39 struct mlx5_wqe_ctrl_seg ctrl;
40 struct mlx5_wqe_aso_ctrl_seg aso_ctrl;
43 struct mlx5_aso_wqe_data {
44 struct mlx5_wqe_ctrl_seg ctrl;
45 struct mlx5_wqe_aso_ctrl_seg aso_ctrl;
46 struct mlx5_wqe_aso_data_seg aso_data;
55 MLX5_ASO_ALWAYS_FALSE,
59 MLX5_ASO_GREATER_OR_EQUAL,
60 MLX5_ASO_LESSER_OR_EQUAL,
63 MLX5_ASO_CYCLIC_GREATER,
64 MLX5_ASO_CYCLIC_LESSER,
68 MLX5_ASO_DATA_MASK_MODE_BITWISE_64BIT,
69 MLX5_ASO_DATA_MASK_MODE_BYTEWISE_64BYTE,
70 MLX5_ASO_DATA_MASK_MODE_CALCULATED_64BYTE,
74 MLX5_ACCESS_ASO_OPC_MOD_FLOW_METER = 0x2,
75 MLX5_ACCESS_ASO_OPC_MOD_MACSEC = 0x5,
80 void *mlx5_aso_get_wqe(struct mlx5_aso *aso);
81 void mlx5_aso_build_wqe(struct mlx5_aso *aso, u8 ds_cnt,
82 struct mlx5_aso_wqe *aso_wqe,
83 u32 obj_id, u32 opc_mode);
84 void mlx5_aso_post_wqe(struct mlx5_aso *aso, bool with_data,
85 struct mlx5_wqe_ctrl_seg *doorbell_cseg);
86 int mlx5_aso_poll_cq(struct mlx5_aso *aso, bool with_data);
88 struct mlx5_aso *mlx5_aso_create(struct mlx5_core_dev *mdev, u32 pdn);
89 void mlx5_aso_destroy(struct mlx5_aso *aso);
90 #endif /* __MLX5_LIB_ASO_H__ */