drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/highmem.h>
  32 #include <linux/nmi.h>
  33 #include <linux/pagevec.h>
  34 #include <linux/scatterlist.h>
  35 #include <linux/string_helpers.h>
  36 #include <linux/utsname.h>
  37 #include <linux/zlib.h>
  38
  39 #include <drm/drm_cache.h>
  40 #include <drm/drm_print.h>
  41
  42 #include "display/intel_dmc.h"
  43 #include "display/intel_overlay.h"
  44
  45 #include "gem/i915_gem_context.h"
  46 #include "gem/i915_gem_lmem.h"
  47 #include "gt/intel_engine_regs.h"
  48 #include "gt/intel_gt.h"
  49 #include "gt/intel_gt_mcr.h"
  50 #include "gt/intel_gt_pm.h"
  51 #include "gt/intel_gt_regs.h"
  52 #include "gt/uc/intel_guc_capture.h"
  53
  54 #include "i915_driver.h"
  55 #include "i915_drv.h"
  56 #include "i915_gpu_error.h"
  57 #include "i915_memcpy.h"
  58 #include "i915_reg.h"
  59 #include "i915_scatterlist.h"
  60 #include "i915_utils.h"
  61
  62 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
  63 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
  64
  65 static void __sg_set_buf(struct scatterlist *sg,
  66                          void *addr, unsigned int len, loff_t it)
  67 {
  68         sg->page_link = (unsigned long)virt_to_page(addr);
  69         sg->offset = offset_in_page(addr);
  70         sg->length = len;
  71         sg->dma_address = it;
  72 }
  73
  74 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  75 {
  76         if (!len)
  77                 return false;
  78
  79         if (e->bytes + len + 1 <= e->size)
  80                 return true;
  81
  82         if (e->bytes) {
  83                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
  84                 e->iter += e->bytes;
  85                 e->buf = NULL;
  86                 e->bytes = 0;
  87         }
  88
  89         if (e->cur == e->end) {
  90                 struct scatterlist *sgl;
  91
  92                 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
  93                 if (!sgl) {
  94                         e->err = -ENOMEM;
  95                         return false;
  96                 }
  97
  98                 if (e->cur) {
  99                         e->cur->offset = 0;
 100                         e->cur->length = 0;
 101                         e->cur->page_link =
 102                                 (unsigned long)sgl | SG_CHAIN;
 103                 } else {
 104                         e->sgl = sgl;
 105                 }
 106
 107                 e->cur = sgl;
 108                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
 109         }
 110
 111         e->size = ALIGN(len + 1, SZ_64K);
 112         e->buf = kmalloc(e->size, ALLOW_FAIL);
 113         if (!e->buf) {
 114                 e->size = PAGE_ALIGN(len + 1);
 115                 e->buf = kmalloc(e->size, GFP_KERNEL);
 116         }
 117         if (!e->buf) {
 118                 e->err = -ENOMEM;
 119                 return false;
 120         }
 121
 122         return true;
 123 }
 124
 125 __printf(2, 0)
 126 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 127                                const char *fmt, va_list args)
 128 {
 129         va_list ap;
 130         int len;
 131
 132         if (e->err)
 133                 return;
 134
 135         va_copy(ap, args);
 136         len = vsnprintf(NULL, 0, fmt, ap);
 137         va_end(ap);
 138         if (len <= 0) {
 139                 e->err = len;
 140                 return;
 141         }
 142
 143         if (!__i915_error_grow(e, len))
 144                 return;
 145
 146         GEM_BUG_ON(e->bytes >= e->size);
 147         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 148         if (len < 0) {
 149                 e->err = len;
 150                 return;
 151         }
 152         e->bytes += len;
 153 }
 154
 155 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 156 {
 157         unsigned len;
 158
 159         if (e->err || !str)
 160                 return;
 161
 162         len = strlen(str);
 163         if (!__i915_error_grow(e, len))
 164                 return;
 165
 166         GEM_BUG_ON(e->bytes + len > e->size);
 167         memcpy(e->buf + e->bytes, str, len);
 168         e->bytes += len;
 169 }
 170
 171 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 172 #define err_puts(e, s) i915_error_puts(e, s)
 173
 174 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 175 {
 176         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 177 }
 178
 179 static inline struct drm_printer
 180 i915_error_printer(struct drm_i915_error_state_buf *e)
 181 {
 182         struct drm_printer p = {
 183                 .printfn = __i915_printfn_error,
 184                 .arg = e,
 185         };
 186         return p;
 187 }
 188
 189 /* single threaded page allocator with a reserved stash for emergencies */
 190 static void pool_fini(struct pagevec *pv)
 191 {
 192         pagevec_release(pv);
 193 }
 194
 195 static int pool_refill(struct pagevec *pv, gfp_t gfp)
 196 {
 197         while (pagevec_space(pv)) {
 198                 struct page *p;
 199
 200                 p = alloc_page(gfp);
 201                 if (!p)
 202                         return -ENOMEM;
 203
 204                 pagevec_add(pv, p);
 205         }
 206
 207         return 0;
 208 }
 209
 210 static int pool_init(struct pagevec *pv, gfp_t gfp)
 211 {
 212         int err;
 213
 214         pagevec_init(pv);
 215
 216         err = pool_refill(pv, gfp);
 217         if (err)
 218                 pool_fini(pv);
 219
 220         return err;
 221 }
 222
 223 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
 224 {
 225         struct page *p;
 226
 227         p = alloc_page(gfp);
 228         if (!p && pagevec_count(pv))
 229                 p = pv->pages[--pv->nr];
 230
 231         return p ? page_address(p) : NULL;
 232 }
 233
 234 static void pool_free(struct pagevec *pv, void *addr)
 235 {
 236         struct page *p = virt_to_page(addr);
 237
 238         if (pagevec_space(pv))
 239                 pagevec_add(pv, p);
 240         else
 241                 __free_page(p);
 242 }
 243
 244 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 245
 246 struct i915_vma_compress {
 247         struct pagevec pool;
 248         struct z_stream_s zstream;
 249         void *tmp;
 250 };
 251
 252 static bool compress_init(struct i915_vma_compress *c)
 253 {
 254         struct z_stream_s *zstream = &c->zstream;
 255
 256         if (pool_init(&c->pool, ALLOW_FAIL))
 257                 return false;
 258
 259         zstream->workspace =
 260                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 261                         ALLOW_FAIL);
 262         if (!zstream->workspace) {
 263                 pool_fini(&c->pool);
 264                 return false;
 265         }
 266
 267         c->tmp = NULL;
 268         if (i915_has_memcpy_from_wc())
 269                 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
 270
 271         return true;
 272 }
 273
 274 static bool compress_start(struct i915_vma_compress *c)
 275 {
 276         struct z_stream_s *zstream = &c->zstream;
 277         void *workspace = zstream->workspace;
 278
 279         memset(zstream, 0, sizeof(*zstream));
 280         zstream->workspace = workspace;
 281
 282         return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
 283 }
 284
 285 static void *compress_next_page(struct i915_vma_compress *c,
 286                                 struct i915_vma_coredump *dst)
 287 {
 288         void *page_addr;
 289         struct page *page;
 290
 291         page_addr = pool_alloc(&c->pool, ALLOW_FAIL);
 292         if (!page_addr)
 293                 return ERR_PTR(-ENOMEM);
 294
 295         page = virt_to_page(page_addr);
 296         list_add_tail(&page->lru, &dst->page_list);
 297         return page_addr;
 298 }
 299
 300 static int compress_page(struct i915_vma_compress *c,
 301                          void *src,
 302                          struct i915_vma_coredump *dst,
 303                          bool wc)
 304 {
 305         struct z_stream_s *zstream = &c->zstream;
 306
 307         zstream->next_in = src;
 308         if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 309                 zstream->next_in = c->tmp;
 310         zstream->avail_in = PAGE_SIZE;
 311
 312         do {
 313                 if (zstream->avail_out == 0) {
 314                         zstream->next_out = compress_next_page(c, dst);
 315                         if (IS_ERR(zstream->next_out))
 316                                 return PTR_ERR(zstream->next_out);
 317
 318                         zstream->avail_out = PAGE_SIZE;
 319                 }
 320
 321                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 322                         return -EIO;
 323
 324                 cond_resched();
 325         } while (zstream->avail_in);
 326
 327         /* Fallback to uncompressed if we increase size? */
 328         if (0 && zstream->total_out > zstream->total_in)
 329                 return -E2BIG;
 330
 331         return 0;
 332 }
 333
 334 static int compress_flush(struct i915_vma_compress *c,
 335                           struct i915_vma_coredump *dst)
 336 {
 337         struct z_stream_s *zstream = &c->zstream;
 338
 339         do {
 340                 switch (zlib_deflate(zstream, Z_FINISH)) {
 341                 case Z_OK: /* more space requested */
 342                         zstream->next_out = compress_next_page(c, dst);
 343                         if (IS_ERR(zstream->next_out))
 344                                 return PTR_ERR(zstream->next_out);
 345
 346                         zstream->avail_out = PAGE_SIZE;
 347                         break;
 348
 349                 case Z_STREAM_END:
 350                         goto end;
 351
 352                 default: /* any error */
 353                         return -EIO;
 354                 }
 355         } while (1);
 356
 357 end:
 358         memset(zstream->next_out, 0, zstream->avail_out);
 359         dst->unused = zstream->avail_out;
 360         return 0;
 361 }
 362
 363 static void compress_finish(struct i915_vma_compress *c)
 364 {
 365         zlib_deflateEnd(&c->zstream);
 366 }
 367
 368 static void compress_fini(struct i915_vma_compress *c)
 369 {
 370         kfree(c->zstream.workspace);
 371         if (c->tmp)
 372                 pool_free(&c->pool, c->tmp);
 373         pool_fini(&c->pool);
 374 }
 375
 376 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 377 {
 378         err_puts(m, ":");
 379 }
 380
 381 #else
 382
 383 struct i915_vma_compress {
 384         struct pagevec pool;
 385 };
 386
 387 static bool compress_init(struct i915_vma_compress *c)
 388 {
 389         return pool_init(&c->pool, ALLOW_FAIL) == 0;
 390 }
 391
 392 static bool compress_start(struct i915_vma_compress *c)
 393 {
 394         return true;
 395 }
 396
 397 static int compress_page(struct i915_vma_compress *c,
 398                          void *src,
 399                          struct i915_vma_coredump *dst,
 400                          bool wc)
 401 {
 402         void *ptr;
 403
 404         ptr = pool_alloc(&c->pool, ALLOW_FAIL);
 405         if (!ptr)
 406                 return -ENOMEM;
 407
 408         if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
 409                 memcpy(ptr, src, PAGE_SIZE);
 410         list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list);
 411         cond_resched();
 412
 413         return 0;
 414 }
 415
 416 static int compress_flush(struct i915_vma_compress *c,
 417                           struct i915_vma_coredump *dst)
 418 {
 419         return 0;
 420 }
 421
 422 static void compress_finish(struct i915_vma_compress *c)
 423 {
 424 }
 425
 426 static void compress_fini(struct i915_vma_compress *c)
 427 {
 428         pool_fini(&c->pool);
 429 }
 430
 431 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 432 {
 433         err_puts(m, "~");
 434 }
 435
 436 #endif
 437
 438 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 439                                  const struct intel_engine_coredump *ee)
 440 {
 441         int slice;
 442         int subslice;
 443         int iter;
 444
 445         err_printf(m, "  INSTDONE: 0x%08x\n",
 446                    ee->instdone.instdone);
 447
 448         if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)
 449                 return;
 450
 451         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 452                    ee->instdone.slice_common);
 453
 454         if (GRAPHICS_VER(m->i915) <= 6)
 455                 return;
 456
 457         for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 458                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 459                            slice, subslice,
 460                            ee->instdone.sampler[slice][subslice]);
 461
 462         for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 463                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 464                            slice, subslice,
 465                            ee->instdone.row[slice][subslice]);
 466
 467         if (GRAPHICS_VER(m->i915) < 12)
 468                 return;
 469
 470         if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {
 471                 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 472                         err_printf(m, "  GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n",
 473                                    slice, subslice,
 474                                    ee->instdone.geom_svg[slice][subslice]);
 475         }
 476
 477         err_printf(m, "  SC_INSTDONE_EXTRA: 0x%08x\n",
 478                    ee->instdone.slice_common_extra[0]);
 479         err_printf(m, "  SC_INSTDONE_EXTRA2: 0x%08x\n",
 480                    ee->instdone.slice_common_extra[1]);
 481 }
 482
 483 static void error_print_request(struct drm_i915_error_state_buf *m,
 484                                 const char *prefix,
 485                                 const struct i915_request_coredump *erq)
 486 {
 487         if (!erq->seqno)
 488                 return;
 489
 490         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
 491                    prefix, erq->pid, erq->context, erq->seqno,
 492                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 493                             &erq->flags) ? "!" : "",
 494                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 495                             &erq->flags) ? "+" : "",
 496                    erq->sched_attr.priority,
 497                    erq->head, erq->tail);
 498 }
 499
 500 static void error_print_context(struct drm_i915_error_state_buf *m,
 501                                 const char *header,
 502                                 const struct i915_gem_context_coredump *ctx)
 503 {
 504         err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
 505                    header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
 506                    ctx->guilty, ctx->active,
 507                    ctx->total_runtime, ctx->avg_runtime);
 508 }
 509
 510 static struct i915_vma_coredump *
 511 __find_vma(struct i915_vma_coredump *vma, const char *name)
 512 {
 513         while (vma) {
 514                 if (strcmp(vma->name, name) == 0)
 515                         return vma;
 516                 vma = vma->next;
 517         }
 518
 519         return NULL;
 520 }
 521
 522 struct i915_vma_coredump *
 523 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee)
 524 {
 525         return __find_vma(ee->vma, "batch");
 526 }
 527
 528 static void error_print_engine(struct drm_i915_error_state_buf *m,
 529                                const struct intel_engine_coredump *ee)
 530 {
 531         struct i915_vma_coredump *batch;
 532         int n;
 533
 534         err_printf(m, "%s command stream:\n", ee->engine->name);
 535         err_printf(m, "  CCID:  0x%08x\n", ee->ccid);
 536         err_printf(m, "  START: 0x%08x\n", ee->start);
 537         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 538         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 539                    ee->tail, ee->rq_post, ee->rq_tail);
 540         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 541         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 542         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 543         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 544                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 545         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 546         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 547         err_printf(m, "  ESR:   0x%08x\n", ee->esr);
 548
 549         error_print_instdone(m, ee);
 550
 551         batch = intel_gpu_error_find_batch(ee);
 552         if (batch) {
 553                 u64 start = batch->gtt_offset;
 554                 u64 end = start + batch->gtt_size;
 555
 556                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 557                            upper_32_bits(start), lower_32_bits(start),
 558                            upper_32_bits(end), lower_32_bits(end));
 559         }
 560         if (GRAPHICS_VER(m->i915) >= 4) {
 561                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 562                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 563                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 564                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 565         }
 566         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 567         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 568                    lower_32_bits(ee->faddr));
 569         if (GRAPHICS_VER(m->i915) >= 6) {
 570                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 571                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 572         }
 573         if (GRAPHICS_VER(m->i915) >= 11) {
 574                 err_printf(m, "  NOPID: 0x%08x\n", ee->nopid);
 575                 err_printf(m, "  EXCC: 0x%08x\n", ee->excc);
 576                 err_printf(m, "  CMD_CCTL: 0x%08x\n", ee->cmd_cctl);
 577                 err_printf(m, "  CSCMDOP: 0x%08x\n", ee->cscmdop);
 578                 err_printf(m, "  CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl);
 579                 err_printf(m, "  DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi);
 580                 err_printf(m, "  DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo);
 581         }
 582         if (HAS_PPGTT(m->i915)) {
 583                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 584
 585                 if (GRAPHICS_VER(m->i915) >= 8) {
 586                         int i;
 587                         for (i = 0; i < 4; i++)
 588                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 589                                            i, ee->vm_info.pdp[i]);
 590                 } else {
 591                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 592                                    ee->vm_info.pp_dir_base);
 593                 }
 594         }
 595
 596         for (n = 0; n < ee->num_ports; n++) {
 597                 err_printf(m, "  ELSP[%d]:", n);
 598                 error_print_request(m, " ", &ee->execlist[n]);
 599         }
 600 }
 601
 602 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 603 {
 604         va_list args;
 605
 606         va_start(args, f);
 607         i915_error_vprintf(e, f, args);
 608         va_end(args);
 609 }
 610
 611 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,
 612                                const struct intel_engine_cs *engine,
 613                                const struct i915_vma_coredump *vma)
 614 {
 615         char out[ASCII85_BUFSZ];
 616         struct page *page;
 617
 618         if (!vma)
 619                 return;
 620
 621         err_printf(m, "%s --- %s = 0x%08x %08x\n",
 622                    engine ? engine->name : "global", vma->name,
 623                    upper_32_bits(vma->gtt_offset),
 624                    lower_32_bits(vma->gtt_offset));
 625
 626         if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
 627                 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
 628
 629         err_compression_marker(m);
 630         list_for_each_entry(page, &vma->page_list, lru) {
 631                 int i, len;
 632                 const u32 *addr = page_address(page);
 633
 634                 len = PAGE_SIZE;
 635                 if (page == list_last_entry(&vma->page_list, typeof(*page), lru))
 636                         len -= vma->unused;
 637                 len = ascii85_encode_len(len);
 638
 639                 for (i = 0; i < len; i++)
 640                         err_puts(m, ascii85_encode(addr[i], out));
 641         }
 642         err_puts(m, "\n");
 643 }
 644
 645 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 646                                    struct i915_gpu_coredump *error)
 647 {
 648         struct drm_printer p = i915_error_printer(m);
 649
 650         intel_device_info_print(&error->device_info, &error->runtime_info, &p);
 651         intel_driver_caps_print(&error->driver_caps, &p);
 652 }
 653
 654 static void err_print_params(struct drm_i915_error_state_buf *m,
 655                              const struct i915_params *params)
 656 {
 657         struct drm_printer p = i915_error_printer(m);
 658
 659         i915_params_dump(params, &p);
 660 }
 661
 662 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 663                             struct drm_i915_private *i915)
 664 {
 665         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 666
 667         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 668         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 669         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 670                    pdev->subsystem_vendor,
 671                    pdev->subsystem_device);
 672 }
 673
 674 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m,
 675                               const char *name,
 676                               const struct intel_ctb_coredump *ctb)
 677 {
 678         if (!ctb->size)
 679                 return;
 680
 681         err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n",
 682                    name, ctb->raw_status, ctb->raw_head, ctb->raw_tail,
 683                    ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size);
 684 }
 685
 686 static void err_print_uc(struct drm_i915_error_state_buf *m,
 687                          const struct intel_uc_coredump *error_uc)
 688 {
 689         struct drm_printer p = i915_error_printer(m);
 690
 691         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 692         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 693         err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp);
 694         intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log);
 695         err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence);
 696         err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0);
 697         err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1);
 698         intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb);
 699 }
 700
 701 static void err_free_sgl(struct scatterlist *sgl)
 702 {
 703         while (sgl) {
 704                 struct scatterlist *sg;
 705
 706                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 707                         kfree(sg_virt(sg));
 708                         if (sg_is_last(sg))
 709                                 break;
 710                 }
 711
 712                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 713                 free_page((unsigned long)sgl);
 714                 sgl = sg;
 715         }
 716 }
 717
 718 static void err_print_gt_info(struct drm_i915_error_state_buf *m,
 719                               struct intel_gt_coredump *gt)
 720 {
 721         struct drm_printer p = i915_error_printer(m);
 722
 723         intel_gt_info_print(&gt->info, &p);
 724         intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
 725 }
 726
 727 static void err_print_gt_display(struct drm_i915_error_state_buf *m,
 728                                  struct intel_gt_coredump *gt)
 729 {
 730         err_printf(m, "IER: 0x%08x\n", gt->ier);
 731         err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 732 }
 733
 734 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m,
 735                                        struct intel_gt_coredump *gt)
 736 {
 737         int i;
 738
 739         err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
 740         err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
 741                    gt->clock_frequency, gt->clock_period_ns);
 742         err_printf(m, "EIR: 0x%08x\n", gt->eir);
 743         err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 744
 745         for (i = 0; i < gt->ngtier; i++)
 746                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
 747 }
 748
 749 static void err_print_gt_global(struct drm_i915_error_state_buf *m,
 750                                 struct intel_gt_coredump *gt)
 751 {
 752         err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
 753
 754         if (IS_GRAPHICS_VER(m->i915, 6, 11)) {
 755                 err_printf(m, "ERROR: 0x%08x\n", gt->error);
 756                 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
 757         }
 758
 759         if (GRAPHICS_VER(m->i915) >= 8)
 760                 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 761                            gt->fault_data1, gt->fault_data0);
 762
 763         if (GRAPHICS_VER(m->i915) == 7)
 764                 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
 765
 766         if (IS_GRAPHICS_VER(m->i915, 8, 11))
 767                 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
 768
 769         if (GRAPHICS_VER(m->i915) == 12)
 770                 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
 771
 772         if (GRAPHICS_VER(m->i915) >= 12) {
 773                 int i;
 774
 775                 for (i = 0; i < I915_MAX_SFC; i++) {
 776                         /*
 777                          * SFC_DONE resides in the VD forcewake domain, so it
 778                          * only exists if the corresponding VCS engine is
 779                          * present.
 780                          */
 781                         if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
 782                             !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
 783                                 continue;
 784
 785                         err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
 786                                    gt->sfc_done[i]);
 787                 }
 788
 789                 err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
 790         }
 791 }
 792
 793 static void err_print_gt_fences(struct drm_i915_error_state_buf *m,
 794                                 struct intel_gt_coredump *gt)
 795 {
 796         int i;
 797
 798         for (i = 0; i < gt->nfence; i++)
 799                 err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
 800 }
 801
 802 static void err_print_gt_engines(struct drm_i915_error_state_buf *m,
 803                                  struct intel_gt_coredump *gt)
 804 {
 805         const struct intel_engine_coredump *ee;
 806
 807         for (ee = gt->engine; ee; ee = ee->next) {
 808                 const struct i915_vma_coredump *vma;
 809
 810                 if (ee->guc_capture_node)
 811                         intel_guc_capture_print_engine_node(m, ee);
 812                 else
 813                         error_print_engine(m, ee);
 814
 815                 err_printf(m, "  hung: %u\n", ee->hung);
 816                 err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 817                 error_print_context(m, "  Active context: ", &ee->context);
 818
 819                 for (vma = ee->vma; vma; vma = vma->next)
 820                         intel_gpu_error_print_vma(m, ee->engine, vma);
 821         }
 822
 823 }
 824
 825 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 826                                struct i915_gpu_coredump *error)
 827 {
 828         const struct intel_engine_coredump *ee;
 829         struct timespec64 ts;
 830
 831         if (*error->error_msg)
 832                 err_printf(m, "%s\n", error->error_msg);
 833         err_printf(m, "Kernel: %s %s\n",
 834                    init_utsname()->release,
 835                    init_utsname()->machine);
 836         err_printf(m, "Driver: %s\n", DRIVER_DATE);
 837         ts = ktime_to_timespec64(error->time);
 838         err_printf(m, "Time: %lld s %ld us\n",
 839                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 840         ts = ktime_to_timespec64(error->boottime);
 841         err_printf(m, "Boottime: %lld s %ld us\n",
 842                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 843         ts = ktime_to_timespec64(error->uptime);
 844         err_printf(m, "Uptime: %lld s %ld us\n",
 845                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 846         err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
 847                    error->capture, jiffies_to_msecs(jiffies - error->capture));
 848
 849         for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
 850                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
 851                            ee->engine->name,
 852                            ee->context.comm,
 853                            ee->context.pid);
 854
 855         err_printf(m, "Reset count: %u\n", error->reset_count);
 856         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 857         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 858         err_printf(m, "Subplatform: 0x%x\n",
 859                    intel_subplatform(&error->runtime_info,
 860                                      error->device_info.platform));
 861         err_print_pciid(m, m->i915);
 862
 863         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 864
 865         intel_dmc_print_error_state(m, m->i915);
 866
 867         err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
 868         err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
 869
 870         if (error->gt) {
 871                 bool print_guc_capture = false;
 872
 873                 if (error->gt->uc && error->gt->uc->guc.is_guc_capture)
 874                         print_guc_capture = true;
 875
 876                 err_print_gt_display(m, error->gt);
 877                 err_print_gt_global_nonguc(m, error->gt);
 878                 err_print_gt_fences(m, error->gt);
 879
 880                 /*
 881                  * GuC dumped global, eng-class and eng-instance registers together
 882                  * as part of engine state dump so we print in err_print_gt_engines
 883                  */
 884                 if (!print_guc_capture)
 885                         err_print_gt_global(m, error->gt);
 886
 887                 err_print_gt_engines(m, error->gt);
 888
 889                 if (error->gt->uc)
 890                         err_print_uc(m, error->gt->uc);
 891
 892                 err_print_gt_info(m, error->gt);
 893         }
 894
 895         if (error->overlay)
 896                 intel_overlay_print_error_state(m, error->overlay);
 897
 898         err_print_capabilities(m, error);
 899         err_print_params(m, &error->params);
 900 }
 901
 902 static int err_print_to_sgl(struct i915_gpu_coredump *error)
 903 {
 904         struct drm_i915_error_state_buf m;
 905
 906         if (IS_ERR(error))
 907                 return PTR_ERR(error);
 908
 909         if (READ_ONCE(error->sgl))
 910                 return 0;
 911
 912         memset(&m, 0, sizeof(m));
 913         m.i915 = error->i915;
 914
 915         __err_print_to_sgl(&m, error);
 916
 917         if (m.buf) {
 918                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 919                 m.bytes = 0;
 920                 m.buf = NULL;
 921         }
 922         if (m.cur) {
 923                 GEM_BUG_ON(m.end < m.cur);
 924                 sg_mark_end(m.cur - 1);
 925         }
 926         GEM_BUG_ON(m.sgl && !m.cur);
 927
 928         if (m.err) {
 929                 err_free_sgl(m.sgl);
 930                 return m.err;
 931         }
 932
 933         if (cmpxchg(&error->sgl, NULL, m.sgl))
 934                 err_free_sgl(m.sgl);
 935
 936         return 0;
 937 }
 938
 939 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
 940                                          char *buf, loff_t off, size_t rem)
 941 {
 942         struct scatterlist *sg;
 943         size_t count;
 944         loff_t pos;
 945         int err;
 946
 947         if (!error || !rem)
 948                 return 0;
 949
 950         err = err_print_to_sgl(error);
 951         if (err)
 952                 return err;
 953
 954         sg = READ_ONCE(error->fit);
 955         if (!sg || off < sg->dma_address)
 956                 sg = error->sgl;
 957         if (!sg)
 958                 return 0;
 959
 960         pos = sg->dma_address;
 961         count = 0;
 962         do {
 963                 size_t len, start;
 964
 965                 if (sg_is_chain(sg)) {
 966                         sg = sg_chain_ptr(sg);
 967                         GEM_BUG_ON(sg_is_chain(sg));
 968                 }
 969
 970                 len = sg->length;
 971                 if (pos + len <= off) {
 972                         pos += len;
 973                         continue;
 974                 }
 975
 976                 start = sg->offset;
 977                 if (pos < off) {
 978                         GEM_BUG_ON(off - pos > len);
 979                         len -= off - pos;
 980                         start += off - pos;
 981                         pos = off;
 982                 }
 983
 984                 len = min(len, rem);
 985                 GEM_BUG_ON(!len || len > sg->length);
 986
 987                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 988
 989                 count += len;
 990                 pos += len;
 991
 992                 buf += len;
 993                 rem -= len;
 994                 if (!rem) {
 995                         WRITE_ONCE(error->fit, sg);
 996                         break;
 997                 }
 998         } while (!sg_is_last(sg++));
 999
1000         return count;
1001 }
1002
1003 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
1004 {
1005         while (vma) {
1006                 struct i915_vma_coredump *next = vma->next;
1007                 struct page *page, *n;
1008
1009                 list_for_each_entry_safe(page, n, &vma->page_list, lru) {
1010                         list_del_init(&page->lru);
1011                         __free_page(page);
1012                 }
1013
1014                 kfree(vma);
1015                 vma = next;
1016         }
1017 }
1018
1019 static void cleanup_params(struct i915_gpu_coredump *error)
1020 {
1021         i915_params_free(&error->params);
1022 }
1023
1024 static void cleanup_uc(struct intel_uc_coredump *uc)
1025 {
1026         kfree(uc->guc_fw.path);
1027         kfree(uc->huc_fw.path);
1028         i915_vma_coredump_free(uc->guc.vma_log);
1029         i915_vma_coredump_free(uc->guc.vma_ctb);
1030
1031         kfree(uc);
1032 }
1033
1034 static void cleanup_gt(struct intel_gt_coredump *gt)
1035 {
1036         while (gt->engine) {
1037                 struct intel_engine_coredump *ee = gt->engine;
1038
1039                 gt->engine = ee->next;
1040
1041                 i915_vma_coredump_free(ee->vma);
1042                 intel_guc_capture_free_node(ee);
1043                 kfree(ee);
1044         }
1045
1046         if (gt->uc)
1047                 cleanup_uc(gt->uc);
1048
1049         kfree(gt);
1050 }
1051
1052 void __i915_gpu_coredump_free(struct kref *error_ref)
1053 {
1054         struct i915_gpu_coredump *error =
1055                 container_of(error_ref, typeof(*error), ref);
1056
1057         while (error->gt) {
1058                 struct intel_gt_coredump *gt = error->gt;
1059
1060                 error->gt = gt->next;
1061                 cleanup_gt(gt);
1062         }
1063
1064         kfree(error->overlay);
1065
1066         cleanup_params(error);
1067
1068         err_free_sgl(error->sgl);
1069         kfree(error);
1070 }
1071
1072 static struct i915_vma_coredump *
1073 i915_vma_coredump_create(const struct intel_gt *gt,
1074                          const struct i915_vma_resource *vma_res,
1075                          struct i915_vma_compress *compress,
1076                          const char *name)
1077
1078 {
1079         struct i915_ggtt *ggtt = gt->ggtt;
1080         const u64 slot = ggtt->error_capture.start;
1081         struct i915_vma_coredump *dst;
1082         struct sgt_iter iter;
1083         int ret;
1084
1085         might_sleep();
1086
1087         if (!vma_res || !vma_res->bi.pages || !compress)
1088                 return NULL;
1089
1090         dst = kmalloc(sizeof(*dst), ALLOW_FAIL);
1091         if (!dst)
1092                 return NULL;
1093
1094         if (!compress_start(compress)) {
1095                 kfree(dst);
1096                 return NULL;
1097         }
1098
1099         INIT_LIST_HEAD(&dst->page_list);
1100         strcpy(dst->name, name);
1101         dst->next = NULL;
1102
1103         dst->gtt_offset = vma_res->start;
1104         dst->gtt_size = vma_res->node_size;
1105         dst->gtt_page_sizes = vma_res->page_sizes_gtt;
1106         dst->unused = 0;
1107
1108         ret = -EINVAL;
1109         if (drm_mm_node_allocated(&ggtt->error_capture)) {
1110                 void __iomem *s;
1111                 dma_addr_t dma;
1112
1113                 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1114                         mutex_lock(&ggtt->error_mutex);
1115                         if (ggtt->vm.raw_insert_page)
1116                                 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
1117                                                          I915_CACHE_NONE, 0);
1118                         else
1119                                 ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1120                                                      I915_CACHE_NONE, 0);
1121                         mb();
1122
1123                         s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1124                         ret = compress_page(compress,
1125                                             (void  __force *)s, dst,
1126                                             true);
1127                         io_mapping_unmap(s);
1128
1129                         mb();
1130                         ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1131                         mutex_unlock(&ggtt->error_mutex);
1132                         if (ret)
1133                                 break;
1134                 }
1135         } else if (vma_res->bi.lmem) {
1136                 struct intel_memory_region *mem = vma_res->mr;
1137                 dma_addr_t dma;
1138
1139                 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1140                         dma_addr_t offset = dma - mem->region.start;
1141                         void __iomem *s;
1142
1143                         if (offset + PAGE_SIZE > mem->io_size) {
1144                                 ret = -EINVAL;
1145                                 break;
1146                         }
1147
1148                         s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE);
1149                         ret = compress_page(compress,
1150                                             (void __force *)s, dst,
1151                                             true);
1152                         io_mapping_unmap(s);
1153                         if (ret)
1154                                 break;
1155                 }
1156         } else {
1157                 struct page *page;
1158
1159                 for_each_sgt_page(page, iter, vma_res->bi.pages) {
1160                         void *s;
1161
1162                         drm_clflush_pages(&page, 1);
1163
1164                         s = kmap(page);
1165                         ret = compress_page(compress, s, dst, false);
1166                         kunmap(page);
1167
1168                         drm_clflush_pages(&page, 1);
1169
1170                         if (ret)
1171                                 break;
1172                 }
1173         }
1174
1175         if (ret || compress_flush(compress, dst)) {
1176                 struct page *page, *n;
1177
1178                 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) {
1179                         list_del_init(&page->lru);
1180                         pool_free(&compress->pool, page_address(page));
1181                 }
1182
1183                 kfree(dst);
1184                 dst = NULL;
1185         }
1186         compress_finish(compress);
1187
1188         return dst;
1189 }
1190
1191 static void gt_record_fences(struct intel_gt_coredump *gt)
1192 {
1193         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1194         struct intel_uncore *uncore = gt->_gt->uncore;
1195         int i;
1196
1197         if (GRAPHICS_VER(uncore->i915) >= 6) {
1198                 for (i = 0; i < ggtt->num_fences; i++)
1199                         gt->fence[i] =
1200                                 intel_uncore_read64(uncore,
1201                                                     FENCE_REG_GEN6_LO(i));
1202         } else if (GRAPHICS_VER(uncore->i915) >= 4) {
1203                 for (i = 0; i < ggtt->num_fences; i++)
1204                         gt->fence[i] =
1205                                 intel_uncore_read64(uncore,
1206                                                     FENCE_REG_965_LO(i));
1207         } else {
1208                 for (i = 0; i < ggtt->num_fences; i++)
1209                         gt->fence[i] =
1210                                 intel_uncore_read(uncore, FENCE_REG(i));
1211         }
1212         gt->nfence = i;
1213 }
1214
1215 static void engine_record_registers(struct intel_engine_coredump *ee)
1216 {
1217         const struct intel_engine_cs *engine = ee->engine;
1218         struct drm_i915_private *i915 = engine->i915;
1219
1220         if (GRAPHICS_VER(i915) >= 6) {
1221                 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1222
1223                 if (GRAPHICS_VER(i915) >= 12)
1224                         ee->fault_reg = intel_uncore_read(engine->uncore,
1225                                                           GEN12_RING_FAULT_REG);
1226                 else if (GRAPHICS_VER(i915) >= 8)
1227                         ee->fault_reg = intel_uncore_read(engine->uncore,
1228                                                           GEN8_RING_FAULT_REG);
1229                 else
1230                         ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1231         }
1232
1233         if (GRAPHICS_VER(i915) >= 4) {
1234                 ee->esr = ENGINE_READ(engine, RING_ESR);
1235                 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1236                 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1237                 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1238                 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1239                 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1240                 ee->ccid = ENGINE_READ(engine, CCID);
1241                 if (GRAPHICS_VER(i915) >= 8) {
1242                         ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1243                         ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1244                 }
1245                 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1246         } else {
1247                 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1248                 ee->ipeir = ENGINE_READ(engine, IPEIR);
1249                 ee->ipehr = ENGINE_READ(engine, IPEHR);
1250         }
1251
1252         if (GRAPHICS_VER(i915) >= 11) {
1253                 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL);
1254                 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP);
1255                 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL);
1256                 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW);
1257                 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD);
1258                 ee->nopid = ENGINE_READ(engine, RING_NOPID);
1259                 ee->excc = ENGINE_READ(engine, RING_EXCC);
1260         }
1261
1262         intel_engine_get_instdone(engine, &ee->instdone);
1263
1264         ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1265         ee->acthd = intel_engine_get_active_head(engine);
1266         ee->start = ENGINE_READ(engine, RING_START);
1267         ee->head = ENGINE_READ(engine, RING_HEAD);
1268         ee->tail = ENGINE_READ(engine, RING_TAIL);
1269         ee->ctl = ENGINE_READ(engine, RING_CTL);
1270         if (GRAPHICS_VER(i915) > 2)
1271                 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1272
1273         if (!HWS_NEEDS_PHYSICAL(i915)) {
1274                 i915_reg_t mmio;
1275
1276                 if (GRAPHICS_VER(i915) == 7) {
1277                         switch (engine->id) {
1278                         default:
1279                                 MISSING_CASE(engine->id);
1280                                 fallthrough;
1281                         case RCS0:
1282                                 mmio = RENDER_HWS_PGA_GEN7;
1283                                 break;
1284                         case BCS0:
1285                                 mmio = BLT_HWS_PGA_GEN7;
1286                                 break;
1287                         case VCS0:
1288                                 mmio = BSD_HWS_PGA_GEN7;
1289                                 break;
1290                         case VECS0:
1291                                 mmio = VEBOX_HWS_PGA_GEN7;
1292                                 break;
1293                         }
1294                 } else if (GRAPHICS_VER(engine->i915) == 6) {
1295                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1296                 } else {
1297                         /* XXX: gen8 returns to sanity */
1298                         mmio = RING_HWS_PGA(engine->mmio_base);
1299                 }
1300
1301                 ee->hws = intel_uncore_read(engine->uncore, mmio);
1302         }
1303
1304         ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1305
1306         if (HAS_PPGTT(i915)) {
1307                 int i;
1308
1309                 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1310
1311                 if (GRAPHICS_VER(i915) == 6) {
1312                         ee->vm_info.pp_dir_base =
1313                                 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1314                 } else if (GRAPHICS_VER(i915) == 7) {
1315                         ee->vm_info.pp_dir_base =
1316                                 ENGINE_READ(engine, RING_PP_DIR_BASE);
1317                 } else if (GRAPHICS_VER(i915) >= 8) {
1318                         u32 base = engine->mmio_base;
1319
1320                         for (i = 0; i < 4; i++) {
1321                                 ee->vm_info.pdp[i] =
1322                                         intel_uncore_read(engine->uncore,
1323                                                           GEN8_RING_PDP_UDW(base, i));
1324                                 ee->vm_info.pdp[i] <<= 32;
1325                                 ee->vm_info.pdp[i] |=
1326                                         intel_uncore_read(engine->uncore,
1327                                                           GEN8_RING_PDP_LDW(base, i));
1328                         }
1329                 }
1330         }
1331 }
1332
1333 static void record_request(const struct i915_request *request,
1334                            struct i915_request_coredump *erq)
1335 {
1336         erq->flags = request->fence.flags;
1337         erq->context = request->fence.context;
1338         erq->seqno = request->fence.seqno;
1339         erq->sched_attr = request->sched.attr;
1340         erq->head = request->head;
1341         erq->tail = request->tail;
1342
1343         erq->pid = 0;
1344         rcu_read_lock();
1345         if (!intel_context_is_closed(request->context)) {
1346                 const struct i915_gem_context *ctx;
1347
1348                 ctx = rcu_dereference(request->context->gem_context);
1349                 if (ctx)
1350                         erq->pid = pid_nr(ctx->pid);
1351         }
1352         rcu_read_unlock();
1353 }
1354
1355 static void engine_record_execlists(struct intel_engine_coredump *ee)
1356 {
1357         const struct intel_engine_execlists * const el = &ee->engine->execlists;
1358         struct i915_request * const *port = el->active;
1359         unsigned int n = 0;
1360
1361         while (*port)
1362                 record_request(*port++, &ee->execlist[n++]);
1363
1364         ee->num_ports = n;
1365 }
1366
1367 static bool record_context(struct i915_gem_context_coredump *e,
1368                            const struct i915_request *rq)
1369 {
1370         struct i915_gem_context *ctx;
1371         struct task_struct *task;
1372         bool simulated;
1373
1374         rcu_read_lock();
1375         ctx = rcu_dereference(rq->context->gem_context);
1376         if (ctx && !kref_get_unless_zero(&ctx->ref))
1377                 ctx = NULL;
1378         rcu_read_unlock();
1379         if (!ctx)
1380                 return true;
1381
1382         rcu_read_lock();
1383         task = pid_task(ctx->pid, PIDTYPE_PID);
1384         if (task) {
1385                 strcpy(e->comm, task->comm);
1386                 e->pid = task->pid;
1387         }
1388         rcu_read_unlock();
1389
1390         e->sched_attr = ctx->sched;
1391         e->guilty = atomic_read(&ctx->guilty_count);
1392         e->active = atomic_read(&ctx->active_count);
1393
1394         e->total_runtime = intel_context_get_total_runtime_ns(rq->context);
1395         e->avg_runtime = intel_context_get_avg_runtime_ns(rq->context);
1396
1397         simulated = i915_gem_context_no_error_capture(ctx);
1398
1399         i915_gem_context_put(ctx);
1400         return simulated;
1401 }
1402
1403 struct intel_engine_capture_vma {
1404         struct intel_engine_capture_vma *next;
1405         struct i915_vma_resource *vma_res;
1406         char name[16];
1407         bool lockdep_cookie;
1408 };
1409
1410 static struct intel_engine_capture_vma *
1411 capture_vma_snapshot(struct intel_engine_capture_vma *next,
1412                      struct i915_vma_resource *vma_res,
1413                      gfp_t gfp, const char *name)
1414 {
1415         struct intel_engine_capture_vma *c;
1416
1417         if (!vma_res)
1418                 return next;
1419
1420         c = kmalloc(sizeof(*c), gfp);
1421         if (!c)
1422                 return next;
1423
1424         if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) {
1425                 kfree(c);
1426                 return next;
1427         }
1428
1429         strcpy(c->name, name);
1430         c->vma_res = i915_vma_resource_get(vma_res);
1431
1432         c->next = next;
1433         return c;
1434 }
1435
1436 static struct intel_engine_capture_vma *
1437 capture_vma(struct intel_engine_capture_vma *next,
1438             struct i915_vma *vma,
1439             const char *name,
1440             gfp_t gfp)
1441 {
1442         if (!vma)
1443                 return next;
1444
1445         /*
1446          * If the vma isn't pinned, then the vma should be snapshotted
1447          * to a struct i915_vma_snapshot at command submission time.
1448          * Not here.
1449          */
1450         if (GEM_WARN_ON(!i915_vma_is_pinned(vma)))
1451                 return next;
1452
1453         next = capture_vma_snapshot(next, vma->resource, gfp, name);
1454
1455         return next;
1456 }
1457
1458 static struct intel_engine_capture_vma *
1459 capture_user(struct intel_engine_capture_vma *capture,
1460              const struct i915_request *rq,
1461              gfp_t gfp)
1462 {
1463         struct i915_capture_list *c;
1464
1465         for (c = rq->capture_list; c; c = c->next)
1466                 capture = capture_vma_snapshot(capture, c->vma_res, gfp,
1467                                                "user");
1468
1469         return capture;
1470 }
1471
1472 static void add_vma(struct intel_engine_coredump *ee,
1473                     struct i915_vma_coredump *vma)
1474 {
1475         if (vma) {
1476                 vma->next = ee->vma;
1477                 ee->vma = vma;
1478         }
1479 }
1480
1481 static struct i915_vma_coredump *
1482 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma,
1483                     const char *name, struct i915_vma_compress *compress)
1484 {
1485         struct i915_vma_coredump *ret = NULL;
1486         struct i915_vma_resource *vma_res;
1487         bool lockdep_cookie;
1488
1489         if (!vma)
1490                 return NULL;
1491
1492         vma_res = vma->resource;
1493
1494         if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) {
1495                 ret = i915_vma_coredump_create(gt, vma_res, compress, name);
1496                 i915_vma_resource_unhold(vma_res, lockdep_cookie);
1497         }
1498
1499         return ret;
1500 }
1501
1502 static void add_vma_coredump(struct intel_engine_coredump *ee,
1503                              const struct intel_gt *gt,
1504                              struct i915_vma *vma,
1505                              const char *name,
1506                              struct i915_vma_compress *compress)
1507 {
1508         add_vma(ee, create_vma_coredump(gt, vma, name, compress));
1509 }
1510
1511 struct intel_engine_coredump *
1512 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
1513 {
1514         struct intel_engine_coredump *ee;
1515
1516         ee = kzalloc(sizeof(*ee), gfp);
1517         if (!ee)
1518                 return NULL;
1519
1520         ee->engine = engine;
1521
1522         if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) {
1523                 engine_record_registers(ee);
1524                 engine_record_execlists(ee);
1525         }
1526
1527         return ee;
1528 }
1529
1530 struct intel_engine_capture_vma *
1531 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1532                                   struct i915_request *rq,
1533                                   gfp_t gfp)
1534 {
1535         struct intel_engine_capture_vma *vma = NULL;
1536
1537         ee->simulated |= record_context(&ee->context, rq);
1538         if (ee->simulated)
1539                 return NULL;
1540
1541         /*
1542          * We need to copy these to an anonymous buffer
1543          * as the simplest method to avoid being overwritten
1544          * by userspace.
1545          */
1546         vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch");
1547         vma = capture_user(vma, rq, gfp);
1548         vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1549         vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1550
1551         ee->rq_head = rq->head;
1552         ee->rq_post = rq->postfix;
1553         ee->rq_tail = rq->tail;
1554
1555         return vma;
1556 }
1557
1558 void
1559 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1560                               struct intel_engine_capture_vma *capture,
1561                               struct i915_vma_compress *compress)
1562 {
1563         const struct intel_engine_cs *engine = ee->engine;
1564
1565         while (capture) {
1566                 struct intel_engine_capture_vma *this = capture;
1567                 struct i915_vma_resource *vma_res = this->vma_res;
1568
1569                 add_vma(ee,
1570                         i915_vma_coredump_create(engine->gt, vma_res,
1571                                                  compress, this->name));
1572
1573                 i915_vma_resource_unhold(vma_res, this->lockdep_cookie);
1574                 i915_vma_resource_put(vma_res);
1575
1576                 capture = this->next;
1577                 kfree(this);
1578         }
1579
1580         add_vma_coredump(ee, engine->gt, engine->status_page.vma,
1581                          "HW Status", compress);
1582
1583         add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma,
1584                          "WA context", compress);
1585 }
1586
1587 static struct intel_engine_coredump *
1588 capture_engine(struct intel_engine_cs *engine,
1589                struct i915_vma_compress *compress,
1590                u32 dump_flags)
1591 {
1592         struct intel_engine_capture_vma *capture = NULL;
1593         struct intel_engine_coredump *ee;
1594         struct intel_context *ce;
1595         struct i915_request *rq = NULL;
1596         unsigned long flags;
1597
1598         ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags);
1599         if (!ee)
1600                 return NULL;
1601
1602         ce = intel_engine_get_hung_context(engine);
1603         if (ce) {
1604                 intel_engine_clear_hung_context(engine);
1605                 rq = intel_context_find_active_request(ce);
1606                 if (!rq || !i915_request_started(rq))
1607                         goto no_request_capture;
1608         } else {
1609                 /*
1610                  * Getting here with GuC enabled means it is a forced error capture
1611                  * with no actual hang. So, no need to attempt the execlist search.
1612                  */
1613                 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
1614                         spin_lock_irqsave(&engine->sched_engine->lock, flags);
1615                         rq = intel_engine_execlist_find_hung_request(engine);
1616                         spin_unlock_irqrestore(&engine->sched_engine->lock,
1617                                                flags);
1618                 }
1619         }
1620         if (rq)
1621                 rq = i915_request_get_rcu(rq);
1622
1623         if (!rq)
1624                 goto no_request_capture;
1625
1626         capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL);
1627         if (!capture) {
1628                 i915_request_put(rq);
1629                 goto no_request_capture;
1630         }
1631         if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1632                 intel_guc_capture_get_matching_node(engine->gt, ee, ce);
1633
1634         intel_engine_coredump_add_vma(ee, capture, compress);
1635         i915_request_put(rq);
1636
1637         return ee;
1638
1639 no_request_capture:
1640         kfree(ee);
1641         return NULL;
1642 }
1643
1644 static void
1645 gt_record_engines(struct intel_gt_coredump *gt,
1646                   intel_engine_mask_t engine_mask,
1647                   struct i915_vma_compress *compress,
1648                   u32 dump_flags)
1649 {
1650         struct intel_engine_cs *engine;
1651         enum intel_engine_id id;
1652
1653         for_each_engine(engine, gt->_gt, id) {
1654                 struct intel_engine_coredump *ee;
1655
1656                 /* Refill our page pool before entering atomic section */
1657                 pool_refill(&compress->pool, ALLOW_FAIL);
1658
1659                 ee = capture_engine(engine, compress, dump_flags);
1660                 if (!ee)
1661                         continue;
1662
1663                 ee->hung = engine->mask & engine_mask;
1664
1665                 gt->simulated |= ee->simulated;
1666                 if (ee->simulated) {
1667                         if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1668                                 intel_guc_capture_free_node(ee);
1669                         kfree(ee);
1670                         continue;
1671                 }
1672
1673                 ee->next = gt->engine;
1674                 gt->engine = ee;
1675         }
1676 }
1677
1678 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved,
1679                               const struct intel_guc_ct_buffer *ctb,
1680                               const void *blob_ptr, struct intel_guc *guc)
1681 {
1682         if (!ctb || !ctb->desc)
1683                 return;
1684
1685         saved->raw_status = ctb->desc->status;
1686         saved->raw_head = ctb->desc->head;
1687         saved->raw_tail = ctb->desc->tail;
1688         saved->head = ctb->head;
1689         saved->tail = ctb->tail;
1690         saved->size = ctb->size;
1691         saved->desc_offset = ((void *)ctb->desc) - blob_ptr;
1692         saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr;
1693 }
1694
1695 static struct intel_uc_coredump *
1696 gt_record_uc(struct intel_gt_coredump *gt,
1697              struct i915_vma_compress *compress)
1698 {
1699         const struct intel_uc *uc = &gt->_gt->uc;
1700         struct intel_uc_coredump *error_uc;
1701
1702         error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1703         if (!error_uc)
1704                 return NULL;
1705
1706         memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1707         memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1708
1709         /* Non-default firmware paths will be specified by the modparam.
1710          * As modparams are generally accesible from the userspace make
1711          * explicit copies of the firmware paths.
1712          */
1713         error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1714         error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1715
1716         /*
1717          * Save the GuC log and include a timestamp reference for converting the
1718          * log times to system times (in conjunction with the error->boottime and
1719          * gt->clock_frequency fields saved elsewhere).
1720          */
1721         error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP);
1722         error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,
1723                                                     "GuC log buffer", compress);
1724         error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma,
1725                                                     "GuC CT buffer", compress);
1726         error_uc->guc.last_fence = uc->guc.ct.requests.last_fence;
1727         gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send,
1728                           uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1729         gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv,
1730                           uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1731
1732         return error_uc;
1733 }
1734
1735 /* Capture display registers. */
1736 static void gt_record_display_regs(struct intel_gt_coredump *gt)
1737 {
1738         struct intel_uncore *uncore = gt->_gt->uncore;
1739         struct drm_i915_private *i915 = uncore->i915;
1740
1741         if (GRAPHICS_VER(i915) >= 6)
1742                 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1743
1744         if (GRAPHICS_VER(i915) >= 8)
1745                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1746         else if (IS_VALLEYVIEW(i915))
1747                 gt->ier = intel_uncore_read(uncore, VLV_IER);
1748         else if (HAS_PCH_SPLIT(i915))
1749                 gt->ier = intel_uncore_read(uncore, DEIER);
1750         else if (GRAPHICS_VER(i915) == 2)
1751                 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1752         else
1753                 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1754 }
1755
1756 /* Capture all other registers that GuC doesn't capture. */
1757 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt)
1758 {
1759         struct intel_uncore *uncore = gt->_gt->uncore;
1760         struct drm_i915_private *i915 = uncore->i915;
1761         int i;
1762
1763         if (IS_VALLEYVIEW(i915)) {
1764                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1765                 gt->ngtier = 1;
1766         } else if (GRAPHICS_VER(i915) >= 11) {
1767                 gt->gtier[0] =
1768                         intel_uncore_read(uncore,
1769                                           GEN11_RENDER_COPY_INTR_ENABLE);
1770                 gt->gtier[1] =
1771                         intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1772                 gt->gtier[2] =
1773                         intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1774                 gt->gtier[3] =
1775                         intel_uncore_read(uncore,
1776                                           GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1777                 gt->gtier[4] =
1778                         intel_uncore_read(uncore,
1779                                           GEN11_CRYPTO_RSVD_INTR_ENABLE);
1780                 gt->gtier[5] =
1781                         intel_uncore_read(uncore,
1782                                           GEN11_GUNIT_CSME_INTR_ENABLE);
1783                 gt->ngtier = 6;
1784         } else if (GRAPHICS_VER(i915) >= 8) {
1785                 for (i = 0; i < 4; i++)
1786                         gt->gtier[i] =
1787                                 intel_uncore_read(uncore, GEN8_GT_IER(i));
1788                 gt->ngtier = 4;
1789         } else if (HAS_PCH_SPLIT(i915)) {
1790                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1791                 gt->ngtier = 1;
1792         }
1793
1794         gt->eir = intel_uncore_read(uncore, EIR);
1795         gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1796 }
1797
1798 /*
1799  * Capture all registers that relate to workload submission.
1800  * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us
1801  */
1802 static void gt_record_global_regs(struct intel_gt_coredump *gt)
1803 {
1804         struct intel_uncore *uncore = gt->_gt->uncore;
1805         struct drm_i915_private *i915 = uncore->i915;
1806         int i;
1807
1808         /*
1809          * General organization
1810          * 1. Registers specific to a single generation
1811          * 2. Registers which belong to multiple generations
1812          * 3. Feature specific registers.
1813          * 4. Everything else
1814          * Please try to follow the order.
1815          */
1816
1817         /* 1: Registers specific to a single generation */
1818         if (IS_VALLEYVIEW(i915))
1819                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1820
1821         if (GRAPHICS_VER(i915) == 7)
1822                 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1823
1824         if (GRAPHICS_VER(i915) >= 12) {
1825                 gt->fault_data0 = intel_uncore_read(uncore,
1826                                                     GEN12_FAULT_TLB_DATA0);
1827                 gt->fault_data1 = intel_uncore_read(uncore,
1828                                                     GEN12_FAULT_TLB_DATA1);
1829         } else if (GRAPHICS_VER(i915) >= 8) {
1830                 gt->fault_data0 = intel_uncore_read(uncore,
1831                                                     GEN8_FAULT_TLB_DATA0);
1832                 gt->fault_data1 = intel_uncore_read(uncore,
1833                                                     GEN8_FAULT_TLB_DATA1);
1834         }
1835
1836         if (GRAPHICS_VER(i915) == 6) {
1837                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1838                 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1839                 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1840         }
1841
1842         /* 2: Registers which belong to multiple generations */
1843         if (GRAPHICS_VER(i915) >= 7)
1844                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1845
1846         if (GRAPHICS_VER(i915) >= 6) {
1847                 if (GRAPHICS_VER(i915) < 12) {
1848                         gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1849                         gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1850                 }
1851         }
1852
1853         /* 3: Feature specific registers */
1854         if (IS_GRAPHICS_VER(i915, 6, 7)) {
1855                 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1856                 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1857         }
1858
1859         if (IS_GRAPHICS_VER(i915, 8, 11))
1860                 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1861
1862         if (GRAPHICS_VER(i915) == 12)
1863                 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1864
1865         if (GRAPHICS_VER(i915) >= 12) {
1866                 for (i = 0; i < I915_MAX_SFC; i++) {
1867                         /*
1868                          * SFC_DONE resides in the VD forcewake domain, so it
1869                          * only exists if the corresponding VCS engine is
1870                          * present.
1871                          */
1872                         if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
1873                             !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
1874                                 continue;
1875
1876                         gt->sfc_done[i] =
1877                                 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1878                 }
1879
1880                 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1881         }
1882 }
1883
1884 static void gt_record_info(struct intel_gt_coredump *gt)
1885 {
1886         memcpy(&gt->info, &gt->_gt->info, sizeof(struct intel_gt_info));
1887         gt->clock_frequency = gt->_gt->clock_frequency;
1888         gt->clock_period_ns = gt->_gt->clock_period_ns;
1889 }
1890
1891 /*
1892  * Generate a semi-unique error code. The code is not meant to have meaning, The
1893  * code's only purpose is to try to prevent false duplicated bug reports by
1894  * grossly estimating a GPU error state.
1895  *
1896  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1897  * the hang if we could strip the GTT offset information from it.
1898  *
1899  * It's only a small step better than a random number in its current form.
1900  */
1901 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1902 {
1903         /*
1904          * IPEHR would be an ideal way to detect errors, as it's the gross
1905          * measure of "the command that hung." However, has some very common
1906          * synchronization commands which almost always appear in the case
1907          * strictly a client bug. Use instdone to differentiate those some.
1908          */
1909         return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1910 }
1911
1912 static const char *error_msg(struct i915_gpu_coredump *error)
1913 {
1914         struct intel_engine_coredump *first = NULL;
1915         unsigned int hung_classes = 0;
1916         struct intel_gt_coredump *gt;
1917         int len;
1918
1919         for (gt = error->gt; gt; gt = gt->next) {
1920                 struct intel_engine_coredump *cs;
1921
1922                 for (cs = gt->engine; cs; cs = cs->next) {
1923                         if (cs->hung) {
1924                                 hung_classes |= BIT(cs->engine->uabi_class);
1925                                 if (!first)
1926                                         first = cs;
1927                         }
1928                 }
1929         }
1930
1931         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1932                         "GPU HANG: ecode %d:%x:%08x",
1933                         GRAPHICS_VER(error->i915), hung_classes,
1934                         generate_ecode(first));
1935         if (first && first->context.pid) {
1936                 /* Just show the first executing process, more is confusing */
1937                 len += scnprintf(error->error_msg + len,
1938                                  sizeof(error->error_msg) - len,
1939                                  ", in %s [%d]",
1940                                  first->context.comm, first->context.pid);
1941         }
1942
1943         return error->error_msg;
1944 }
1945
1946 static void capture_gen(struct i915_gpu_coredump *error)
1947 {
1948         struct drm_i915_private *i915 = error->i915;
1949
1950         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1951         error->suspended = i915->runtime_pm.suspended;
1952
1953         error->iommu = i915_vtd_active(i915);
1954         error->reset_count = i915_reset_count(&i915->gpu_error);
1955         error->suspend_count = i915->suspend_count;
1956
1957         i915_params_copy(&error->params, &i915->params);
1958         memcpy(&error->device_info,
1959                INTEL_INFO(i915),
1960                sizeof(error->device_info));
1961         memcpy(&error->runtime_info,
1962                RUNTIME_INFO(i915),
1963                sizeof(error->runtime_info));
1964         error->driver_caps = i915->caps;
1965 }
1966
1967 struct i915_gpu_coredump *
1968 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1969 {
1970         struct i915_gpu_coredump *error;
1971
1972         if (!i915->params.error_capture)
1973                 return NULL;
1974
1975         error = kzalloc(sizeof(*error), gfp);
1976         if (!error)
1977                 return NULL;
1978
1979         kref_init(&error->ref);
1980         error->i915 = i915;
1981
1982         error->time = ktime_get_real();
1983         error->boottime = ktime_get_boottime();
1984         error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time);
1985         error->capture = jiffies;
1986
1987         capture_gen(error);
1988
1989         return error;
1990 }
1991
1992 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1993
1994 struct intel_gt_coredump *
1995 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
1996 {
1997         struct intel_gt_coredump *gc;
1998
1999         gc = kzalloc(sizeof(*gc), gfp);
2000         if (!gc)
2001                 return NULL;
2002
2003         gc->_gt = gt;
2004         gc->awake = intel_gt_pm_is_awake(gt);
2005
2006         gt_record_display_regs(gc);
2007         gt_record_global_nonguc_regs(gc);
2008
2009         /*
2010          * GuC dumps global, eng-class and eng-instance registers
2011          * (that can change as part of engine state during execution)
2012          * before an engine is reset due to a hung context.
2013          * GuC captures and reports all three groups of registers
2014          * together as a single set before the engine is reset.
2015          * Thus, if GuC triggered the context reset we retrieve
2016          * the register values as part of gt_record_engines.
2017          */
2018         if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE))
2019                 gt_record_global_regs(gc);
2020
2021         gt_record_fences(gc);
2022
2023         return gc;
2024 }
2025
2026 struct i915_vma_compress *
2027 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
2028 {
2029         struct i915_vma_compress *compress;
2030
2031         compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
2032         if (!compress)
2033                 return NULL;
2034
2035         if (!compress_init(compress)) {
2036                 kfree(compress);
2037                 return NULL;
2038         }
2039
2040         return compress;
2041 }
2042
2043 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
2044                              struct i915_vma_compress *compress)
2045 {
2046         if (!compress)
2047                 return;
2048
2049         compress_fini(compress);
2050         kfree(compress);
2051 }
2052
2053 static struct i915_gpu_coredump *
2054 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2055 {
2056         struct drm_i915_private *i915 = gt->i915;
2057         struct i915_gpu_coredump *error;
2058
2059         /* Check if GPU capture has been disabled */
2060         error = READ_ONCE(i915->gpu_error.first_error);
2061         if (IS_ERR(error))
2062                 return error;
2063
2064         error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
2065         if (!error)
2066                 return ERR_PTR(-ENOMEM);
2067
2068         error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags);
2069         if (error->gt) {
2070                 struct i915_vma_compress *compress;
2071
2072                 compress = i915_vma_capture_prepare(error->gt);
2073                 if (!compress) {
2074                         kfree(error->gt);
2075                         kfree(error);
2076                         return ERR_PTR(-ENOMEM);
2077                 }
2078
2079                 if (INTEL_INFO(i915)->has_gt_uc) {
2080                         error->gt->uc = gt_record_uc(error->gt, compress);
2081                         if (error->gt->uc) {
2082                                 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
2083                                         error->gt->uc->guc.is_guc_capture = true;
2084                                 else
2085                                         GEM_BUG_ON(error->gt->uc->guc.is_guc_capture);
2086                         }
2087                 }
2088
2089                 gt_record_info(error->gt);
2090                 gt_record_engines(error->gt, engine_mask, compress, dump_flags);
2091
2092
2093                 i915_vma_capture_finish(error->gt, compress);
2094
2095                 error->simulated |= error->gt->simulated;
2096         }
2097
2098         error->overlay = intel_overlay_capture_error_state(i915);
2099
2100         return error;
2101 }
2102
2103 struct i915_gpu_coredump *
2104 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2105 {
2106         static DEFINE_MUTEX(capture_mutex);
2107         int ret = mutex_lock_interruptible(&capture_mutex);
2108         struct i915_gpu_coredump *dump;
2109
2110         if (ret)
2111                 return ERR_PTR(ret);
2112
2113         dump = __i915_gpu_coredump(gt, engine_mask, dump_flags);
2114         mutex_unlock(&capture_mutex);
2115
2116         return dump;
2117 }
2118
2119 void i915_error_state_store(struct i915_gpu_coredump *error)
2120 {
2121         struct drm_i915_private *i915;
2122         static bool warned;
2123
2124         if (IS_ERR_OR_NULL(error))
2125                 return;
2126
2127         i915 = error->i915;
2128         drm_info(&i915->drm, "%s\n", error_msg(error));
2129
2130         if (error->simulated ||
2131             cmpxchg(&i915->gpu_error.first_error, NULL, error))
2132                 return;
2133
2134         i915_gpu_coredump_get(error);
2135
2136         if (!xchg(&warned, true) &&
2137             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
2138                 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
2139                 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
2140                 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
2141                 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
2142                 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
2143                 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
2144                         i915->drm.primary->index);
2145         }
2146 }
2147
2148 /**
2149  * i915_capture_error_state - capture an error record for later analysis
2150  * @gt: intel_gt which originated the hang
2151  * @engine_mask: hung engines
2152  *
2153  *
2154  * Should be called when an error is detected (either a hang or an error
2155  * interrupt) to capture error state from the time of the error.  Fills
2156  * out a structure which becomes available in debugfs for user level tools
2157  * to pick up.
2158  */
2159 void i915_capture_error_state(struct intel_gt *gt,
2160                               intel_engine_mask_t engine_mask, u32 dump_flags)
2161 {
2162         struct i915_gpu_coredump *error;
2163
2164         error = i915_gpu_coredump(gt, engine_mask, dump_flags);
2165         if (IS_ERR(error)) {
2166                 cmpxchg(&gt->i915->gpu_error.first_error, NULL, error);
2167                 return;
2168         }
2169
2170         i915_error_state_store(error);
2171         i915_gpu_coredump_put(error);
2172 }
2173
2174 struct i915_gpu_coredump *
2175 i915_first_error_state(struct drm_i915_private *i915)
2176 {
2177         struct i915_gpu_coredump *error;
2178
2179         spin_lock_irq(&i915->gpu_error.lock);
2180         error = i915->gpu_error.first_error;
2181         if (!IS_ERR_OR_NULL(error))
2182                 i915_gpu_coredump_get(error);
2183         spin_unlock_irq(&i915->gpu_error.lock);
2184
2185         return error;
2186 }
2187
2188 void i915_reset_error_state(struct drm_i915_private *i915)
2189 {
2190         struct i915_gpu_coredump *error;
2191
2192         spin_lock_irq(&i915->gpu_error.lock);
2193         error = i915->gpu_error.first_error;
2194         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
2195                 i915->gpu_error.first_error = NULL;
2196         spin_unlock_irq(&i915->gpu_error.lock);
2197
2198         if (!IS_ERR_OR_NULL(error))
2199                 i915_gpu_coredump_put(error);
2200 }
2201
2202 void i915_disable_error_state(struct drm_i915_private *i915, int err)
2203 {
2204         spin_lock_irq(&i915->gpu_error.lock);
2205         if (!i915->gpu_error.first_error)
2206                 i915->gpu_error.first_error = ERR_PTR(err);
2207         spin_unlock_irq(&i915->gpu_error.lock);
2208 }