drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn30_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn20/dcn20_resource.h"
  35
  36 #include "dcn30_resource.h"
  37
  38 #include "dcn10/dcn10_ipp.h"
  39 #include "dcn30/dcn30_hubbub.h"
  40 #include "dcn30/dcn30_mpc.h"
  41 #include "dcn30/dcn30_hubp.h"
  42 #include "irq/dcn30/irq_service_dcn30.h"
  43 #include "dcn30/dcn30_dpp.h"
  44 #include "dcn30/dcn30_optc.h"
  45 #include "dcn20/dcn20_hwseq.h"
  46 #include "dcn30/dcn30_hwseq.h"
  47 #include "dce110/dce110_hw_sequencer.h"
  48 #include "dcn30/dcn30_opp.h"
  49 #include "dcn20/dcn20_dsc.h"
  50 #include "dcn30/dcn30_vpg.h"
  51 #include "dcn30/dcn30_afmt.h"
  52 #include "dcn30/dcn30_dio_stream_encoder.h"
  53 #include "dcn30/dcn30_dio_link_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "clk_mgr.h"
  58 #include "virtual/virtual_stream_encoder.h"
  59 #include "dce110/dce110_resource.h"
  60 #include "dml/display_mode_vba.h"
  61 #include "dcn30/dcn30_dccg.h"
  62 #include "dcn10/dcn10_resource.h"
  63 #include "dc_link_ddc.h"
  64 #include "dce/dce_panel_cntl.h"
  65
  66 #include "dcn30/dcn30_dwb.h"
  67 #include "dcn30/dcn30_mmhubbub.h"
  68
  69 #include "sienna_cichlid_ip_offset.h"
  70 #include "dcn/dcn_3_0_0_offset.h"
  71 #include "dcn/dcn_3_0_0_sh_mask.h"
  72
  73 #include "nbio/nbio_7_4_offset.h"
  74
  75 #include "dpcs/dpcs_3_0_0_offset.h"
  76 #include "dpcs/dpcs_3_0_0_sh_mask.h"
  77
  78 #include "mmhub/mmhub_2_0_0_offset.h"
  79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  80
  81 #include "reg_helper.h"
  82 #include "dce/dmub_abm.h"
  83 #include "dce/dmub_psr.h"
  84 #include "dce/dce_aux.h"
  85 #include "dce/dce_i2c.h"
  86
  87 #include "dml/dcn30/dcn30_fpu.h"
  88 #include "dml/dcn30/display_mode_vba_30.h"
  89 #include "vm_helper.h"
  90 #include "dcn20/dcn20_vmid.h"
  91 #include "amdgpu_socbb.h"
  92 #include "dc_dmub_srv.h"
  93
  94 #define DC_LOGGER_INIT(logger)
  95
  96 enum dcn30_clk_src_array_id {
  97         DCN30_CLK_SRC_PLL0,
  98         DCN30_CLK_SRC_PLL1,
  99         DCN30_CLK_SRC_PLL2,
 100         DCN30_CLK_SRC_PLL3,
 101         DCN30_CLK_SRC_PLL4,
 102         DCN30_CLK_SRC_PLL5,
 103         DCN30_CLK_SRC_TOTAL
 104 };
 105
 106 /* begin *********************
 107  * macros to expend register list macro defined in HW object header file
 108  */
 109
 110 /* DCN */
 111 /* TODO awful hack. fixup dcn20_dwb.h */
 112 #undef BASE_INNER
 113 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 114
 115 #define BASE(seg) BASE_INNER(seg)
 116
 117 #define SR(reg_name)\
 118                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 119                                         mm ## reg_name
 120
 121 #define SRI(reg_name, block, id)\
 122         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 123                                         mm ## block ## id ## _ ## reg_name
 124
 125 #define SRI2(reg_name, block, id)\
 126         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
 127                                         mm ## reg_name
 128
 129 #define SRIR(var_name, reg_name, block, id)\
 130         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 131                                         mm ## block ## id ## _ ## reg_name
 132
 133 #define SRII(reg_name, block, id)\
 134         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 135                                         mm ## block ## id ## _ ## reg_name
 136
 137 #define SRII_MPC_RMU(reg_name, block, id)\
 138         .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 139                                         mm ## block ## id ## _ ## reg_name
 140
 141 #define SRII_DWB(reg_name, temp_name, block, id)\
 142         .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 143                                         mm ## block ## id ## _ ## temp_name
 144
 145 #define DCCG_SRII(reg_name, block, id)\
 146         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 147                                         mm ## block ## id ## _ ## reg_name
 148
 149 #define VUPDATE_SRII(reg_name, block, id)\
 150         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 151                                         mm ## reg_name ## _ ## block ## id
 152
 153 /* NBIO */
 154 #define NBIO_BASE_INNER(seg) \
 155         NBIO_BASE__INST0_SEG ## seg
 156
 157 #define NBIO_BASE(seg) \
 158         NBIO_BASE_INNER(seg)
 159
 160 #define NBIO_SR(reg_name)\
 161                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 162                                         mm ## reg_name
 163
 164 /* MMHUB */
 165 #define MMHUB_BASE_INNER(seg) \
 166         MMHUB_BASE__INST0_SEG ## seg
 167
 168 #define MMHUB_BASE(seg) \
 169         MMHUB_BASE_INNER(seg)
 170
 171 #define MMHUB_SR(reg_name)\
 172                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 173                                         mmMM ## reg_name
 174
 175 /* CLOCK */
 176 #define CLK_BASE_INNER(seg) \
 177         CLK_BASE__INST0_SEG ## seg
 178
 179 #define CLK_BASE(seg) \
 180         CLK_BASE_INNER(seg)
 181
 182 #define CLK_SRI(reg_name, block, inst)\
 183         .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 184                                         mm ## block ## _ ## inst ## _ ## reg_name
 185
 186
 187 static const struct bios_registers bios_regs = {
 188                 NBIO_SR(BIOS_SCRATCH_3),
 189                 NBIO_SR(BIOS_SCRATCH_6)
 190 };
 191
 192 #define clk_src_regs(index, pllid)\
 193 [index] = {\
 194         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 195 }
 196
 197 static const struct dce110_clk_src_regs clk_src_regs[] = {
 198         clk_src_regs(0, A),
 199         clk_src_regs(1, B),
 200         clk_src_regs(2, C),
 201         clk_src_regs(3, D),
 202         clk_src_regs(4, E),
 203         clk_src_regs(5, F)
 204 };
 205
 206 static const struct dce110_clk_src_shift cs_shift = {
 207                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 208 };
 209
 210 static const struct dce110_clk_src_mask cs_mask = {
 211                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 212 };
 213
 214 #define abm_regs(id)\
 215 [id] = {\
 216                 ABM_DCN30_REG_LIST(id)\
 217 }
 218
 219 static const struct dce_abm_registers abm_regs[] = {
 220                 abm_regs(0),
 221                 abm_regs(1),
 222                 abm_regs(2),
 223                 abm_regs(3),
 224                 abm_regs(4),
 225                 abm_regs(5),
 226 };
 227
 228 static const struct dce_abm_shift abm_shift = {
 229                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 230 };
 231
 232 static const struct dce_abm_mask abm_mask = {
 233                 ABM_MASK_SH_LIST_DCN30(_MASK)
 234 };
 235
 236
 237
 238 #define audio_regs(id)\
 239 [id] = {\
 240                 AUD_COMMON_REG_LIST(id)\
 241 }
 242
 243 static const struct dce_audio_registers audio_regs[] = {
 244         audio_regs(0),
 245         audio_regs(1),
 246         audio_regs(2),
 247         audio_regs(3),
 248         audio_regs(4),
 249         audio_regs(5),
 250         audio_regs(6)
 251 };
 252
 253 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 254                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 255                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 256                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 257
 258 static const struct dce_audio_shift audio_shift = {
 259                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 260 };
 261
 262 static const struct dce_audio_mask audio_mask = {
 263                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 264 };
 265
 266 #define vpg_regs(id)\
 267 [id] = {\
 268         VPG_DCN3_REG_LIST(id)\
 269 }
 270
 271 static const struct dcn30_vpg_registers vpg_regs[] = {
 272         vpg_regs(0),
 273         vpg_regs(1),
 274         vpg_regs(2),
 275         vpg_regs(3),
 276         vpg_regs(4),
 277         vpg_regs(5),
 278         vpg_regs(6),
 279 };
 280
 281 static const struct dcn30_vpg_shift vpg_shift = {
 282         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 283 };
 284
 285 static const struct dcn30_vpg_mask vpg_mask = {
 286         DCN3_VPG_MASK_SH_LIST(_MASK)
 287 };
 288
 289 #define afmt_regs(id)\
 290 [id] = {\
 291         AFMT_DCN3_REG_LIST(id)\
 292 }
 293
 294 static const struct dcn30_afmt_registers afmt_regs[] = {
 295         afmt_regs(0),
 296         afmt_regs(1),
 297         afmt_regs(2),
 298         afmt_regs(3),
 299         afmt_regs(4),
 300         afmt_regs(5),
 301         afmt_regs(6),
 302 };
 303
 304 static const struct dcn30_afmt_shift afmt_shift = {
 305         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 306 };
 307
 308 static const struct dcn30_afmt_mask afmt_mask = {
 309         DCN3_AFMT_MASK_SH_LIST(_MASK)
 310 };
 311
 312 #define stream_enc_regs(id)\
 313 [id] = {\
 314         SE_DCN3_REG_LIST(id)\
 315 }
 316
 317 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 318         stream_enc_regs(0),
 319         stream_enc_regs(1),
 320         stream_enc_regs(2),
 321         stream_enc_regs(3),
 322         stream_enc_regs(4),
 323         stream_enc_regs(5)
 324 };
 325
 326 static const struct dcn10_stream_encoder_shift se_shift = {
 327                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 328 };
 329
 330 static const struct dcn10_stream_encoder_mask se_mask = {
 331                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 332 };
 333
 334
 335 #define aux_regs(id)\
 336 [id] = {\
 337         DCN2_AUX_REG_LIST(id)\
 338 }
 339
 340 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 341                 aux_regs(0),
 342                 aux_regs(1),
 343                 aux_regs(2),
 344                 aux_regs(3),
 345                 aux_regs(4),
 346                 aux_regs(5)
 347 };
 348
 349 #define hpd_regs(id)\
 350 [id] = {\
 351         HPD_REG_LIST(id)\
 352 }
 353
 354 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 355                 hpd_regs(0),
 356                 hpd_regs(1),
 357                 hpd_regs(2),
 358                 hpd_regs(3),
 359                 hpd_regs(4),
 360                 hpd_regs(5)
 361 };
 362
 363 #define link_regs(id, phyid)\
 364 [id] = {\
 365         LE_DCN3_REG_LIST(id), \
 366         UNIPHY_DCN2_REG_LIST(phyid), \
 367         DPCS_DCN2_REG_LIST(id), \
 368         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 369 }
 370
 371 static const struct dce110_aux_registers_shift aux_shift = {
 372         DCN_AUX_MASK_SH_LIST(__SHIFT)
 373 };
 374
 375 static const struct dce110_aux_registers_mask aux_mask = {
 376         DCN_AUX_MASK_SH_LIST(_MASK)
 377 };
 378
 379 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 380         link_regs(0, A),
 381         link_regs(1, B),
 382         link_regs(2, C),
 383         link_regs(3, D),
 384         link_regs(4, E),
 385         link_regs(5, F)
 386 };
 387
 388 static const struct dcn10_link_enc_shift le_shift = {
 389         LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
 390         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 391 };
 392
 393 static const struct dcn10_link_enc_mask le_mask = {
 394         LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
 395         DPCS_DCN2_MASK_SH_LIST(_MASK)
 396 };
 397
 398
 399 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 400         { DCN_PANEL_CNTL_REG_LIST() }
 401 };
 402
 403 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 404         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 405 };
 406
 407 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 408         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 409 };
 410
 411 #define dpp_regs(id)\
 412 [id] = {\
 413         DPP_REG_LIST_DCN30(id),\
 414 }
 415
 416 static const struct dcn3_dpp_registers dpp_regs[] = {
 417         dpp_regs(0),
 418         dpp_regs(1),
 419         dpp_regs(2),
 420         dpp_regs(3),
 421         dpp_regs(4),
 422         dpp_regs(5),
 423 };
 424
 425 static const struct dcn3_dpp_shift tf_shift = {
 426                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 427 };
 428
 429 static const struct dcn3_dpp_mask tf_mask = {
 430                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 431 };
 432
 433 #define opp_regs(id)\
 434 [id] = {\
 435         OPP_REG_LIST_DCN30(id),\
 436 }
 437
 438 static const struct dcn20_opp_registers opp_regs[] = {
 439         opp_regs(0),
 440         opp_regs(1),
 441         opp_regs(2),
 442         opp_regs(3),
 443         opp_regs(4),
 444         opp_regs(5)
 445 };
 446
 447 static const struct dcn20_opp_shift opp_shift = {
 448         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 449 };
 450
 451 static const struct dcn20_opp_mask opp_mask = {
 452         OPP_MASK_SH_LIST_DCN20(_MASK)
 453 };
 454
 455 #define aux_engine_regs(id)\
 456 [id] = {\
 457         AUX_COMMON_REG_LIST0(id), \
 458         .AUXN_IMPCAL = 0, \
 459         .AUXP_IMPCAL = 0, \
 460         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 461 }
 462
 463 static const struct dce110_aux_registers aux_engine_regs[] = {
 464                 aux_engine_regs(0),
 465                 aux_engine_regs(1),
 466                 aux_engine_regs(2),
 467                 aux_engine_regs(3),
 468                 aux_engine_regs(4),
 469                 aux_engine_regs(5)
 470 };
 471
 472 #define dwbc_regs_dcn3(id)\
 473 [id] = {\
 474         DWBC_COMMON_REG_LIST_DCN30(id),\
 475 }
 476
 477 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 478         dwbc_regs_dcn3(0),
 479 };
 480
 481 static const struct dcn30_dwbc_shift dwbc30_shift = {
 482         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 483 };
 484
 485 static const struct dcn30_dwbc_mask dwbc30_mask = {
 486         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 487 };
 488
 489 #define mcif_wb_regs_dcn3(id)\
 490 [id] = {\
 491         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 492 }
 493
 494 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 495         mcif_wb_regs_dcn3(0)
 496 };
 497
 498 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 499         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 500 };
 501
 502 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 503         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 504 };
 505
 506 #define dsc_regsDCN20(id)\
 507 [id] = {\
 508         DSC_REG_LIST_DCN20(id)\
 509 }
 510
 511 static const struct dcn20_dsc_registers dsc_regs[] = {
 512         dsc_regsDCN20(0),
 513         dsc_regsDCN20(1),
 514         dsc_regsDCN20(2),
 515         dsc_regsDCN20(3),
 516         dsc_regsDCN20(4),
 517         dsc_regsDCN20(5)
 518 };
 519
 520 static const struct dcn20_dsc_shift dsc_shift = {
 521         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 522 };
 523
 524 static const struct dcn20_dsc_mask dsc_mask = {
 525         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 526 };
 527
 528 static const struct dcn30_mpc_registers mpc_regs = {
 529                 MPC_REG_LIST_DCN3_0(0),
 530                 MPC_REG_LIST_DCN3_0(1),
 531                 MPC_REG_LIST_DCN3_0(2),
 532                 MPC_REG_LIST_DCN3_0(3),
 533                 MPC_REG_LIST_DCN3_0(4),
 534                 MPC_REG_LIST_DCN3_0(5),
 535                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 536                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 537                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 538                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 539                 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
 540                 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
 541                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 542                 MPC_RMU_REG_LIST_DCN3AG(0),
 543                 MPC_RMU_REG_LIST_DCN3AG(1),
 544                 MPC_RMU_REG_LIST_DCN3AG(2),
 545                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 546 };
 547
 548 static const struct dcn30_mpc_shift mpc_shift = {
 549         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 550 };
 551
 552 static const struct dcn30_mpc_mask mpc_mask = {
 553         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 554 };
 555
 556 #define optc_regs(id)\
 557 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
 558
 559
 560 static const struct dcn_optc_registers optc_regs[] = {
 561         optc_regs(0),
 562         optc_regs(1),
 563         optc_regs(2),
 564         optc_regs(3),
 565         optc_regs(4),
 566         optc_regs(5)
 567 };
 568
 569 static const struct dcn_optc_shift optc_shift = {
 570         OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 571 };
 572
 573 static const struct dcn_optc_mask optc_mask = {
 574         OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 575 };
 576
 577 #define hubp_regs(id)\
 578 [id] = {\
 579         HUBP_REG_LIST_DCN30(id)\
 580 }
 581
 582 static const struct dcn_hubp2_registers hubp_regs[] = {
 583                 hubp_regs(0),
 584                 hubp_regs(1),
 585                 hubp_regs(2),
 586                 hubp_regs(3),
 587                 hubp_regs(4),
 588                 hubp_regs(5)
 589 };
 590
 591 static const struct dcn_hubp2_shift hubp_shift = {
 592                 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 593 };
 594
 595 static const struct dcn_hubp2_mask hubp_mask = {
 596                 HUBP_MASK_SH_LIST_DCN30(_MASK)
 597 };
 598
 599 static const struct dcn_hubbub_registers hubbub_reg = {
 600                 HUBBUB_REG_LIST_DCN30(0)
 601 };
 602
 603 static const struct dcn_hubbub_shift hubbub_shift = {
 604                 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
 605 };
 606
 607 static const struct dcn_hubbub_mask hubbub_mask = {
 608                 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
 609 };
 610
 611 static const struct dccg_registers dccg_regs = {
 612                 DCCG_REG_LIST_DCN30()
 613 };
 614
 615 static const struct dccg_shift dccg_shift = {
 616                 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
 617 };
 618
 619 static const struct dccg_mask dccg_mask = {
 620                 DCCG_MASK_SH_LIST_DCN3(_MASK)
 621 };
 622
 623 static const struct dce_hwseq_registers hwseq_reg = {
 624                 HWSEQ_DCN30_REG_LIST()
 625 };
 626
 627 static const struct dce_hwseq_shift hwseq_shift = {
 628                 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
 629 };
 630
 631 static const struct dce_hwseq_mask hwseq_mask = {
 632                 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
 633 };
 634 #define vmid_regs(id)\
 635 [id] = {\
 636                 DCN20_VMID_REG_LIST(id)\
 637 }
 638
 639 static const struct dcn_vmid_registers vmid_regs[] = {
 640         vmid_regs(0),
 641         vmid_regs(1),
 642         vmid_regs(2),
 643         vmid_regs(3),
 644         vmid_regs(4),
 645         vmid_regs(5),
 646         vmid_regs(6),
 647         vmid_regs(7),
 648         vmid_regs(8),
 649         vmid_regs(9),
 650         vmid_regs(10),
 651         vmid_regs(11),
 652         vmid_regs(12),
 653         vmid_regs(13),
 654         vmid_regs(14),
 655         vmid_regs(15)
 656 };
 657
 658 static const struct dcn20_vmid_shift vmid_shifts = {
 659                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 660 };
 661
 662 static const struct dcn20_vmid_mask vmid_masks = {
 663                 DCN20_VMID_MASK_SH_LIST(_MASK)
 664 };
 665
 666 static const struct resource_caps res_cap_dcn3 = {
 667         .num_timing_generator = 6,
 668         .num_opp = 6,
 669         .num_video_plane = 6,
 670         .num_audio = 6,
 671         .num_stream_encoder = 6,
 672         .num_pll = 6,
 673         .num_dwb = 1,
 674         .num_ddc = 6,
 675         .num_vmid = 16,
 676         .num_mpc_3dlut = 3,
 677         .num_dsc = 6,
 678 };
 679
 680 static const struct dc_plane_cap plane_cap = {
 681         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 682         .blends_with_above = true,
 683         .blends_with_below = true,
 684         .per_pixel_alpha = true,
 685
 686         .pixel_format_support = {
 687                         .argb8888 = true,
 688                         .nv12 = true,
 689                         .fp16 = true,
 690                         .p010 = true,
 691                         .ayuv = false,
 692         },
 693
 694         .max_upscale_factor = {
 695                         .argb8888 = 16000,
 696                         .nv12 = 16000,
 697                         .fp16 = 16000
 698         },
 699
 700         /* 6:1 downscaling ratio: 1000/6 = 166.666 */
 701         .max_downscale_factor = {
 702                         .argb8888 = 167,
 703                         .nv12 = 167,
 704                         .fp16 = 167
 705         }
 706 };
 707
 708 static const struct dc_debug_options debug_defaults_drv = {
 709         .disable_dmcu = true, //No DMCU on DCN30
 710         .force_abm_enable = false,
 711         .timing_trace = false,
 712         .clock_trace = true,
 713         .disable_pplib_clock_request = true,
 714         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 715         .force_single_disp_pipe_split = false,
 716         .disable_dcc = DCC_ENABLE,
 717         .vsr_support = true,
 718         .performance_trace = false,
 719         .max_downscale_src_width = 7680,/*upto 8K*/
 720         .disable_pplib_wm_range = false,
 721         .scl_reset_length10 = true,
 722         .sanity_checks = false,
 723         .underflow_assert_delay_us = 0xFFFFFFFF,
 724         .dwb_fi_phase = -1, // -1 = disable,
 725         .dmub_command_table = true,
 726         .disable_psr = false,
 727         .use_max_lb = true,
 728         .exit_idle_opt_for_cursor_updates = true
 729 };
 730
 731 static const struct dc_debug_options debug_defaults_diags = {
 732         .disable_dmcu = true, //No dmcu on DCN30
 733         .force_abm_enable = false,
 734         .timing_trace = true,
 735         .clock_trace = true,
 736         .disable_dpp_power_gate = true,
 737         .disable_hubp_power_gate = true,
 738         .disable_clock_gate = true,
 739         .disable_pplib_clock_request = true,
 740         .disable_pplib_wm_range = true,
 741         .disable_stutter = false,
 742         .scl_reset_length10 = true,
 743         .dwb_fi_phase = -1, // -1 = disable
 744         .dmub_command_table = true,
 745         .disable_psr = true,
 746         .enable_tri_buf = true,
 747         .use_max_lb = true
 748 };
 749
 750 static void dcn30_dpp_destroy(struct dpp **dpp)
 751 {
 752         kfree(TO_DCN20_DPP(*dpp));
 753         *dpp = NULL;
 754 }
 755
 756 static struct dpp *dcn30_dpp_create(
 757         struct dc_context *ctx,
 758         uint32_t inst)
 759 {
 760         struct dcn3_dpp *dpp =
 761                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 762
 763         if (!dpp)
 764                 return NULL;
 765
 766         if (dpp3_construct(dpp, ctx, inst,
 767                         &dpp_regs[inst], &tf_shift, &tf_mask))
 768                 return &dpp->base;
 769
 770         BREAK_TO_DEBUGGER();
 771         kfree(dpp);
 772         return NULL;
 773 }
 774
 775 static struct output_pixel_processor *dcn30_opp_create(
 776         struct dc_context *ctx, uint32_t inst)
 777 {
 778         struct dcn20_opp *opp =
 779                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 780
 781         if (!opp) {
 782                 BREAK_TO_DEBUGGER();
 783                 return NULL;
 784         }
 785
 786         dcn20_opp_construct(opp, ctx, inst,
 787                         &opp_regs[inst], &opp_shift, &opp_mask);
 788         return &opp->base;
 789 }
 790
 791 static struct dce_aux *dcn30_aux_engine_create(
 792         struct dc_context *ctx,
 793         uint32_t inst)
 794 {
 795         struct aux_engine_dce110 *aux_engine =
 796                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 797
 798         if (!aux_engine)
 799                 return NULL;
 800
 801         dce110_aux_engine_construct(aux_engine, ctx, inst,
 802                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 803                                     &aux_engine_regs[inst],
 804                                         &aux_mask,
 805                                         &aux_shift,
 806                                         ctx->dc->caps.extended_aux_timeout_support);
 807
 808         return &aux_engine->base;
 809 }
 810
 811 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 812
 813 static const struct dce_i2c_registers i2c_hw_regs[] = {
 814                 i2c_inst_regs(1),
 815                 i2c_inst_regs(2),
 816                 i2c_inst_regs(3),
 817                 i2c_inst_regs(4),
 818                 i2c_inst_regs(5),
 819                 i2c_inst_regs(6),
 820 };
 821
 822 static const struct dce_i2c_shift i2c_shifts = {
 823                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 824 };
 825
 826 static const struct dce_i2c_mask i2c_masks = {
 827                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 828 };
 829
 830 static struct dce_i2c_hw *dcn30_i2c_hw_create(
 831         struct dc_context *ctx,
 832         uint32_t inst)
 833 {
 834         struct dce_i2c_hw *dce_i2c_hw =
 835                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 836
 837         if (!dce_i2c_hw)
 838                 return NULL;
 839
 840         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 841                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 842
 843         return dce_i2c_hw;
 844 }
 845
 846 static struct mpc *dcn30_mpc_create(
 847                 struct dc_context *ctx,
 848                 int num_mpcc,
 849                 int num_rmu)
 850 {
 851         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
 852                                           GFP_KERNEL);
 853
 854         if (!mpc30)
 855                 return NULL;
 856
 857         dcn30_mpc_construct(mpc30, ctx,
 858                         &mpc_regs,
 859                         &mpc_shift,
 860                         &mpc_mask,
 861                         num_mpcc,
 862                         num_rmu);
 863
 864         return &mpc30->base;
 865 }
 866
 867 static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
 868 {
 869         int i;
 870
 871         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 872                                           GFP_KERNEL);
 873
 874         if (!hubbub3)
 875                 return NULL;
 876
 877         hubbub3_construct(hubbub3, ctx,
 878                         &hubbub_reg,
 879                         &hubbub_shift,
 880                         &hubbub_mask);
 881
 882
 883         for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
 884                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
 885
 886                 vmid->ctx = ctx;
 887
 888                 vmid->regs = &vmid_regs[i];
 889                 vmid->shifts = &vmid_shifts;
 890                 vmid->masks = &vmid_masks;
 891         }
 892
 893         return &hubbub3->base;
 894 }
 895
 896 static struct timing_generator *dcn30_timing_generator_create(
 897                 struct dc_context *ctx,
 898                 uint32_t instance)
 899 {
 900         struct optc *tgn10 =
 901                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 902
 903         if (!tgn10)
 904                 return NULL;
 905
 906         tgn10->base.inst = instance;
 907         tgn10->base.ctx = ctx;
 908
 909         tgn10->tg_regs = &optc_regs[instance];
 910         tgn10->tg_shift = &optc_shift;
 911         tgn10->tg_mask = &optc_mask;
 912
 913         dcn30_timing_generator_init(tgn10);
 914
 915         return &tgn10->base;
 916 }
 917
 918 static const struct encoder_feature_support link_enc_feature = {
 919                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 920                 .max_hdmi_pixel_clock = 600000,
 921                 .hdmi_ycbcr420_supported = true,
 922                 .dp_ycbcr420_supported = true,
 923                 .fec_supported = true,
 924                 .flags.bits.IS_HBR2_CAPABLE = true,
 925                 .flags.bits.IS_HBR3_CAPABLE = true,
 926                 .flags.bits.IS_TPS3_CAPABLE = true,
 927                 .flags.bits.IS_TPS4_CAPABLE = true
 928 };
 929
 930 static struct link_encoder *dcn30_link_encoder_create(
 931         struct dc_context *ctx,
 932         const struct encoder_init_data *enc_init_data)
 933 {
 934         struct dcn20_link_encoder *enc20 =
 935                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
 936
 937         if (!enc20)
 938                 return NULL;
 939
 940         dcn30_link_encoder_construct(enc20,
 941                         enc_init_data,
 942                         &link_enc_feature,
 943                         &link_enc_regs[enc_init_data->transmitter],
 944                         &link_enc_aux_regs[enc_init_data->channel - 1],
 945                         &link_enc_hpd_regs[enc_init_data->hpd_source],
 946                         &le_shift,
 947                         &le_mask);
 948
 949         return &enc20->enc10.base;
 950 }
 951
 952 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 953 {
 954         struct dce_panel_cntl *panel_cntl =
 955                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 956
 957         if (!panel_cntl)
 958                 return NULL;
 959
 960         dce_panel_cntl_construct(panel_cntl,
 961                         init_data,
 962                         &panel_cntl_regs[init_data->inst],
 963                         &panel_cntl_shift,
 964                         &panel_cntl_mask);
 965
 966         return &panel_cntl->base;
 967 }
 968
 969 static void read_dce_straps(
 970         struct dc_context *ctx,
 971         struct resource_straps *straps)
 972 {
 973         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 974                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 975
 976 }
 977
 978 static struct audio *dcn30_create_audio(
 979                 struct dc_context *ctx, unsigned int inst)
 980 {
 981         return dce_audio_create(ctx, inst,
 982                         &audio_regs[inst], &audio_shift, &audio_mask);
 983 }
 984
 985 static struct vpg *dcn30_vpg_create(
 986         struct dc_context *ctx,
 987         uint32_t inst)
 988 {
 989         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
 990
 991         if (!vpg3)
 992                 return NULL;
 993
 994         vpg3_construct(vpg3, ctx, inst,
 995                         &vpg_regs[inst],
 996                         &vpg_shift,
 997                         &vpg_mask);
 998
 999         return &vpg3->base;
1000 }
1001
1002 static struct afmt *dcn30_afmt_create(
1003         struct dc_context *ctx,
1004         uint32_t inst)
1005 {
1006         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1007
1008         if (!afmt3)
1009                 return NULL;
1010
1011         afmt3_construct(afmt3, ctx, inst,
1012                         &afmt_regs[inst],
1013                         &afmt_shift,
1014                         &afmt_mask);
1015
1016         return &afmt3->base;
1017 }
1018
1019 static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1020                                                           struct dc_context *ctx)
1021 {
1022         struct dcn10_stream_encoder *enc1;
1023         struct vpg *vpg;
1024         struct afmt *afmt;
1025         int vpg_inst;
1026         int afmt_inst;
1027
1028         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1029         if (eng_id <= ENGINE_ID_DIGF) {
1030                 vpg_inst = eng_id;
1031                 afmt_inst = eng_id;
1032         } else
1033                 return NULL;
1034
1035         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1036         vpg = dcn30_vpg_create(ctx, vpg_inst);
1037         afmt = dcn30_afmt_create(ctx, afmt_inst);
1038
1039         if (!enc1 || !vpg || !afmt) {
1040                 kfree(enc1);
1041                 kfree(vpg);
1042                 kfree(afmt);
1043                 return NULL;
1044         }
1045
1046         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1047                                         eng_id, vpg, afmt,
1048                                         &stream_enc_regs[eng_id],
1049                                         &se_shift, &se_mask);
1050
1051         return &enc1->base;
1052 }
1053
1054 static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1055 {
1056         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1057
1058         if (hws) {
1059                 hws->ctx = ctx;
1060                 hws->regs = &hwseq_reg;
1061                 hws->shifts = &hwseq_shift;
1062                 hws->masks = &hwseq_mask;
1063         }
1064         return hws;
1065 }
1066 static const struct resource_create_funcs res_create_funcs = {
1067         .read_dce_straps = read_dce_straps,
1068         .create_audio = dcn30_create_audio,
1069         .create_stream_encoder = dcn30_stream_encoder_create,
1070         .create_hwseq = dcn30_hwseq_create,
1071 };
1072
1073 static const struct resource_create_funcs res_create_maximus_funcs = {
1074         .read_dce_straps = NULL,
1075         .create_audio = NULL,
1076         .create_stream_encoder = NULL,
1077         .create_hwseq = dcn30_hwseq_create,
1078 };
1079
1080 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1081 {
1082         unsigned int i;
1083
1084         for (i = 0; i < pool->base.stream_enc_count; i++) {
1085                 if (pool->base.stream_enc[i] != NULL) {
1086                         if (pool->base.stream_enc[i]->vpg != NULL) {
1087                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1088                                 pool->base.stream_enc[i]->vpg = NULL;
1089                         }
1090                         if (pool->base.stream_enc[i]->afmt != NULL) {
1091                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1092                                 pool->base.stream_enc[i]->afmt = NULL;
1093                         }
1094                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1095                         pool->base.stream_enc[i] = NULL;
1096                 }
1097         }
1098
1099         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1100                 if (pool->base.dscs[i] != NULL)
1101                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1102         }
1103
1104         if (pool->base.mpc != NULL) {
1105                 kfree(TO_DCN20_MPC(pool->base.mpc));
1106                 pool->base.mpc = NULL;
1107         }
1108         if (pool->base.hubbub != NULL) {
1109                 kfree(pool->base.hubbub);
1110                 pool->base.hubbub = NULL;
1111         }
1112         for (i = 0; i < pool->base.pipe_count; i++) {
1113                 if (pool->base.dpps[i] != NULL)
1114                         dcn30_dpp_destroy(&pool->base.dpps[i]);
1115
1116                 if (pool->base.ipps[i] != NULL)
1117                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1118
1119                 if (pool->base.hubps[i] != NULL) {
1120                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1121                         pool->base.hubps[i] = NULL;
1122                 }
1123
1124                 if (pool->base.irqs != NULL) {
1125                         dal_irq_service_destroy(&pool->base.irqs);
1126                 }
1127         }
1128
1129         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1130                 if (pool->base.engines[i] != NULL)
1131                         dce110_engine_destroy(&pool->base.engines[i]);
1132                 if (pool->base.hw_i2cs[i] != NULL) {
1133                         kfree(pool->base.hw_i2cs[i]);
1134                         pool->base.hw_i2cs[i] = NULL;
1135                 }
1136                 if (pool->base.sw_i2cs[i] != NULL) {
1137                         kfree(pool->base.sw_i2cs[i]);
1138                         pool->base.sw_i2cs[i] = NULL;
1139                 }
1140         }
1141
1142         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1143                 if (pool->base.opps[i] != NULL)
1144                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1145         }
1146
1147         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1148                 if (pool->base.timing_generators[i] != NULL)    {
1149                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1150                         pool->base.timing_generators[i] = NULL;
1151                 }
1152         }
1153
1154         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1155                 if (pool->base.dwbc[i] != NULL) {
1156                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1157                         pool->base.dwbc[i] = NULL;
1158                 }
1159                 if (pool->base.mcif_wb[i] != NULL) {
1160                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1161                         pool->base.mcif_wb[i] = NULL;
1162                 }
1163         }
1164
1165         for (i = 0; i < pool->base.audio_count; i++) {
1166                 if (pool->base.audios[i])
1167                         dce_aud_destroy(&pool->base.audios[i]);
1168         }
1169
1170         for (i = 0; i < pool->base.clk_src_count; i++) {
1171                 if (pool->base.clock_sources[i] != NULL) {
1172                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1173                         pool->base.clock_sources[i] = NULL;
1174                 }
1175         }
1176
1177         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1178                 if (pool->base.mpc_lut[i] != NULL) {
1179                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1180                         pool->base.mpc_lut[i] = NULL;
1181                 }
1182                 if (pool->base.mpc_shaper[i] != NULL) {
1183                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1184                         pool->base.mpc_shaper[i] = NULL;
1185                 }
1186         }
1187
1188         if (pool->base.dp_clock_source != NULL) {
1189                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1190                 pool->base.dp_clock_source = NULL;
1191         }
1192
1193         for (i = 0; i < pool->base.pipe_count; i++) {
1194                 if (pool->base.multiple_abms[i] != NULL)
1195                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1196         }
1197
1198         if (pool->base.psr != NULL)
1199                 dmub_psr_destroy(&pool->base.psr);
1200
1201         if (pool->base.dccg != NULL)
1202                 dcn_dccg_destroy(&pool->base.dccg);
1203
1204         if (pool->base.oem_device != NULL)
1205                 dal_ddc_service_destroy(&pool->base.oem_device);
1206 }
1207
1208 static struct hubp *dcn30_hubp_create(
1209         struct dc_context *ctx,
1210         uint32_t inst)
1211 {
1212         struct dcn20_hubp *hubp2 =
1213                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1214
1215         if (!hubp2)
1216                 return NULL;
1217
1218         if (hubp3_construct(hubp2, ctx, inst,
1219                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1220                 return &hubp2->base;
1221
1222         BREAK_TO_DEBUGGER();
1223         kfree(hubp2);
1224         return NULL;
1225 }
1226
1227 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1228 {
1229         int i;
1230         uint32_t pipe_count = pool->res_cap->num_dwb;
1231
1232         for (i = 0; i < pipe_count; i++) {
1233                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1234                                                     GFP_KERNEL);
1235
1236                 if (!dwbc30) {
1237                         dm_error("DC: failed to create dwbc30!\n");
1238                         return false;
1239                 }
1240
1241                 dcn30_dwbc_construct(dwbc30, ctx,
1242                                 &dwbc30_regs[i],
1243                                 &dwbc30_shift,
1244                                 &dwbc30_mask,
1245                                 i);
1246
1247                 pool->dwbc[i] = &dwbc30->base;
1248         }
1249         return true;
1250 }
1251
1252 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1253 {
1254         int i;
1255         uint32_t pipe_count = pool->res_cap->num_dwb;
1256
1257         for (i = 0; i < pipe_count; i++) {
1258                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1259                                                     GFP_KERNEL);
1260
1261                 if (!mcif_wb30) {
1262                         dm_error("DC: failed to create mcif_wb30!\n");
1263                         return false;
1264                 }
1265
1266                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1267                                 &mcif_wb30_regs[i],
1268                                 &mcif_wb30_shift,
1269                                 &mcif_wb30_mask,
1270                                 i);
1271
1272                 pool->mcif_wb[i] = &mcif_wb30->base;
1273         }
1274         return true;
1275 }
1276
1277 static struct display_stream_compressor *dcn30_dsc_create(
1278         struct dc_context *ctx, uint32_t inst)
1279 {
1280         struct dcn20_dsc *dsc =
1281                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1282
1283         if (!dsc) {
1284                 BREAK_TO_DEBUGGER();
1285                 return NULL;
1286         }
1287
1288         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1289         return &dsc->base;
1290 }
1291
1292 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1293 {
1294
1295         return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1296 }
1297
1298 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1299 {
1300         struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1301
1302         dcn30_resource_destruct(dcn30_pool);
1303         kfree(dcn30_pool);
1304         *pool = NULL;
1305 }
1306
1307 static struct clock_source *dcn30_clock_source_create(
1308                 struct dc_context *ctx,
1309                 struct dc_bios *bios,
1310                 enum clock_source_id id,
1311                 const struct dce110_clk_src_regs *regs,
1312                 bool dp_clk_src)
1313 {
1314         struct dce110_clk_src *clk_src =
1315                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1316
1317         if (!clk_src)
1318                 return NULL;
1319
1320         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1321                         regs, &cs_shift, &cs_mask)) {
1322                 clk_src->base.dp_clk_src = dp_clk_src;
1323                 return &clk_src->base;
1324         }
1325
1326         BREAK_TO_DEBUGGER();
1327         return NULL;
1328 }
1329
1330 int dcn30_populate_dml_pipes_from_context(
1331         struct dc *dc, struct dc_state *context,
1332         display_e2e_pipe_params_st *pipes,
1333         bool fast_validate)
1334 {
1335         int i, pipe_cnt;
1336         struct resource_context *res_ctx = &context->res_ctx;
1337
1338         DC_FP_START();
1339         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1340         DC_FP_END();
1341
1342         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1343                 if (!res_ctx->pipe_ctx[i].stream)
1344                         continue;
1345
1346                 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1347                         dm_lb_16;
1348         }
1349
1350         return pipe_cnt;
1351 }
1352
1353 void dcn30_populate_dml_writeback_from_context(
1354         struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1355 {
1356         DC_FP_START();
1357         dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1358         DC_FP_END();
1359 }
1360
1361 unsigned int dcn30_calc_max_scaled_time(
1362                 unsigned int time_per_pixel,
1363                 enum mmhubbub_wbif_mode mode,
1364                 unsigned int urgent_watermark)
1365 {
1366         unsigned int time_per_byte = 0;
1367         unsigned int total_free_entry = 0xb40;
1368         unsigned int buf_lh_capability;
1369         unsigned int max_scaled_time;
1370
1371         if (mode == PACKED_444) /* packed mode 32 bpp */
1372                 time_per_byte = time_per_pixel/4;
1373         else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1374                 time_per_byte = time_per_pixel/8;
1375
1376         if (time_per_byte == 0)
1377                 time_per_byte = 1;
1378
1379         buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1380         max_scaled_time   = buf_lh_capability - urgent_watermark;
1381         return max_scaled_time;
1382 }
1383
1384 void dcn30_set_mcif_arb_params(
1385                 struct dc *dc,
1386                 struct dc_state *context,
1387                 display_e2e_pipe_params_st *pipes,
1388                 int pipe_cnt)
1389 {
1390         enum mmhubbub_wbif_mode wbif_mode;
1391         struct display_mode_lib *dml = &context->bw_ctx.dml;
1392         struct mcif_arb_params *wb_arb_params;
1393         int i, j, dwb_pipe;
1394
1395         /* Writeback MCIF_WB arbitration parameters */
1396         dwb_pipe = 0;
1397         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1398
1399                 if (!context->res_ctx.pipe_ctx[i].stream)
1400                         continue;
1401
1402                 for (j = 0; j < MAX_DWB_PIPES; j++) {
1403                         struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1404
1405                         if (writeback_info->wb_enabled == false)
1406                                 continue;
1407
1408                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1409                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1410
1411                         if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1412                                 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1413                                 wbif_mode = PACKED_444_FP16;
1414                         else
1415                                 wbif_mode = PACKED_444;
1416
1417                         DC_FP_START();
1418                         dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1419                         DC_FP_END();
1420                         wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1421                         wb_arb_params->slice_lines = 32;
1422                         wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1423                         wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1424                                         wbif_mode,
1425                                         wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1426
1427                         dwb_pipe++;
1428
1429                         if (dwb_pipe >= MAX_DWB_PIPES)
1430                                 return;
1431                 }
1432                 if (dwb_pipe >= MAX_DWB_PIPES)
1433                         return;
1434         }
1435
1436 }
1437
1438 static struct dc_cap_funcs cap_funcs = {
1439         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1440 };
1441
1442 bool dcn30_acquire_post_bldn_3dlut(
1443                 struct resource_context *res_ctx,
1444                 const struct resource_pool *pool,
1445                 int mpcc_id,
1446                 struct dc_3dlut **lut,
1447                 struct dc_transfer_func **shaper)
1448 {
1449         int i;
1450         bool ret = false;
1451         union dc_3dlut_state *state;
1452
1453         ASSERT(*lut == NULL && *shaper == NULL);
1454         *lut = NULL;
1455         *shaper = NULL;
1456
1457         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1458                 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1459                         *lut = pool->mpc_lut[i];
1460                         *shaper = pool->mpc_shaper[i];
1461                         state = &pool->mpc_lut[i]->state;
1462                         res_ctx->is_mpc_3dlut_acquired[i] = true;
1463                         state->bits.rmu_idx_valid = 1;
1464                         state->bits.rmu_mux_num = i;
1465                         if (state->bits.rmu_mux_num == 0)
1466                                 state->bits.mpc_rmu0_mux = mpcc_id;
1467                         else if (state->bits.rmu_mux_num == 1)
1468                                 state->bits.mpc_rmu1_mux = mpcc_id;
1469                         else if (state->bits.rmu_mux_num == 2)
1470                                 state->bits.mpc_rmu2_mux = mpcc_id;
1471                         ret = true;
1472                         break;
1473                         }
1474                 }
1475         return ret;
1476 }
1477
1478 bool dcn30_release_post_bldn_3dlut(
1479                 struct resource_context *res_ctx,
1480                 const struct resource_pool *pool,
1481                 struct dc_3dlut **lut,
1482                 struct dc_transfer_func **shaper)
1483 {
1484         int i;
1485         bool ret = false;
1486
1487         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1488                 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1489                         res_ctx->is_mpc_3dlut_acquired[i] = false;
1490                         pool->mpc_lut[i]->state.raw = 0;
1491                         *lut = NULL;
1492                         *shaper = NULL;
1493                         ret = true;
1494                         break;
1495                 }
1496         }
1497         return ret;
1498 }
1499
1500 static bool is_soc_bounding_box_valid(struct dc *dc)
1501 {
1502         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1503
1504         if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1505                 return true;
1506
1507         return false;
1508 }
1509
1510 static bool init_soc_bounding_box(struct dc *dc,
1511                                   struct dcn30_resource_pool *pool)
1512 {
1513         struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1514         struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1515
1516         DC_LOGGER_INIT(dc->ctx->logger);
1517
1518         if (!is_soc_bounding_box_valid(dc)) {
1519                 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1520                 return false;
1521         }
1522
1523         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1524         loaded_ip->max_num_dpp = pool->base.pipe_count;
1525         loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1526         dcn20_patch_bounding_box(dc, loaded_bb);
1527         DC_FP_START();
1528         patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);
1529         DC_FP_END();
1530
1531         return true;
1532 }
1533
1534 static bool dcn30_split_stream_for_mpc_or_odm(
1535                 const struct dc *dc,
1536                 struct resource_context *res_ctx,
1537                 struct pipe_ctx *pri_pipe,
1538                 struct pipe_ctx *sec_pipe,
1539                 bool odm)
1540 {
1541         int pipe_idx = sec_pipe->pipe_idx;
1542         const struct resource_pool *pool = dc->res_pool;
1543
1544         *sec_pipe = *pri_pipe;
1545
1546         sec_pipe->pipe_idx = pipe_idx;
1547         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1548         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1549         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1550         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1551         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1552         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1553         sec_pipe->stream_res.dsc = NULL;
1554         if (odm) {
1555                 if (pri_pipe->next_odm_pipe) {
1556                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1557                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1558                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1559                 }
1560                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1561                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1562                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1563                 }
1564                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1565                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1566                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1567                 }
1568                 pri_pipe->next_odm_pipe = sec_pipe;
1569                 sec_pipe->prev_odm_pipe = pri_pipe;
1570
1571                 if (!sec_pipe->top_pipe)
1572                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1573                 else
1574                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1575                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1576                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1577                         ASSERT(sec_pipe->stream_res.dsc);
1578                         if (sec_pipe->stream_res.dsc == NULL)
1579                                 return false;
1580                 }
1581         } else {
1582                 if (pri_pipe->bottom_pipe) {
1583                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1584                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1585                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1586                 }
1587                 pri_pipe->bottom_pipe = sec_pipe;
1588                 sec_pipe->top_pipe = pri_pipe;
1589
1590                 ASSERT(pri_pipe->plane_state);
1591         }
1592
1593         return true;
1594 }
1595
1596 static struct pipe_ctx *dcn30_find_split_pipe(
1597                 struct dc *dc,
1598                 struct dc_state *context,
1599                 int old_index)
1600 {
1601         struct pipe_ctx *pipe = NULL;
1602         int i;
1603
1604         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1605                 pipe = &context->res_ctx.pipe_ctx[old_index];
1606                 pipe->pipe_idx = old_index;
1607         }
1608
1609         if (!pipe)
1610                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1611                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1612                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1613                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1614                                         pipe = &context->res_ctx.pipe_ctx[i];
1615                                         pipe->pipe_idx = i;
1616                                         break;
1617                                 }
1618                         }
1619                 }
1620
1621         /*
1622          * May need to fix pipes getting tossed from 1 opp to another on flip
1623          * Add for debugging transient underflow during topology updates:
1624          * ASSERT(pipe);
1625          */
1626         if (!pipe)
1627                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1628                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1629                                 pipe = &context->res_ctx.pipe_ctx[i];
1630                                 pipe->pipe_idx = i;
1631                                 break;
1632                         }
1633                 }
1634
1635         return pipe;
1636 }
1637
1638 noinline bool dcn30_internal_validate_bw(
1639                 struct dc *dc,
1640                 struct dc_state *context,
1641                 display_e2e_pipe_params_st *pipes,
1642                 int *pipe_cnt_out,
1643                 int *vlevel_out,
1644                 bool fast_validate)
1645 {
1646         bool out = false;
1647         bool repopulate_pipes = false;
1648         int split[MAX_PIPES] = { 0 };
1649         bool merge[MAX_PIPES] = { false };
1650         bool newly_split[MAX_PIPES] = { false };
1651         int pipe_cnt, i, pipe_idx, vlevel;
1652         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1653
1654         ASSERT(pipes);
1655         if (!pipes)
1656                 return false;
1657
1658         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1659         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1660
1661         if (!pipe_cnt) {
1662                 out = true;
1663                 goto validate_out;
1664         }
1665
1666         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1667
1668         if (!fast_validate) {
1669                 /*
1670                  * DML favors voltage over p-state, but we're more interested in
1671                  * supporting p-state over voltage. We can't support p-state in
1672                  * prefetch mode > 0 so try capping the prefetch mode to start.
1673                  */
1674                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1675                         dm_allow_self_refresh_and_mclk_switch;
1676                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1677                 /* This may adjust vlevel and maxMpcComb */
1678                 if (vlevel < context->bw_ctx.dml.soc.num_states)
1679                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1680         }
1681         if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1682                         vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1683                 /*
1684                  * If mode is unsupported or there's still no p-state support then
1685                  * fall back to favoring voltage.
1686                  *
1687                  * We don't actually support prefetch mode 2, so require that we
1688                  * at least support prefetch mode 1.
1689                  */
1690                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1691                         dm_allow_self_refresh;
1692
1693                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1694                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1695                         memset(split, 0, sizeof(split));
1696                         memset(merge, 0, sizeof(merge));
1697                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1698                 }
1699         }
1700
1701         dml_log_mode_support_params(&context->bw_ctx.dml);
1702
1703         if (vlevel == context->bw_ctx.dml.soc.num_states)
1704                 goto validate_fail;
1705
1706         if (!dc->config.enable_windowed_mpo_odm) {
1707                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1708                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1709                         struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1710
1711                         if (!pipe->stream)
1712                                 continue;
1713
1714                         /* We only support full screen mpo with ODM */
1715                         if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1716                                         && pipe->plane_state && mpo_pipe
1717                                         && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1718                                                         &pipe->plane_res.scl_data.recout,
1719                                                         sizeof(struct rect)) != 0) {
1720                                 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1721                                 goto validate_fail;
1722                         }
1723                         pipe_idx++;
1724                 }
1725         }
1726
1727         /* merge pipes if necessary */
1728         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1729                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1730
1731                 /*skip pipes that don't need merging*/
1732                 if (!merge[i])
1733                         continue;
1734
1735                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1736                 if (pipe->prev_odm_pipe) {
1737                         /*split off odm pipe*/
1738                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1739                         if (pipe->next_odm_pipe)
1740                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1741
1742                         pipe->bottom_pipe = NULL;
1743                         pipe->next_odm_pipe = NULL;
1744                         pipe->plane_state = NULL;
1745                         pipe->stream = NULL;
1746                         pipe->top_pipe = NULL;
1747                         pipe->prev_odm_pipe = NULL;
1748                         if (pipe->stream_res.dsc)
1749                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1750                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1751                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1752                         repopulate_pipes = true;
1753                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1754                         struct pipe_ctx *top_pipe = pipe->top_pipe;
1755                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1756
1757                         top_pipe->bottom_pipe = bottom_pipe;
1758                         if (bottom_pipe)
1759                                 bottom_pipe->top_pipe = top_pipe;
1760
1761                         pipe->top_pipe = NULL;
1762                         pipe->bottom_pipe = NULL;
1763                         pipe->plane_state = NULL;
1764                         pipe->stream = NULL;
1765                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1766                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1767                         repopulate_pipes = true;
1768                 } else
1769                         ASSERT(0); /* Should never try to merge master pipe */
1770
1771         }
1772
1773         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1774                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1775                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1776                 struct pipe_ctx *hsplit_pipe = NULL;
1777                 bool odm;
1778                 int old_index = -1;
1779
1780                 if (!pipe->stream || newly_split[i])
1781                         continue;
1782
1783                 pipe_idx++;
1784                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1785
1786                 if (!pipe->plane_state && !odm)
1787                         continue;
1788
1789                 if (split[i]) {
1790                         if (odm) {
1791                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1792                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1793                                 else if (old_pipe->next_odm_pipe)
1794                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
1795                         } else {
1796                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1797                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1798                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1799                                 else if (old_pipe->bottom_pipe &&
1800                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1801                                         old_index = old_pipe->bottom_pipe->pipe_idx;
1802                         }
1803                         hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1804                         ASSERT(hsplit_pipe);
1805                         if (!hsplit_pipe)
1806                                 goto validate_fail;
1807
1808                         if (!dcn30_split_stream_for_mpc_or_odm(
1809                                         dc, &context->res_ctx,
1810                                         pipe, hsplit_pipe, odm))
1811                                 goto validate_fail;
1812
1813                         newly_split[hsplit_pipe->pipe_idx] = true;
1814                         repopulate_pipes = true;
1815                 }
1816                 if (split[i] == 4) {
1817                         struct pipe_ctx *pipe_4to1;
1818
1819                         if (odm && old_pipe->next_odm_pipe)
1820                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
1821                         else if (!odm && old_pipe->bottom_pipe &&
1822                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1823                                 old_index = old_pipe->bottom_pipe->pipe_idx;
1824                         else
1825                                 old_index = -1;
1826                         pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1827                         ASSERT(pipe_4to1);
1828                         if (!pipe_4to1)
1829                                 goto validate_fail;
1830                         if (!dcn30_split_stream_for_mpc_or_odm(
1831                                         dc, &context->res_ctx,
1832                                         pipe, pipe_4to1, odm))
1833                                 goto validate_fail;
1834                         newly_split[pipe_4to1->pipe_idx] = true;
1835
1836                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1837                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1838                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1839                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1840                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1841                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1842                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1843                         else
1844                                 old_index = -1;
1845                         pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1846                         ASSERT(pipe_4to1);
1847                         if (!pipe_4to1)
1848                                 goto validate_fail;
1849                         if (!dcn30_split_stream_for_mpc_or_odm(
1850                                         dc, &context->res_ctx,
1851                                         hsplit_pipe, pipe_4to1, odm))
1852                                 goto validate_fail;
1853                         newly_split[pipe_4to1->pipe_idx] = true;
1854                 }
1855                 if (odm)
1856                         dcn20_build_mapped_resource(dc, context, pipe->stream);
1857         }
1858
1859         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1860                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1861
1862                 if (pipe->plane_state) {
1863                         if (!resource_build_scaling_params(pipe))
1864                                 goto validate_fail;
1865                 }
1866         }
1867
1868         /* Actual dsc count per stream dsc validation*/
1869         if (!dcn20_validate_dsc(dc, context)) {
1870                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1871                 goto validate_fail;
1872         }
1873
1874         if (repopulate_pipes)
1875                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1876         *vlevel_out = vlevel;
1877         *pipe_cnt_out = pipe_cnt;
1878
1879         out = true;
1880         goto validate_out;
1881
1882 validate_fail:
1883         out = false;
1884
1885 validate_out:
1886         return out;
1887 }
1888
1889 static int get_refresh_rate(struct dc_state *context)
1890 {
1891         int refresh_rate = 0;
1892         int h_v_total = 0;
1893         struct dc_crtc_timing *timing = NULL;
1894
1895         if (context == NULL || context->streams[0] == NULL)
1896                 return 0;
1897
1898         /* check if refresh rate at least 120hz */
1899         timing = &context->streams[0]->timing;
1900         if (timing == NULL)
1901                 return 0;
1902
1903         h_v_total = timing->h_total * timing->v_total;
1904         if (h_v_total == 0)
1905                 return 0;
1906
1907         refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1908         return refresh_rate;
1909 }
1910
1911 #define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
1912 /*
1913  * Scaling factor for v_blank stretch calculations considering timing in
1914  * micro-seconds and pixel clock in 100hz.
1915  * Note: the parenthesis are necessary to ensure the correct order of
1916  * operation where V_SCALE is used.
1917  */
1918 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
1919
1920 static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
1921 {
1922         struct dc_crtc_timing *timing = NULL;
1923         uint32_t sec_per_100_lines;
1924         uint32_t max_v_blank;
1925         uint32_t curr_v_blank;
1926         uint32_t v_stretch_max;
1927         uint32_t stretched_frame_pix_cnt;
1928         uint32_t scaled_stretched_frame_pix_cnt;
1929         uint32_t scaled_refresh_rate;
1930
1931         if (context == NULL || context->streams[0] == NULL)
1932                 return 0;
1933
1934         /* check if refresh rate at least 120hz */
1935         timing = &context->streams[0]->timing;
1936         if (timing == NULL)
1937                 return 0;
1938
1939         sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1940         max_v_blank = sec_per_100_lines / V_SCALE + 1;
1941         curr_v_blank = timing->v_total - timing->v_addressable;
1942         v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
1943         stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
1944         scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
1945         scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
1946
1947         return scaled_refresh_rate;
1948 }
1949
1950 static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
1951 {
1952         int refresh_rate_max_stretch_100hz;
1953         int min_refresh_100hz;
1954
1955         if (context == NULL || context->streams[0] == NULL)
1956                 return false;
1957
1958         refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
1959         min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
1960
1961         if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
1962                 return false;
1963
1964         return true;
1965 }
1966
1967 bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
1968 {
1969         int refresh_rate = 0;
1970         const int minimum_refreshrate_supported = 120;
1971
1972         if (context == NULL || context->streams[0] == NULL)
1973                 return false;
1974
1975         if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
1976                 return false;
1977
1978         if (dc->debug.disable_fams)
1979                 return false;
1980
1981         if (!dc->caps.dmub_caps.mclk_sw)
1982                 return false;
1983
1984         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
1985                 return false;
1986
1987         /* more then 1 monitor connected */
1988         if (context->stream_count != 1)
1989                 return false;
1990
1991         refresh_rate = get_refresh_rate(context);
1992         if (refresh_rate < minimum_refreshrate_supported)
1993                 return false;
1994
1995         if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
1996                 return false;
1997
1998         // check if freesync enabled
1999         if (!context->streams[0]->allow_freesync)
2000                 return false;
2001
2002         if (context->streams[0]->vrr_active_variable)
2003                 return false;
2004
2005         return true;
2006 }
2007
2008 /*
2009  * set up FPO watermarks, pstate, dram latency
2010  */
2011 void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2012 {
2013         ASSERT(dc != NULL && context != NULL);
2014         if (dc == NULL || context == NULL)
2015                 return;
2016
2017         /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2018         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2019 }
2020
2021 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2022 {
2023         DC_FP_START();
2024         dcn30_fpu_update_soc_for_wm_a(dc, context);
2025         DC_FP_END();
2026 }
2027
2028 void dcn30_calculate_wm_and_dlg(
2029                 struct dc *dc, struct dc_state *context,
2030                 display_e2e_pipe_params_st *pipes,
2031                 int pipe_cnt,
2032                 int vlevel)
2033 {
2034         DC_FP_START();
2035         dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2036         DC_FP_END();
2037 }
2038
2039 bool dcn30_validate_bandwidth(struct dc *dc,
2040                 struct dc_state *context,
2041                 bool fast_validate)
2042 {
2043         bool out = false;
2044
2045         BW_VAL_TRACE_SETUP();
2046
2047         int vlevel = 0;
2048         int pipe_cnt = 0;
2049         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2050         DC_LOGGER_INIT(dc->ctx->logger);
2051
2052         BW_VAL_TRACE_COUNT();
2053
2054         DC_FP_START();
2055         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2056         DC_FP_END();
2057
2058         if (pipe_cnt == 0)
2059                 goto validate_out;
2060
2061         if (!out)
2062                 goto validate_fail;
2063
2064         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2065
2066         if (fast_validate) {
2067                 BW_VAL_TRACE_SKIP(fast);
2068                 goto validate_out;
2069         }
2070
2071         DC_FP_START();
2072         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2073         DC_FP_END();
2074
2075         BW_VAL_TRACE_END_WATERMARKS();
2076
2077         goto validate_out;
2078
2079 validate_fail:
2080         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2081                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2082
2083         BW_VAL_TRACE_SKIP(fail);
2084         out = false;
2085
2086 validate_out:
2087         kfree(pipes);
2088
2089         BW_VAL_TRACE_FINISH();
2090
2091         return out;
2092 }
2093
2094 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2095 {
2096         unsigned int i, j;
2097         unsigned int num_states = 0;
2098
2099         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2100         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2101         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2102         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2103
2104         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2105         unsigned int num_dcfclk_sta_targets = 4;
2106         unsigned int num_uclk_states;
2107
2108         struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2109
2110         memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2111
2112         if (dc->ctx->dc_bios->vram_info.num_chans)
2113                 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2114
2115         DC_FP_START();
2116         dcn30_fpu_update_dram_channel_width_bytes(dc);
2117         DC_FP_END();
2118
2119         if (bw_params->clk_table.entries[0].memclk_mhz) {
2120
2121                 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2122                         if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2123                                 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2124                         if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
2125                                 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2126                         if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
2127                                 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2128                         if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
2129                                 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2130                 }
2131
2132                 DC_FP_START();
2133                 dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
2134                 DC_FP_END();
2135
2136                 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2137                         // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2138                         dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2139                         num_dcfclk_sta_targets++;
2140                 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2141                         // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2142                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
2143                                 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2144                                         dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2145                                         break;
2146                                 }
2147                         }
2148                         // Update size of array since we "removed" duplicates
2149                         num_dcfclk_sta_targets = i + 1;
2150                 }
2151
2152                 num_uclk_states = bw_params->clk_table.num_entries;
2153
2154                 // Calculate optimal dcfclk for each uclk
2155                 for (i = 0; i < num_uclk_states; i++) {
2156                         DC_FP_START();
2157                         dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2158                                         &optimal_dcfclk_for_uclk[i], NULL);
2159                         DC_FP_END();
2160                         if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2161                                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2162                         }
2163                 }
2164
2165                 // Calculate optimal uclk for each dcfclk sta target
2166                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2167                         for (j = 0; j < num_uclk_states; j++) {
2168                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2169                                         optimal_uclk_for_dcfclk_sta_targets[i] =
2170                                                         bw_params->clk_table.entries[j].memclk_mhz * 16;
2171                                         break;
2172                                 }
2173                         }
2174                 }
2175
2176                 i = 0;
2177                 j = 0;
2178                 // create the final dcfclk and uclk table
2179                 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2180                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2181                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2182                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2183                         } else {
2184                                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2185                                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2186                                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2187                                 } else {
2188                                         j = num_uclk_states;
2189                                 }
2190                         }
2191                 }
2192
2193                 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2194                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2195                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2196                 }
2197
2198                 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2199                                 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2200                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2201                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2202                 }
2203
2204                 dcn3_0_soc.num_states = num_states;
2205                 DC_FP_START();
2206                 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2207                 DC_FP_END();
2208         }
2209 }
2210
2211 static const struct resource_funcs dcn30_res_pool_funcs = {
2212         .destroy = dcn30_destroy_resource_pool,
2213         .link_enc_create = dcn30_link_encoder_create,
2214         .panel_cntl_create = dcn30_panel_cntl_create,
2215         .validate_bandwidth = dcn30_validate_bandwidth,
2216         .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2217         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2218         .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2219         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2220         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2221         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2222         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2223         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2224         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2225         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2226         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2227         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2228         .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2229         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2230 };
2231
2232 #define CTX ctx
2233
2234 #define REG(reg_name) \
2235         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2236
2237 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2238 {
2239         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2240         /* Support for max 6 pipes */
2241         value = value & 0x3f;
2242         return value;
2243 }
2244
2245 static bool dcn30_resource_construct(
2246         uint8_t num_virtual_links,
2247         struct dc *dc,
2248         struct dcn30_resource_pool *pool)
2249 {
2250         int i;
2251         struct dc_context *ctx = dc->ctx;
2252         struct irq_service_init_data init_data;
2253         struct ddc_service_init_data ddc_init_data = {0};
2254         uint32_t pipe_fuses = read_pipe_fuses(ctx);
2255         uint32_t num_pipes = 0;
2256
2257         if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2258                 BREAK_TO_DEBUGGER();
2259                 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2260                 /* fault to single pipe */
2261                 pipe_fuses = 0x3e;
2262         }
2263
2264         DC_FP_START();
2265
2266         ctx->dc_bios->regs = &bios_regs;
2267
2268         pool->base.res_cap = &res_cap_dcn3;
2269
2270         pool->base.funcs = &dcn30_res_pool_funcs;
2271
2272         /*************************************************
2273          *  Resource + asic cap harcoding                *
2274          *************************************************/
2275         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2276         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2277         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2278         dc->caps.max_downscale_ratio = 600;
2279         dc->caps.i2c_speed_in_khz = 100;
2280         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2281         dc->caps.max_cursor_size = 256;
2282         dc->caps.min_horizontal_blanking_period = 80;
2283         dc->caps.dmdata_alloc_size = 2048;
2284         dc->caps.mall_size_per_mem_channel = 8;
2285         /* total size = mall per channel * num channels * 1024 * 1024 */
2286         dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2287         dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2288
2289         dc->caps.max_slave_planes = 2;
2290         dc->caps.max_slave_yuv_planes = 2;
2291         dc->caps.max_slave_rgb_planes = 2;
2292         dc->caps.post_blend_color_processing = true;
2293         dc->caps.force_dp_tps4_for_cp2520 = true;
2294         dc->caps.extended_aux_timeout_support = true;
2295         dc->caps.dmcub_support = true;
2296
2297         /* Color pipeline capabilities */
2298         dc->caps.color.dpp.dcn_arch = 1;
2299         dc->caps.color.dpp.input_lut_shared = 0;
2300         dc->caps.color.dpp.icsc = 1;
2301         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2302         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2303         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2304         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2305         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2306         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2307         dc->caps.color.dpp.post_csc = 1;
2308         dc->caps.color.dpp.gamma_corr = 1;
2309         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2310
2311         dc->caps.color.dpp.hw_3d_lut = 1;
2312         dc->caps.color.dpp.ogam_ram = 1;
2313         // no OGAM ROM on DCN3
2314         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2315         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2316         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2317         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2318         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2319         dc->caps.color.dpp.ocsc = 0;
2320
2321         dc->caps.color.mpc.gamut_remap = 1;
2322         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2323         dc->caps.color.mpc.ogam_ram = 1;
2324         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2325         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2326         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2327         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2328         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2329         dc->caps.color.mpc.ocsc = 1;
2330
2331         dc->caps.dp_hdmi21_pcon_support = true;
2332
2333         /* read VBIOS LTTPR caps */
2334         {
2335                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2336                         enum bp_result bp_query_result;
2337                         uint8_t is_vbios_lttpr_enable = 0;
2338
2339                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2340                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2341                 }
2342
2343                 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2344                         enum bp_result bp_query_result;
2345                         uint8_t is_vbios_interop_enabled = 0;
2346
2347                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2348                                         &is_vbios_interop_enabled);
2349                         dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2350                 }
2351         }
2352
2353         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2354                 dc->debug = debug_defaults_drv;
2355         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2356                 dc->debug = debug_defaults_diags;
2357         } else
2358                 dc->debug = debug_defaults_diags;
2359         // Init the vm_helper
2360         if (dc->vm_helper)
2361                 vm_helper_init(dc->vm_helper, 16);
2362
2363         /*************************************************
2364          *  Create resources                             *
2365          *************************************************/
2366
2367         /* Clock Sources for Pixel Clock*/
2368         pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2369                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2370                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2371                                 &clk_src_regs[0], false);
2372         pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2373                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2374                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2375                                 &clk_src_regs[1], false);
2376         pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2377                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2378                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2379                                 &clk_src_regs[2], false);
2380         pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2381                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2382                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2383                                 &clk_src_regs[3], false);
2384         pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2385                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2386                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2387                                 &clk_src_regs[4], false);
2388         pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2389                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2390                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
2391                                 &clk_src_regs[5], false);
2392
2393         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2394
2395         /* todo: not reuse phy_pll registers */
2396         pool->base.dp_clock_source =
2397                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2398                                 CLOCK_SOURCE_ID_DP_DTO,
2399                                 &clk_src_regs[0], true);
2400
2401         for (i = 0; i < pool->base.clk_src_count; i++) {
2402                 if (pool->base.clock_sources[i] == NULL) {
2403                         dm_error("DC: failed to create clock sources!\n");
2404                         BREAK_TO_DEBUGGER();
2405                         goto create_fail;
2406                 }
2407         }
2408
2409         /* DCCG */
2410         pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2411         if (pool->base.dccg == NULL) {
2412                 dm_error("DC: failed to create dccg!\n");
2413                 BREAK_TO_DEBUGGER();
2414                 goto create_fail;
2415         }
2416
2417         /* PP Lib and SMU interfaces */
2418         init_soc_bounding_box(dc, pool);
2419
2420         num_pipes = dcn3_0_ip.max_num_dpp;
2421
2422         for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2423                 if (pipe_fuses & 1 << i)
2424                         num_pipes--;
2425
2426         dcn3_0_ip.max_num_dpp = num_pipes;
2427         dcn3_0_ip.max_num_otg = num_pipes;
2428
2429         dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2430
2431         /* IRQ */
2432         init_data.ctx = dc->ctx;
2433         pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2434         if (!pool->base.irqs)
2435                 goto create_fail;
2436
2437         /* HUBBUB */
2438         pool->base.hubbub = dcn30_hubbub_create(ctx);
2439         if (pool->base.hubbub == NULL) {
2440                 BREAK_TO_DEBUGGER();
2441                 dm_error("DC: failed to create hubbub!\n");
2442                 goto create_fail;
2443         }
2444
2445         /* HUBPs, DPPs, OPPs and TGs */
2446         for (i = 0; i < pool->base.pipe_count; i++) {
2447                 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2448                 if (pool->base.hubps[i] == NULL) {
2449                         BREAK_TO_DEBUGGER();
2450                         dm_error(
2451                                 "DC: failed to create hubps!\n");
2452                         goto create_fail;
2453                 }
2454
2455                 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2456                 if (pool->base.dpps[i] == NULL) {
2457                         BREAK_TO_DEBUGGER();
2458                         dm_error(
2459                                 "DC: failed to create dpps!\n");
2460                         goto create_fail;
2461                 }
2462         }
2463
2464         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2465                 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2466                 if (pool->base.opps[i] == NULL) {
2467                         BREAK_TO_DEBUGGER();
2468                         dm_error(
2469                                 "DC: failed to create output pixel processor!\n");
2470                         goto create_fail;
2471                 }
2472         }
2473
2474         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2475                 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2476                                 ctx, i);
2477                 if (pool->base.timing_generators[i] == NULL) {
2478                         BREAK_TO_DEBUGGER();
2479                         dm_error("DC: failed to create tg!\n");
2480                         goto create_fail;
2481                 }
2482         }
2483         pool->base.timing_generator_count = i;
2484         /* PSR */
2485         pool->base.psr = dmub_psr_create(ctx);
2486
2487         if (pool->base.psr == NULL) {
2488                 dm_error("DC: failed to create PSR obj!\n");
2489                 BREAK_TO_DEBUGGER();
2490                 goto create_fail;
2491         }
2492
2493         /* ABM */
2494         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2495                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2496                                 &abm_regs[i],
2497                                 &abm_shift,
2498                                 &abm_mask);
2499                 if (pool->base.multiple_abms[i] == NULL) {
2500                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2501                         BREAK_TO_DEBUGGER();
2502                         goto create_fail;
2503                 }
2504         }
2505         /* MPC and DSC */
2506         pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2507         if (pool->base.mpc == NULL) {
2508                 BREAK_TO_DEBUGGER();
2509                 dm_error("DC: failed to create mpc!\n");
2510                 goto create_fail;
2511         }
2512
2513         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2514                 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2515                 if (pool->base.dscs[i] == NULL) {
2516                         BREAK_TO_DEBUGGER();
2517                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2518                         goto create_fail;
2519                 }
2520         }
2521
2522         /* DWB and MMHUBBUB */
2523         if (!dcn30_dwbc_create(ctx, &pool->base)) {
2524                 BREAK_TO_DEBUGGER();
2525                 dm_error("DC: failed to create dwbc!\n");
2526                 goto create_fail;
2527         }
2528
2529         if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2530                 BREAK_TO_DEBUGGER();
2531                 dm_error("DC: failed to create mcif_wb!\n");
2532                 goto create_fail;
2533         }
2534
2535         /* AUX and I2C */
2536         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2537                 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2538                 if (pool->base.engines[i] == NULL) {
2539                         BREAK_TO_DEBUGGER();
2540                         dm_error(
2541                                 "DC:failed to create aux engine!!\n");
2542                         goto create_fail;
2543                 }
2544                 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2545                 if (pool->base.hw_i2cs[i] == NULL) {
2546                         BREAK_TO_DEBUGGER();
2547                         dm_error(
2548                                 "DC:failed to create hw i2c!!\n");
2549                         goto create_fail;
2550                 }
2551                 pool->base.sw_i2cs[i] = NULL;
2552         }
2553
2554         /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2555         if (!resource_construct(num_virtual_links, dc, &pool->base,
2556                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2557                         &res_create_funcs : &res_create_maximus_funcs)))
2558                 goto create_fail;
2559
2560         /* HW Sequencer and Plane caps */
2561         dcn30_hw_sequencer_construct(dc);
2562
2563         dc->caps.max_planes =  pool->base.pipe_count;
2564
2565         for (i = 0; i < dc->caps.max_planes; ++i)
2566                 dc->caps.planes[i] = plane_cap;
2567
2568         dc->cap_funcs = cap_funcs;
2569
2570         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2571                 ddc_init_data.ctx = dc->ctx;
2572                 ddc_init_data.link = NULL;
2573                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2574                 ddc_init_data.id.enum_id = 0;
2575                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2576                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2577         } else {
2578                 pool->base.oem_device = NULL;
2579         }
2580
2581         DC_FP_END();
2582
2583         return true;
2584
2585 create_fail:
2586
2587         DC_FP_END();
2588         dcn30_resource_destruct(pool);
2589
2590         return false;
2591 }
2592
2593 struct resource_pool *dcn30_create_resource_pool(
2594                 const struct dc_init_data *init_data,
2595                 struct dc *dc)
2596 {
2597         struct dcn30_resource_pool *pool =
2598                 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2599
2600         if (!pool)
2601                 return NULL;
2602
2603         if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2604                 return &pool->base;
2605
2606         BREAK_TO_DEBUGGER();
2607         kfree(pool);
2608         return NULL;
2609 }