drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

   1 /*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn21_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn21/dcn21_resource.h"
  38
  39 #include "dml/dcn20/dcn20_fpu.h"
  40
  41 #include "clk_mgr.h"
  42 #include "dcn10/dcn10_hubp.h"
  43 #include "dcn10/dcn10_ipp.h"
  44 #include "dcn20/dcn20_hubbub.h"
  45 #include "dcn20/dcn20_mpc.h"
  46 #include "dcn20/dcn20_hubp.h"
  47 #include "dcn21_hubp.h"
  48 #include "irq/dcn21/irq_service_dcn21.h"
  49 #include "dcn20/dcn20_dpp.h"
  50 #include "dcn20/dcn20_optc.h"
  51 #include "dcn21/dcn21_hwseq.h"
  52 #include "dce110/dce110_hw_sequencer.h"
  53 #include "dcn20/dcn20_opp.h"
  54 #include "dcn20/dcn20_dsc.h"
  55 #include "dcn21/dcn21_link_encoder.h"
  56 #include "dcn20/dcn20_stream_encoder.h"
  57 #include "dce/dce_clock_source.h"
  58 #include "dce/dce_audio.h"
  59 #include "dce/dce_hwseq.h"
  60 #include "virtual/virtual_stream_encoder.h"
  61 #include "dml/display_mode_vba.h"
  62 #include "dcn20/dcn20_dccg.h"
  63 #include "dcn21/dcn21_dccg.h"
  64 #include "dcn21_hubbub.h"
  65 #include "dcn10/dcn10_resource.h"
  66 #include "dce/dce_panel_cntl.h"
  67
  68 #include "dcn20/dcn20_dwb.h"
  69 #include "dcn20/dcn20_mmhubbub.h"
  70 #include "dpcs/dpcs_2_1_0_offset.h"
  71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
  72
  73 #include "renoir_ip_offset.h"
  74 #include "dcn/dcn_2_1_0_offset.h"
  75 #include "dcn/dcn_2_1_0_sh_mask.h"
  76
  77 #include "nbio/nbio_7_0_offset.h"
  78
  79 #include "mmhub/mmhub_2_0_0_offset.h"
  80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  81
  82 #include "reg_helper.h"
  83 #include "dce/dce_abm.h"
  84 #include "dce/dce_dmcu.h"
  85 #include "dce/dce_aux.h"
  86 #include "dce/dce_i2c.h"
  87 #include "dcn21_resource.h"
  88 #include "vm_helper.h"
  89 #include "dcn20/dcn20_vmid.h"
  90 #include "dce/dmub_psr.h"
  91 #include "dce/dmub_abm.h"
  92
  93 /* begin *********************
  94  * macros to expend register list macro defined in HW object header file */
  95
  96 /* DCN */
  97 /* TODO awful hack. fixup dcn20_dwb.h */
  98 #undef BASE_INNER
  99 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 100
 101 #define BASE(seg) BASE_INNER(seg)
 102
 103 #define SR(reg_name)\
 104                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 105                                         mm ## reg_name
 106
 107 #define SRI(reg_name, block, id)\
 108         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 109                                         mm ## block ## id ## _ ## reg_name
 110
 111 #define SRIR(var_name, reg_name, block, id)\
 112         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 113                                         mm ## block ## id ## _ ## reg_name
 114
 115 #define SRII(reg_name, block, id)\
 116         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 117                                         mm ## block ## id ## _ ## reg_name
 118
 119 #define DCCG_SRII(reg_name, block, id)\
 120         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 121                                         mm ## block ## id ## _ ## reg_name
 122
 123 #define VUPDATE_SRII(reg_name, block, id)\
 124         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 125                                         mm ## reg_name ## _ ## block ## id
 126
 127 /* NBIO */
 128 #define NBIO_BASE_INNER(seg) \
 129         NBIF0_BASE__INST0_SEG ## seg
 130
 131 #define NBIO_BASE(seg) \
 132         NBIO_BASE_INNER(seg)
 133
 134 #define NBIO_SR(reg_name)\
 135                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 136                                         mm ## reg_name
 137
 138 /* MMHUB */
 139 #define MMHUB_BASE_INNER(seg) \
 140         MMHUB_BASE__INST0_SEG ## seg
 141
 142 #define MMHUB_BASE(seg) \
 143         MMHUB_BASE_INNER(seg)
 144
 145 #define MMHUB_SR(reg_name)\
 146                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 147                                         mmMM ## reg_name
 148
 149 #define clk_src_regs(index, pllid)\
 150 [index] = {\
 151         CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
 152 }
 153
 154 static const struct dce110_clk_src_regs clk_src_regs[] = {
 155         clk_src_regs(0, A),
 156         clk_src_regs(1, B),
 157         clk_src_regs(2, C),
 158         clk_src_regs(3, D),
 159         clk_src_regs(4, E),
 160 };
 161
 162 static const struct dce110_clk_src_shift cs_shift = {
 163                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 164 };
 165
 166 static const struct dce110_clk_src_mask cs_mask = {
 167                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 168 };
 169
 170 static const struct bios_registers bios_regs = {
 171                 NBIO_SR(BIOS_SCRATCH_3),
 172                 NBIO_SR(BIOS_SCRATCH_6)
 173 };
 174
 175 static const struct dce_dmcu_registers dmcu_regs = {
 176                 DMCU_DCN20_REG_LIST()
 177 };
 178
 179 static const struct dce_dmcu_shift dmcu_shift = {
 180                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 181 };
 182
 183 static const struct dce_dmcu_mask dmcu_mask = {
 184                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 185 };
 186
 187 static const struct dce_abm_registers abm_regs = {
 188                 ABM_DCN20_REG_LIST()
 189 };
 190
 191 static const struct dce_abm_shift abm_shift = {
 192                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 193 };
 194
 195 static const struct dce_abm_mask abm_mask = {
 196                 ABM_MASK_SH_LIST_DCN20(_MASK)
 197 };
 198
 199 #define audio_regs(id)\
 200 [id] = {\
 201                 AUD_COMMON_REG_LIST(id)\
 202 }
 203
 204 static const struct dce_audio_registers audio_regs[] = {
 205         audio_regs(0),
 206         audio_regs(1),
 207         audio_regs(2),
 208         audio_regs(3),
 209         audio_regs(4),
 210         audio_regs(5),
 211 };
 212
 213 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 214                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 215                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 216                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 217
 218 static const struct dce_audio_shift audio_shift = {
 219                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 220 };
 221
 222 static const struct dce_audio_mask audio_mask = {
 223                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 224 };
 225
 226 static const struct dccg_registers dccg_regs = {
 227                 DCCG_COMMON_REG_LIST_DCN_BASE()
 228 };
 229
 230 static const struct dccg_shift dccg_shift = {
 231                 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
 232 };
 233
 234 static const struct dccg_mask dccg_mask = {
 235                 DCCG_MASK_SH_LIST_DCN2_1(_MASK)
 236 };
 237
 238 #define opp_regs(id)\
 239 [id] = {\
 240         OPP_REG_LIST_DCN20(id),\
 241 }
 242
 243 static const struct dcn20_opp_registers opp_regs[] = {
 244         opp_regs(0),
 245         opp_regs(1),
 246         opp_regs(2),
 247         opp_regs(3),
 248         opp_regs(4),
 249         opp_regs(5),
 250 };
 251
 252 static const struct dcn20_opp_shift opp_shift = {
 253                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 254 };
 255
 256 static const struct dcn20_opp_mask opp_mask = {
 257                 OPP_MASK_SH_LIST_DCN20(_MASK)
 258 };
 259
 260 #define tg_regs(id)\
 261 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 262
 263 static const struct dcn_optc_registers tg_regs[] = {
 264         tg_regs(0),
 265         tg_regs(1),
 266         tg_regs(2),
 267         tg_regs(3)
 268 };
 269
 270 static const struct dcn_optc_shift tg_shift = {
 271         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 272 };
 273
 274 static const struct dcn_optc_mask tg_mask = {
 275         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 276 };
 277
 278 static const struct dcn20_mpc_registers mpc_regs = {
 279                 MPC_REG_LIST_DCN2_0(0),
 280                 MPC_REG_LIST_DCN2_0(1),
 281                 MPC_REG_LIST_DCN2_0(2),
 282                 MPC_REG_LIST_DCN2_0(3),
 283                 MPC_REG_LIST_DCN2_0(4),
 284                 MPC_REG_LIST_DCN2_0(5),
 285                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 286                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 287                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 288                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 289                 MPC_DBG_REG_LIST_DCN2_0()
 290 };
 291
 292 static const struct dcn20_mpc_shift mpc_shift = {
 293         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 294         MPC_DEBUG_REG_LIST_SH_DCN20
 295 };
 296
 297 static const struct dcn20_mpc_mask mpc_mask = {
 298         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 299         MPC_DEBUG_REG_LIST_MASK_DCN20
 300 };
 301
 302 #define hubp_regs(id)\
 303 [id] = {\
 304         HUBP_REG_LIST_DCN21(id)\
 305 }
 306
 307 static const struct dcn_hubp2_registers hubp_regs[] = {
 308                 hubp_regs(0),
 309                 hubp_regs(1),
 310                 hubp_regs(2),
 311                 hubp_regs(3)
 312 };
 313
 314 static const struct dcn_hubp2_shift hubp_shift = {
 315                 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
 316 };
 317
 318 static const struct dcn_hubp2_mask hubp_mask = {
 319                 HUBP_MASK_SH_LIST_DCN21(_MASK)
 320 };
 321
 322 static const struct dcn_hubbub_registers hubbub_reg = {
 323                 HUBBUB_REG_LIST_DCN21()
 324 };
 325
 326 static const struct dcn_hubbub_shift hubbub_shift = {
 327                 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
 328 };
 329
 330 static const struct dcn_hubbub_mask hubbub_mask = {
 331                 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
 332 };
 333
 334
 335 #define vmid_regs(id)\
 336 [id] = {\
 337                 DCN20_VMID_REG_LIST(id)\
 338 }
 339
 340 static const struct dcn_vmid_registers vmid_regs[] = {
 341         vmid_regs(0),
 342         vmid_regs(1),
 343         vmid_regs(2),
 344         vmid_regs(3),
 345         vmid_regs(4),
 346         vmid_regs(5),
 347         vmid_regs(6),
 348         vmid_regs(7),
 349         vmid_regs(8),
 350         vmid_regs(9),
 351         vmid_regs(10),
 352         vmid_regs(11),
 353         vmid_regs(12),
 354         vmid_regs(13),
 355         vmid_regs(14),
 356         vmid_regs(15)
 357 };
 358
 359 static const struct dcn20_vmid_shift vmid_shifts = {
 360                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 361 };
 362
 363 static const struct dcn20_vmid_mask vmid_masks = {
 364                 DCN20_VMID_MASK_SH_LIST(_MASK)
 365 };
 366
 367 #define dsc_regsDCN20(id)\
 368 [id] = {\
 369         DSC_REG_LIST_DCN20(id)\
 370 }
 371
 372 static const struct dcn20_dsc_registers dsc_regs[] = {
 373         dsc_regsDCN20(0),
 374         dsc_regsDCN20(1),
 375         dsc_regsDCN20(2),
 376         dsc_regsDCN20(3),
 377         dsc_regsDCN20(4),
 378         dsc_regsDCN20(5)
 379 };
 380
 381 static const struct dcn20_dsc_shift dsc_shift = {
 382         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 383 };
 384
 385 static const struct dcn20_dsc_mask dsc_mask = {
 386         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 387 };
 388
 389 #define ipp_regs(id)\
 390 [id] = {\
 391         IPP_REG_LIST_DCN20(id),\
 392 }
 393
 394 static const struct dcn10_ipp_registers ipp_regs[] = {
 395         ipp_regs(0),
 396         ipp_regs(1),
 397         ipp_regs(2),
 398         ipp_regs(3),
 399 };
 400
 401 static const struct dcn10_ipp_shift ipp_shift = {
 402                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 403 };
 404
 405 static const struct dcn10_ipp_mask ipp_mask = {
 406                 IPP_MASK_SH_LIST_DCN20(_MASK),
 407 };
 408
 409 #define opp_regs(id)\
 410 [id] = {\
 411         OPP_REG_LIST_DCN20(id),\
 412 }
 413
 414
 415 #define aux_engine_regs(id)\
 416 [id] = {\
 417         AUX_COMMON_REG_LIST0(id), \
 418         .AUXN_IMPCAL = 0, \
 419         .AUXP_IMPCAL = 0, \
 420         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 421 }
 422
 423 static const struct dce110_aux_registers aux_engine_regs[] = {
 424                 aux_engine_regs(0),
 425                 aux_engine_regs(1),
 426                 aux_engine_regs(2),
 427                 aux_engine_regs(3),
 428                 aux_engine_regs(4),
 429 };
 430
 431 #define tf_regs(id)\
 432 [id] = {\
 433         TF_REG_LIST_DCN20(id),\
 434         TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 435 }
 436
 437 static const struct dcn2_dpp_registers tf_regs[] = {
 438         tf_regs(0),
 439         tf_regs(1),
 440         tf_regs(2),
 441         tf_regs(3),
 442 };
 443
 444 static const struct dcn2_dpp_shift tf_shift = {
 445                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 446                 TF_DEBUG_REG_LIST_SH_DCN20
 447 };
 448
 449 static const struct dcn2_dpp_mask tf_mask = {
 450                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 451                 TF_DEBUG_REG_LIST_MASK_DCN20
 452 };
 453
 454 #define stream_enc_regs(id)\
 455 [id] = {\
 456         SE_DCN2_REG_LIST(id)\
 457 }
 458
 459 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 460         stream_enc_regs(0),
 461         stream_enc_regs(1),
 462         stream_enc_regs(2),
 463         stream_enc_regs(3),
 464         stream_enc_regs(4),
 465 };
 466
 467 static const struct dce110_aux_registers_shift aux_shift = {
 468         DCN_AUX_MASK_SH_LIST(__SHIFT)
 469 };
 470
 471 static const struct dce110_aux_registers_mask aux_mask = {
 472         DCN_AUX_MASK_SH_LIST(_MASK)
 473 };
 474
 475 static const struct dcn10_stream_encoder_shift se_shift = {
 476                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 477 };
 478
 479 static const struct dcn10_stream_encoder_mask se_mask = {
 480                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 481 };
 482
 483 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
 484
 485 static struct input_pixel_processor *dcn21_ipp_create(
 486         struct dc_context *ctx, uint32_t inst)
 487 {
 488         struct dcn10_ipp *ipp =
 489                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 490
 491         if (!ipp) {
 492                 BREAK_TO_DEBUGGER();
 493                 return NULL;
 494         }
 495
 496         dcn20_ipp_construct(ipp, ctx, inst,
 497                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 498         return &ipp->base;
 499 }
 500
 501 static struct dpp *dcn21_dpp_create(
 502         struct dc_context *ctx,
 503         uint32_t inst)
 504 {
 505         struct dcn20_dpp *dpp =
 506                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 507
 508         if (!dpp)
 509                 return NULL;
 510
 511         if (dpp2_construct(dpp, ctx, inst,
 512                         &tf_regs[inst], &tf_shift, &tf_mask))
 513                 return &dpp->base;
 514
 515         BREAK_TO_DEBUGGER();
 516         kfree(dpp);
 517         return NULL;
 518 }
 519
 520 static struct dce_aux *dcn21_aux_engine_create(
 521         struct dc_context *ctx,
 522         uint32_t inst)
 523 {
 524         struct aux_engine_dce110 *aux_engine =
 525                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 526
 527         if (!aux_engine)
 528                 return NULL;
 529
 530         dce110_aux_engine_construct(aux_engine, ctx, inst,
 531                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 532                                     &aux_engine_regs[inst],
 533                                         &aux_mask,
 534                                         &aux_shift,
 535                                         ctx->dc->caps.extended_aux_timeout_support);
 536
 537         return &aux_engine->base;
 538 }
 539
 540 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 541
 542 static const struct dce_i2c_registers i2c_hw_regs[] = {
 543                 i2c_inst_regs(1),
 544                 i2c_inst_regs(2),
 545                 i2c_inst_regs(3),
 546                 i2c_inst_regs(4),
 547                 i2c_inst_regs(5),
 548 };
 549
 550 static const struct dce_i2c_shift i2c_shifts = {
 551                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 552 };
 553
 554 static const struct dce_i2c_mask i2c_masks = {
 555                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 556 };
 557
 558 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
 559                                               uint32_t inst)
 560 {
 561         struct dce_i2c_hw *dce_i2c_hw =
 562                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 563
 564         if (!dce_i2c_hw)
 565                 return NULL;
 566
 567         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 568                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 569
 570         return dce_i2c_hw;
 571 }
 572
 573 static const struct resource_caps res_cap_rn = {
 574                 .num_timing_generator = 4,
 575                 .num_opp = 4,
 576                 .num_video_plane = 4,
 577                 .num_audio = 4, // 4 audio endpoints.  4 audio streams
 578                 .num_stream_encoder = 5,
 579                 .num_pll = 5,  // maybe 3 because the last two used for USB-c
 580                 .num_dwb = 1,
 581                 .num_ddc = 5,
 582                 .num_vmid = 16,
 583                 .num_dsc = 3,
 584 };
 585
 586 #ifdef DIAGS_BUILD
 587 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
 588                 .num_timing_generator = 4,
 589                 .num_opp = 4,
 590                 .num_video_plane = 4,
 591                 .num_audio = 7,
 592                 .num_stream_encoder = 4,
 593                 .num_pll = 4,
 594                 .num_dwb = 1,
 595                 .num_ddc = 4,
 596                 .num_dsc = 0,
 597 };
 598
 599 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
 600                 .num_timing_generator = 2,
 601                 .num_opp = 2,
 602                 .num_video_plane = 2,
 603                 .num_audio = 7,
 604                 .num_stream_encoder = 2,
 605                 .num_pll = 4,
 606                 .num_dwb = 1,
 607                 .num_ddc = 4,
 608                 .num_dsc = 2,
 609 };
 610 #endif
 611
 612 static const struct dc_plane_cap plane_cap = {
 613         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 614         .blends_with_above = true,
 615         .blends_with_below = true,
 616         .per_pixel_alpha = true,
 617
 618         .pixel_format_support = {
 619                         .argb8888 = true,
 620                         .nv12 = true,
 621                         .fp16 = true,
 622                         .p010 = true
 623         },
 624
 625         .max_upscale_factor = {
 626                         .argb8888 = 16000,
 627                         .nv12 = 16000,
 628                         .fp16 = 16000
 629         },
 630
 631         .max_downscale_factor = {
 632                         .argb8888 = 250,
 633                         .nv12 = 250,
 634                         .fp16 = 250
 635         },
 636         64,
 637         64
 638 };
 639
 640 static const struct dc_debug_options debug_defaults_drv = {
 641                 .disable_dmcu = false,
 642                 .force_abm_enable = false,
 643                 .timing_trace = false,
 644                 .clock_trace = true,
 645                 .disable_pplib_clock_request = true,
 646                 .min_disp_clk_khz = 100000,
 647                 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 648                 .force_single_disp_pipe_split = false,
 649                 .disable_dcc = DCC_ENABLE,
 650                 .vsr_support = true,
 651                 .performance_trace = false,
 652                 .max_downscale_src_width = 4096,
 653                 .disable_pplib_wm_range = false,
 654                 .scl_reset_length10 = true,
 655                 .sanity_checks = true,
 656                 .disable_48mhz_pwrdwn = false,
 657                 .usbc_combo_phy_reset_wa = true,
 658                 .dmub_command_table = true,
 659                 .use_max_lb = true,
 660 };
 661
 662 static const struct dc_debug_options debug_defaults_diags = {
 663                 .disable_dmcu = false,
 664                 .force_abm_enable = false,
 665                 .timing_trace = true,
 666                 .clock_trace = true,
 667                 .disable_dpp_power_gate = true,
 668                 .disable_hubp_power_gate = true,
 669                 .disable_clock_gate = true,
 670                 .disable_pplib_clock_request = true,
 671                 .disable_pplib_wm_range = true,
 672                 .disable_stutter = true,
 673                 .disable_48mhz_pwrdwn = true,
 674                 .disable_psr = true,
 675                 .enable_tri_buf = true,
 676                 .use_max_lb = true
 677 };
 678
 679 static const struct dc_panel_config panel_config_defaults = {
 680                 .ilr = {
 681                         .optimize_edp_link_rate = true,
 682                 },
 683 };
 684
 685 enum dcn20_clk_src_array_id {
 686         DCN20_CLK_SRC_PLL0,
 687         DCN20_CLK_SRC_PLL1,
 688         DCN20_CLK_SRC_PLL2,
 689         DCN20_CLK_SRC_PLL3,
 690         DCN20_CLK_SRC_PLL4,
 691         DCN20_CLK_SRC_TOTAL_DCN21
 692 };
 693
 694 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
 695 {
 696         unsigned int i;
 697
 698         for (i = 0; i < pool->base.stream_enc_count; i++) {
 699                 if (pool->base.stream_enc[i] != NULL) {
 700                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 701                         pool->base.stream_enc[i] = NULL;
 702                 }
 703         }
 704
 705         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
 706                 if (pool->base.dscs[i] != NULL)
 707                         dcn20_dsc_destroy(&pool->base.dscs[i]);
 708         }
 709
 710         if (pool->base.mpc != NULL) {
 711                 kfree(TO_DCN20_MPC(pool->base.mpc));
 712                 pool->base.mpc = NULL;
 713         }
 714         if (pool->base.hubbub != NULL) {
 715                 kfree(pool->base.hubbub);
 716                 pool->base.hubbub = NULL;
 717         }
 718         for (i = 0; i < pool->base.pipe_count; i++) {
 719                 if (pool->base.dpps[i] != NULL)
 720                         dcn20_dpp_destroy(&pool->base.dpps[i]);
 721
 722                 if (pool->base.ipps[i] != NULL)
 723                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 724
 725                 if (pool->base.hubps[i] != NULL) {
 726                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
 727                         pool->base.hubps[i] = NULL;
 728                 }
 729
 730                 if (pool->base.irqs != NULL) {
 731                         dal_irq_service_destroy(&pool->base.irqs);
 732                 }
 733         }
 734
 735         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 736                 if (pool->base.engines[i] != NULL)
 737                         dce110_engine_destroy(&pool->base.engines[i]);
 738                 if (pool->base.hw_i2cs[i] != NULL) {
 739                         kfree(pool->base.hw_i2cs[i]);
 740                         pool->base.hw_i2cs[i] = NULL;
 741                 }
 742                 if (pool->base.sw_i2cs[i] != NULL) {
 743                         kfree(pool->base.sw_i2cs[i]);
 744                         pool->base.sw_i2cs[i] = NULL;
 745                 }
 746         }
 747
 748         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 749                 if (pool->base.opps[i] != NULL)
 750                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 751         }
 752
 753         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 754                 if (pool->base.timing_generators[i] != NULL)    {
 755                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 756                         pool->base.timing_generators[i] = NULL;
 757                 }
 758         }
 759
 760         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
 761                 if (pool->base.dwbc[i] != NULL) {
 762                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
 763                         pool->base.dwbc[i] = NULL;
 764                 }
 765                 if (pool->base.mcif_wb[i] != NULL) {
 766                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
 767                         pool->base.mcif_wb[i] = NULL;
 768                 }
 769         }
 770
 771         for (i = 0; i < pool->base.audio_count; i++) {
 772                 if (pool->base.audios[i])
 773                         dce_aud_destroy(&pool->base.audios[i]);
 774         }
 775
 776         for (i = 0; i < pool->base.clk_src_count; i++) {
 777                 if (pool->base.clock_sources[i] != NULL) {
 778                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
 779                         pool->base.clock_sources[i] = NULL;
 780                 }
 781         }
 782
 783         if (pool->base.dp_clock_source != NULL) {
 784                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
 785                 pool->base.dp_clock_source = NULL;
 786         }
 787
 788         if (pool->base.abm != NULL) {
 789                 if (pool->base.abm->ctx->dc->config.disable_dmcu)
 790                         dmub_abm_destroy(&pool->base.abm);
 791                 else
 792                         dce_abm_destroy(&pool->base.abm);
 793         }
 794
 795         if (pool->base.dmcu != NULL)
 796                 dce_dmcu_destroy(&pool->base.dmcu);
 797
 798         if (pool->base.psr != NULL)
 799                 dmub_psr_destroy(&pool->base.psr);
 800
 801         if (pool->base.dccg != NULL)
 802                 dcn_dccg_destroy(&pool->base.dccg);
 803
 804         if (pool->base.pp_smu != NULL)
 805                 dcn21_pp_smu_destroy(&pool->base.pp_smu);
 806 }
 807
 808 bool dcn21_fast_validate_bw(struct dc *dc,
 809                             struct dc_state *context,
 810                             display_e2e_pipe_params_st *pipes,
 811                             int *pipe_cnt_out,
 812                             int *pipe_split_from,
 813                             int *vlevel_out,
 814                             bool fast_validate)
 815 {
 816         bool out = false;
 817         int split[MAX_PIPES] = { 0 };
 818         int pipe_cnt, i, pipe_idx, vlevel;
 819
 820         ASSERT(pipes);
 821         if (!pipes)
 822                 return false;
 823
 824         dcn20_merge_pipes_for_validate(dc, context);
 825
 826         DC_FP_START();
 827         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
 828         DC_FP_END();
 829
 830         *pipe_cnt_out = pipe_cnt;
 831
 832         if (!pipe_cnt) {
 833                 out = true;
 834                 goto validate_out;
 835         }
 836         /*
 837          * DML favors voltage over p-state, but we're more interested in
 838          * supporting p-state over voltage. We can't support p-state in
 839          * prefetch mode > 0 so try capping the prefetch mode to start.
 840          */
 841         context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
 842                                 dm_allow_self_refresh_and_mclk_switch;
 843         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 844
 845         if (vlevel > context->bw_ctx.dml.soc.num_states) {
 846                 /*
 847                  * If mode is unsupported or there's still no p-state support then
 848                  * fall back to favoring voltage.
 849                  *
 850                  * We don't actually support prefetch mode 2, so require that we
 851                  * at least support prefetch mode 1.
 852                  */
 853                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
 854                                         dm_allow_self_refresh;
 855                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 856                 if (vlevel > context->bw_ctx.dml.soc.num_states)
 857                         goto validate_fail;
 858         }
 859
 860         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
 861
 862         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 863                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 864                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
 865                 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 866
 867                 if (!pipe->stream)
 868                         continue;
 869
 870                 /* We only support full screen mpo with ODM */
 871                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
 872                                 && pipe->plane_state && mpo_pipe
 873                                 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
 874                                                 &pipe->plane_res.scl_data.recout,
 875                                                 sizeof(struct rect)) != 0) {
 876                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
 877                         goto validate_fail;
 878                 }
 879                 pipe_idx++;
 880         }
 881
 882         /*initialize pipe_just_split_from to invalid idx*/
 883         for (i = 0; i < MAX_PIPES; i++)
 884                 pipe_split_from[i] = -1;
 885
 886         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
 887                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 888                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
 889
 890                 if (!pipe->stream || pipe_split_from[i] >= 0)
 891                         continue;
 892
 893                 pipe_idx++;
 894
 895                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
 896                         hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
 897                         ASSERT(hsplit_pipe);
 898                         if (!dcn20_split_stream_for_odm(
 899                                         dc, &context->res_ctx,
 900                                         pipe, hsplit_pipe))
 901                                 goto validate_fail;
 902                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
 903                         dcn20_build_mapped_resource(dc, context, pipe->stream);
 904                 }
 905
 906                 if (!pipe->plane_state)
 907                         continue;
 908                 /* Skip 2nd half of already split pipe */
 909                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
 910                         continue;
 911
 912                 if (split[i] == 2) {
 913                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
 914                                 /* pipe not split previously needs split */
 915                                 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
 916                                 ASSERT(hsplit_pipe);
 917                                 if (!hsplit_pipe) {
 918                                         DC_FP_START();
 919                                         dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
 920                                         DC_FP_END();
 921                                         continue;
 922                                 }
 923                                 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
 924                                         if (!dcn20_split_stream_for_odm(
 925                                                         dc, &context->res_ctx,
 926                                                         pipe, hsplit_pipe))
 927                                                 goto validate_fail;
 928                                         dcn20_build_mapped_resource(dc, context, pipe->stream);
 929                                 } else {
 930                                         dcn20_split_stream_for_mpc(
 931                                                         &context->res_ctx, dc->res_pool,
 932                                                         pipe, hsplit_pipe);
 933                                         resource_build_scaling_params(pipe);
 934                                         resource_build_scaling_params(hsplit_pipe);
 935                                 }
 936                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
 937                         }
 938                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
 939                         /* merge should already have been done */
 940                         ASSERT(0);
 941                 }
 942         }
 943         /* Actual dsc count per stream dsc validation*/
 944         if (!dcn20_validate_dsc(dc, context)) {
 945                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
 946                                 DML_FAIL_DSC_VALIDATION_FAILURE;
 947                 goto validate_fail;
 948         }
 949
 950         *vlevel_out = vlevel;
 951
 952         out = true;
 953         goto validate_out;
 954
 955 validate_fail:
 956         out = false;
 957
 958 validate_out:
 959         return out;
 960 }
 961
 962 /*
 963  * Some of the functions further below use the FPU, so we need to wrap this
 964  * with DC_FP_START()/DC_FP_END(). Use the same approach as for
 965  * dcn20_validate_bandwidth in dcn20_resource.c.
 966  */
 967 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
 968                 bool fast_validate)
 969 {
 970         bool voltage_supported;
 971         DC_FP_START();
 972         voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
 973         DC_FP_END();
 974         return voltage_supported;
 975 }
 976
 977 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
 978 {
 979         struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
 980
 981         dcn21_resource_destruct(dcn21_pool);
 982         kfree(dcn21_pool);
 983         *pool = NULL;
 984 }
 985
 986 static struct clock_source *dcn21_clock_source_create(
 987                 struct dc_context *ctx,
 988                 struct dc_bios *bios,
 989                 enum clock_source_id id,
 990                 const struct dce110_clk_src_regs *regs,
 991                 bool dp_clk_src)
 992 {
 993         struct dce110_clk_src *clk_src =
 994                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 995
 996         if (!clk_src)
 997                 return NULL;
 998
 999         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1000                         regs, &cs_shift, &cs_mask)) {
1001                 clk_src->base.dp_clk_src = dp_clk_src;
1002                 return &clk_src->base;
1003         }
1004
1005         kfree(clk_src);
1006         BREAK_TO_DEBUGGER();
1007         return NULL;
1008 }
1009
1010 static struct hubp *dcn21_hubp_create(
1011         struct dc_context *ctx,
1012         uint32_t inst)
1013 {
1014         struct dcn21_hubp *hubp21 =
1015                 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1016
1017         if (!hubp21)
1018                 return NULL;
1019
1020         if (hubp21_construct(hubp21, ctx, inst,
1021                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1022                 return &hubp21->base;
1023
1024         BREAK_TO_DEBUGGER();
1025         kfree(hubp21);
1026         return NULL;
1027 }
1028
1029 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1030 {
1031         int i;
1032
1033         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1034                                           GFP_KERNEL);
1035
1036         if (!hubbub)
1037                 return NULL;
1038
1039         hubbub21_construct(hubbub, ctx,
1040                         &hubbub_reg,
1041                         &hubbub_shift,
1042                         &hubbub_mask);
1043
1044         for (i = 0; i < res_cap_rn.num_vmid; i++) {
1045                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1046
1047                 vmid->ctx = ctx;
1048
1049                 vmid->regs = &vmid_regs[i];
1050                 vmid->shifts = &vmid_shifts;
1051                 vmid->masks = &vmid_masks;
1052         }
1053         hubbub->num_vmid = res_cap_rn.num_vmid;
1054
1055         return &hubbub->base;
1056 }
1057
1058 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1059                                                        uint32_t inst)
1060 {
1061         struct dcn20_opp *opp =
1062                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1063
1064         if (!opp) {
1065                 BREAK_TO_DEBUGGER();
1066                 return NULL;
1067         }
1068
1069         dcn20_opp_construct(opp, ctx, inst,
1070                         &opp_regs[inst], &opp_shift, &opp_mask);
1071         return &opp->base;
1072 }
1073
1074 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1075                                                               uint32_t instance)
1076 {
1077         struct optc *tgn10 =
1078                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1079
1080         if (!tgn10)
1081                 return NULL;
1082
1083         tgn10->base.inst = instance;
1084         tgn10->base.ctx = ctx;
1085
1086         tgn10->tg_regs = &tg_regs[instance];
1087         tgn10->tg_shift = &tg_shift;
1088         tgn10->tg_mask = &tg_mask;
1089
1090         dcn20_timing_generator_init(tgn10);
1091
1092         return &tgn10->base;
1093 }
1094
1095 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1096 {
1097         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1098                                           GFP_KERNEL);
1099
1100         if (!mpc20)
1101                 return NULL;
1102
1103         dcn20_mpc_construct(mpc20, ctx,
1104                         &mpc_regs,
1105                         &mpc_shift,
1106                         &mpc_mask,
1107                         6);
1108
1109         return &mpc20->base;
1110 }
1111
1112 static void read_dce_straps(
1113         struct dc_context *ctx,
1114         struct resource_straps *straps)
1115 {
1116         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1117                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1118
1119 }
1120
1121
1122 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1123                                                           uint32_t inst)
1124 {
1125         struct dcn20_dsc *dsc =
1126                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1127
1128         if (!dsc) {
1129                 BREAK_TO_DEBUGGER();
1130                 return NULL;
1131         }
1132
1133         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1134         return &dsc->base;
1135 }
1136
1137 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1138 {
1139         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1140
1141         if (!pp_smu)
1142                 return pp_smu;
1143
1144         dm_pp_get_funcs(ctx, pp_smu);
1145
1146         if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1147                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1148
1149
1150         return pp_smu;
1151 }
1152
1153 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1154 {
1155         if (pp_smu && *pp_smu) {
1156                 kfree(*pp_smu);
1157                 *pp_smu = NULL;
1158         }
1159 }
1160
1161 static struct audio *dcn21_create_audio(
1162                 struct dc_context *ctx, unsigned int inst)
1163 {
1164         return dce_audio_create(ctx, inst,
1165                         &audio_regs[inst], &audio_shift, &audio_mask);
1166 }
1167
1168 static struct dc_cap_funcs cap_funcs = {
1169         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1170 };
1171
1172 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1173                                                           struct dc_context *ctx)
1174 {
1175         struct dcn10_stream_encoder *enc1 =
1176                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1177
1178         if (!enc1)
1179                 return NULL;
1180
1181         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1182                                         &stream_enc_regs[eng_id],
1183                                         &se_shift, &se_mask);
1184
1185         return &enc1->base;
1186 }
1187
1188 static const struct dce_hwseq_registers hwseq_reg = {
1189                 HWSEQ_DCN21_REG_LIST()
1190 };
1191
1192 static const struct dce_hwseq_shift hwseq_shift = {
1193                 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1194 };
1195
1196 static const struct dce_hwseq_mask hwseq_mask = {
1197                 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1198 };
1199
1200 static struct dce_hwseq *dcn21_hwseq_create(
1201         struct dc_context *ctx)
1202 {
1203         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1204
1205         if (hws) {
1206                 hws->ctx = ctx;
1207                 hws->regs = &hwseq_reg;
1208                 hws->shifts = &hwseq_shift;
1209                 hws->masks = &hwseq_mask;
1210                 hws->wa.DEGVIDCN21 = true;
1211                 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1212         }
1213         return hws;
1214 }
1215
1216 static const struct resource_create_funcs res_create_funcs = {
1217         .read_dce_straps = read_dce_straps,
1218         .create_audio = dcn21_create_audio,
1219         .create_stream_encoder = dcn21_stream_encoder_create,
1220         .create_hwseq = dcn21_hwseq_create,
1221 };
1222
1223 static const struct resource_create_funcs res_create_maximus_funcs = {
1224         .read_dce_straps = NULL,
1225         .create_audio = NULL,
1226         .create_stream_encoder = NULL,
1227         .create_hwseq = dcn21_hwseq_create,
1228 };
1229
1230 static const struct encoder_feature_support link_enc_feature = {
1231                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1232                 .max_hdmi_pixel_clock = 600000,
1233                 .hdmi_ycbcr420_supported = true,
1234                 .dp_ycbcr420_supported = true,
1235                 .fec_supported = true,
1236                 .flags.bits.IS_HBR2_CAPABLE = true,
1237                 .flags.bits.IS_HBR3_CAPABLE = true,
1238                 .flags.bits.IS_TPS3_CAPABLE = true,
1239                 .flags.bits.IS_TPS4_CAPABLE = true
1240 };
1241
1242
1243 #define link_regs(id, phyid)\
1244 [id] = {\
1245         LE_DCN2_REG_LIST(id), \
1246         UNIPHY_DCN2_REG_LIST(phyid), \
1247         DPCS_DCN21_REG_LIST(id), \
1248         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1249 }
1250
1251 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1252         link_regs(0, A),
1253         link_regs(1, B),
1254         link_regs(2, C),
1255         link_regs(3, D),
1256         link_regs(4, E),
1257 };
1258
1259 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1260         { DCN_PANEL_CNTL_REG_LIST() }
1261 };
1262
1263 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1264         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1265 };
1266
1267 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1268         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1269 };
1270
1271 #define aux_regs(id)\
1272 [id] = {\
1273         DCN2_AUX_REG_LIST(id)\
1274 }
1275
1276 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1277                 aux_regs(0),
1278                 aux_regs(1),
1279                 aux_regs(2),
1280                 aux_regs(3),
1281                 aux_regs(4)
1282 };
1283
1284 #define hpd_regs(id)\
1285 [id] = {\
1286         HPD_REG_LIST(id)\
1287 }
1288
1289 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1290                 hpd_regs(0),
1291                 hpd_regs(1),
1292                 hpd_regs(2),
1293                 hpd_regs(3),
1294                 hpd_regs(4)
1295 };
1296
1297 static const struct dcn10_link_enc_shift le_shift = {
1298         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1299         DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1300 };
1301
1302 static const struct dcn10_link_enc_mask le_mask = {
1303         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1304         DPCS_DCN21_MASK_SH_LIST(_MASK)
1305 };
1306
1307 static int map_transmitter_id_to_phy_instance(
1308         enum transmitter transmitter)
1309 {
1310         switch (transmitter) {
1311         case TRANSMITTER_UNIPHY_A:
1312                 return 0;
1313         break;
1314         case TRANSMITTER_UNIPHY_B:
1315                 return 1;
1316         break;
1317         case TRANSMITTER_UNIPHY_C:
1318                 return 2;
1319         break;
1320         case TRANSMITTER_UNIPHY_D:
1321                 return 3;
1322         break;
1323         case TRANSMITTER_UNIPHY_E:
1324                 return 4;
1325         break;
1326         default:
1327                 ASSERT(0);
1328                 return 0;
1329         }
1330 }
1331
1332 static struct link_encoder *dcn21_link_encoder_create(
1333         struct dc_context *ctx,
1334         const struct encoder_init_data *enc_init_data)
1335 {
1336         struct dcn21_link_encoder *enc21 =
1337                 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1338         int link_regs_id;
1339
1340         if (!enc21)
1341                 return NULL;
1342
1343         link_regs_id =
1344                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1345
1346         dcn21_link_encoder_construct(enc21,
1347                                       enc_init_data,
1348                                       &link_enc_feature,
1349                                       &link_enc_regs[link_regs_id],
1350                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1351                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1352                                       &le_shift,
1353                                       &le_mask);
1354
1355         return &enc21->enc10.base;
1356 }
1357
1358 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1359 {
1360         struct dce_panel_cntl *panel_cntl =
1361                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1362
1363         if (!panel_cntl)
1364                 return NULL;
1365
1366         dce_panel_cntl_construct(panel_cntl,
1367                         init_data,
1368                         &panel_cntl_regs[init_data->inst],
1369                         &panel_cntl_shift,
1370                         &panel_cntl_mask);
1371
1372         return &panel_cntl->base;
1373 }
1374
1375 static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
1376 {
1377         *panel_config = panel_config_defaults;
1378 }
1379
1380 #define CTX ctx
1381
1382 #define REG(reg_name) \
1383         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1384
1385 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1386 {
1387         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1388         /* RV1 support max 4 pipes */
1389         value = value & 0xf;
1390         return value;
1391 }
1392
1393 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1394 {
1395         enum dc_status result = DC_OK;
1396
1397         if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1398                 plane_state->dcc.enable = 1;
1399                 /* align to our worst case block width */
1400                 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1401         }
1402         result = dcn20_patch_unknown_plane_state(plane_state);
1403         return result;
1404 }
1405
1406 static const struct resource_funcs dcn21_res_pool_funcs = {
1407         .destroy = dcn21_destroy_resource_pool,
1408         .link_enc_create = dcn21_link_encoder_create,
1409         .panel_cntl_create = dcn21_panel_cntl_create,
1410         .validate_bandwidth = dcn21_validate_bandwidth,
1411         .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1412         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1413         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1414         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1415         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1416         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1417         .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1418         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1419         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1420         .update_bw_bounding_box = dcn21_update_bw_bounding_box,
1421         .get_panel_config_defaults = dcn21_get_panel_config_defaults,
1422 };
1423
1424 static bool dcn21_resource_construct(
1425         uint8_t num_virtual_links,
1426         struct dc *dc,
1427         struct dcn21_resource_pool *pool)
1428 {
1429         int i, j;
1430         struct dc_context *ctx = dc->ctx;
1431         struct irq_service_init_data init_data;
1432         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1433         uint32_t num_pipes;
1434
1435         ctx->dc_bios->regs = &bios_regs;
1436
1437         pool->base.res_cap = &res_cap_rn;
1438 #ifdef DIAGS_BUILD
1439         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1440                 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1441                 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1442 #endif
1443
1444         pool->base.funcs = &dcn21_res_pool_funcs;
1445
1446         /*************************************************
1447          *  Resource + asic cap harcoding                *
1448          *************************************************/
1449         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1450
1451         /* max pipe num for ASIC before check pipe fuses */
1452         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1453
1454         dc->caps.max_downscale_ratio = 200;
1455         dc->caps.i2c_speed_in_khz = 100;
1456         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1457         dc->caps.max_cursor_size = 256;
1458         dc->caps.min_horizontal_blanking_period = 80;
1459         dc->caps.dmdata_alloc_size = 2048;
1460
1461         dc->caps.max_slave_planes = 1;
1462         dc->caps.max_slave_yuv_planes = 1;
1463         dc->caps.max_slave_rgb_planes = 1;
1464         dc->caps.post_blend_color_processing = true;
1465         dc->caps.force_dp_tps4_for_cp2520 = true;
1466         dc->caps.extended_aux_timeout_support = true;
1467         dc->caps.dmcub_support = true;
1468         dc->caps.is_apu = true;
1469
1470         /* Color pipeline capabilities */
1471         dc->caps.color.dpp.dcn_arch = 1;
1472         dc->caps.color.dpp.input_lut_shared = 0;
1473         dc->caps.color.dpp.icsc = 1;
1474         dc->caps.color.dpp.dgam_ram = 1;
1475         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1476         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1477         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1478         dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1479         dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1480         dc->caps.color.dpp.post_csc = 0;
1481         dc->caps.color.dpp.gamma_corr = 0;
1482         dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1483
1484         dc->caps.color.dpp.hw_3d_lut = 1;
1485         dc->caps.color.dpp.ogam_ram = 1;
1486         // no OGAM ROM on DCN2
1487         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1488         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1489         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1490         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1491         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1492         dc->caps.color.dpp.ocsc = 0;
1493
1494         dc->caps.color.mpc.gamut_remap = 0;
1495         dc->caps.color.mpc.num_3dluts = 0;
1496         dc->caps.color.mpc.shared_3d_lut = 0;
1497         dc->caps.color.mpc.ogam_ram = 1;
1498         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1499         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1500         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1501         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1502         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1503         dc->caps.color.mpc.ocsc = 1;
1504
1505         dc->caps.dp_hdmi21_pcon_support = true;
1506
1507         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1508                 dc->debug = debug_defaults_drv;
1509         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1510                 pool->base.pipe_count = 4;
1511                 dc->debug = debug_defaults_diags;
1512         } else
1513                 dc->debug = debug_defaults_diags;
1514
1515         // Init the vm_helper
1516         if (dc->vm_helper)
1517                 vm_helper_init(dc->vm_helper, 16);
1518
1519         /*************************************************
1520          *  Create resources                             *
1521          *************************************************/
1522
1523         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1524                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1525                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1526                                 &clk_src_regs[0], false);
1527         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1528                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1529                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1530                                 &clk_src_regs[1], false);
1531         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1532                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1533                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1534                                 &clk_src_regs[2], false);
1535         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1536                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1537                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1538                                 &clk_src_regs[3], false);
1539         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1540                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1541                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1542                                 &clk_src_regs[4], false);
1543
1544         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1545
1546         /* todo: not reuse phy_pll registers */
1547         pool->base.dp_clock_source =
1548                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1549                                 CLOCK_SOURCE_ID_DP_DTO,
1550                                 &clk_src_regs[0], true);
1551
1552         for (i = 0; i < pool->base.clk_src_count; i++) {
1553                 if (pool->base.clock_sources[i] == NULL) {
1554                         dm_error("DC: failed to create clock sources!\n");
1555                         BREAK_TO_DEBUGGER();
1556                         goto create_fail;
1557                 }
1558         }
1559
1560         pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1561         if (pool->base.dccg == NULL) {
1562                 dm_error("DC: failed to create dccg!\n");
1563                 BREAK_TO_DEBUGGER();
1564                 goto create_fail;
1565         }
1566
1567         if (!dc->config.disable_dmcu) {
1568                 pool->base.dmcu = dcn21_dmcu_create(ctx,
1569                                 &dmcu_regs,
1570                                 &dmcu_shift,
1571                                 &dmcu_mask);
1572                 if (pool->base.dmcu == NULL) {
1573                         dm_error("DC: failed to create dmcu!\n");
1574                         BREAK_TO_DEBUGGER();
1575                         goto create_fail;
1576                 }
1577
1578                 dc->debug.dmub_command_table = false;
1579         }
1580
1581         if (dc->config.disable_dmcu) {
1582                 pool->base.psr = dmub_psr_create(ctx);
1583
1584                 if (pool->base.psr == NULL) {
1585                         dm_error("DC: failed to create psr obj!\n");
1586                         BREAK_TO_DEBUGGER();
1587                         goto create_fail;
1588                 }
1589         }
1590
1591         if (dc->config.disable_dmcu)
1592                 pool->base.abm = dmub_abm_create(ctx,
1593                         &abm_regs,
1594                         &abm_shift,
1595                         &abm_mask);
1596         else
1597                 pool->base.abm = dce_abm_create(ctx,
1598                         &abm_regs,
1599                         &abm_shift,
1600                         &abm_mask);
1601
1602         pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1603
1604         num_pipes = dcn2_1_ip.max_num_dpp;
1605
1606         for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1607                 if (pipe_fuses & 1 << i)
1608                         num_pipes--;
1609         dcn2_1_ip.max_num_dpp = num_pipes;
1610         dcn2_1_ip.max_num_otg = num_pipes;
1611
1612         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1613
1614         init_data.ctx = dc->ctx;
1615         pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1616         if (!pool->base.irqs)
1617                 goto create_fail;
1618
1619         j = 0;
1620         /* mem input -> ipp -> dpp -> opp -> TG */
1621         for (i = 0; i < pool->base.pipe_count; i++) {
1622                 /* if pipe is disabled, skip instance of HW pipe,
1623                  * i.e, skip ASIC register instance
1624                  */
1625                 if ((pipe_fuses & (1 << i)) != 0)
1626                         continue;
1627
1628                 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1629                 if (pool->base.hubps[j] == NULL) {
1630                         BREAK_TO_DEBUGGER();
1631                         dm_error(
1632                                 "DC: failed to create memory input!\n");
1633                         goto create_fail;
1634                 }
1635
1636                 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1637                 if (pool->base.ipps[j] == NULL) {
1638                         BREAK_TO_DEBUGGER();
1639                         dm_error(
1640                                 "DC: failed to create input pixel processor!\n");
1641                         goto create_fail;
1642                 }
1643
1644                 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1645                 if (pool->base.dpps[j] == NULL) {
1646                         BREAK_TO_DEBUGGER();
1647                         dm_error(
1648                                 "DC: failed to create dpps!\n");
1649                         goto create_fail;
1650                 }
1651
1652                 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1653                 if (pool->base.opps[j] == NULL) {
1654                         BREAK_TO_DEBUGGER();
1655                         dm_error(
1656                                 "DC: failed to create output pixel processor!\n");
1657                         goto create_fail;
1658                 }
1659
1660                 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1661                                 ctx, i);
1662                 if (pool->base.timing_generators[j] == NULL) {
1663                         BREAK_TO_DEBUGGER();
1664                         dm_error("DC: failed to create tg!\n");
1665                         goto create_fail;
1666                 }
1667                 j++;
1668         }
1669
1670         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1671                 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1672                 if (pool->base.engines[i] == NULL) {
1673                         BREAK_TO_DEBUGGER();
1674                         dm_error(
1675                                 "DC:failed to create aux engine!!\n");
1676                         goto create_fail;
1677                 }
1678                 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1679                 if (pool->base.hw_i2cs[i] == NULL) {
1680                         BREAK_TO_DEBUGGER();
1681                         dm_error(
1682                                 "DC:failed to create hw i2c!!\n");
1683                         goto create_fail;
1684                 }
1685                 pool->base.sw_i2cs[i] = NULL;
1686         }
1687
1688         pool->base.timing_generator_count = j;
1689         pool->base.pipe_count = j;
1690         pool->base.mpcc_count = j;
1691
1692         pool->base.mpc = dcn21_mpc_create(ctx);
1693         if (pool->base.mpc == NULL) {
1694                 BREAK_TO_DEBUGGER();
1695                 dm_error("DC: failed to create mpc!\n");
1696                 goto create_fail;
1697         }
1698
1699         pool->base.hubbub = dcn21_hubbub_create(ctx);
1700         if (pool->base.hubbub == NULL) {
1701                 BREAK_TO_DEBUGGER();
1702                 dm_error("DC: failed to create hubbub!\n");
1703                 goto create_fail;
1704         }
1705
1706         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1707                 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1708                 if (pool->base.dscs[i] == NULL) {
1709                         BREAK_TO_DEBUGGER();
1710                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1711                         goto create_fail;
1712                 }
1713         }
1714
1715         if (!dcn20_dwbc_create(ctx, &pool->base)) {
1716                 BREAK_TO_DEBUGGER();
1717                 dm_error("DC: failed to create dwbc!\n");
1718                 goto create_fail;
1719         }
1720         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1721                 BREAK_TO_DEBUGGER();
1722                 dm_error("DC: failed to create mcif_wb!\n");
1723                 goto create_fail;
1724         }
1725
1726         if (!resource_construct(num_virtual_links, dc, &pool->base,
1727                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1728                         &res_create_funcs : &res_create_maximus_funcs)))
1729                         goto create_fail;
1730
1731         dcn21_hw_sequencer_construct(dc);
1732
1733         dc->caps.max_planes =  pool->base.pipe_count;
1734
1735         for (i = 0; i < dc->caps.max_planes; ++i)
1736                 dc->caps.planes[i] = plane_cap;
1737
1738         dc->cap_funcs = cap_funcs;
1739
1740         return true;
1741
1742 create_fail:
1743
1744         dcn21_resource_destruct(pool);
1745
1746         return false;
1747 }
1748
1749 struct resource_pool *dcn21_create_resource_pool(
1750                 const struct dc_init_data *init_data,
1751                 struct dc *dc)
1752 {
1753         struct dcn21_resource_pool *pool =
1754                 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1755
1756         if (!pool)
1757                 return NULL;
1758
1759         if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1760                 return &pool->base;
1761
1762         BREAK_TO_DEBUGGER();
1763         kfree(pool);
1764         return NULL;
1765 }