drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28
  29 #include "dcn10_init.h"
  30
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dcn10_resource.h"
  34 #include "dcn10_ipp.h"
  35 #include "dcn10_mpc.h"
  36 #include "irq/dcn10/irq_service_dcn10.h"
  37 #include "dcn10_dpp.h"
  38 #include "dcn10_optc.h"
  39 #include "dcn10_hw_sequencer.h"
  40 #include "dce110/dce110_hw_sequencer.h"
  41 #include "dcn10_opp.h"
  42 #include "dcn10_link_encoder.h"
  43 #include "dcn10_stream_encoder.h"
  44 #include "dce/dce_clock_source.h"
  45 #include "dce/dce_audio.h"
  46 #include "dce/dce_hwseq.h"
  47 #include "virtual/virtual_stream_encoder.h"
  48 #include "dce110/dce110_resource.h"
  49 #include "dce112/dce112_resource.h"
  50 #include "dcn10_hubp.h"
  51 #include "dcn10_hubbub.h"
  52 #include "dce/dce_panel_cntl.h"
  53
  54 #include "soc15_hw_ip.h"
  55 #include "vega10_ip_offset.h"
  56
  57 #include "dcn/dcn_1_0_offset.h"
  58 #include "dcn/dcn_1_0_sh_mask.h"
  59
  60 #include "nbio/nbio_7_0_offset.h"
  61
  62 #include "mmhub/mmhub_9_1_offset.h"
  63 #include "mmhub/mmhub_9_1_sh_mask.h"
  64
  65 #include "reg_helper.h"
  66 #include "dce/dce_abm.h"
  67 #include "dce/dce_dmcu.h"
  68 #include "dce/dce_aux.h"
  69 #include "dce/dce_i2c.h"
  70
  71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
  72         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
  73         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  74         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
  75         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  76         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
  77         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  78         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
  79         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  80         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
  81         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  82         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
  83         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  84         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
  85         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
  86 #endif
  87
  88
  89 enum dcn10_clk_src_array_id {
  90         DCN10_CLK_SRC_PLL0,
  91         DCN10_CLK_SRC_PLL1,
  92         DCN10_CLK_SRC_PLL2,
  93         DCN10_CLK_SRC_PLL3,
  94         DCN10_CLK_SRC_TOTAL,
  95         DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
  96 };
  97
  98 /* begin *********************
  99  * macros to expend register list macro defined in HW object header file */
 100
 101 /* DCN */
 102 #define BASE_INNER(seg) \
 103         DCE_BASE__INST0_SEG ## seg
 104
 105 #define BASE(seg) \
 106         BASE_INNER(seg)
 107
 108 #define SR(reg_name)\
 109                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 110                                         mm ## reg_name
 111
 112 #define SRI(reg_name, block, id)\
 113         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 114                                         mm ## block ## id ## _ ## reg_name
 115
 116
 117 #define SRII(reg_name, block, id)\
 118         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 119                                         mm ## block ## id ## _ ## reg_name
 120
 121 #define VUPDATE_SRII(reg_name, block, id)\
 122         .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
 123                                         mm ## reg_name ## 0 ## _ ## block ## id
 124
 125 /* set field/register/bitfield name */
 126 #define SFRB(field_name, reg_name, bitfield, post_fix)\
 127         .field_name = reg_name ## __ ## bitfield ## post_fix
 128
 129 /* NBIO */
 130 #define NBIO_BASE_INNER(seg) \
 131         NBIF_BASE__INST0_SEG ## seg
 132
 133 #define NBIO_BASE(seg) \
 134         NBIO_BASE_INNER(seg)
 135
 136 #define NBIO_SR(reg_name)\
 137                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
 138                                         mm ## reg_name
 139
 140 /* MMHUB */
 141 #define MMHUB_BASE_INNER(seg) \
 142         MMHUB_BASE__INST0_SEG ## seg
 143
 144 #define MMHUB_BASE(seg) \
 145         MMHUB_BASE_INNER(seg)
 146
 147 #define MMHUB_SR(reg_name)\
 148                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
 149                                         mm ## reg_name
 150
 151 /* macros to expend register list macro defined in HW object header file
 152  * end *********************/
 153
 154
 155 static const struct dce_dmcu_registers dmcu_regs = {
 156                 DMCU_DCN10_REG_LIST()
 157 };
 158
 159 static const struct dce_dmcu_shift dmcu_shift = {
 160                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 161 };
 162
 163 static const struct dce_dmcu_mask dmcu_mask = {
 164                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 165 };
 166
 167 static const struct dce_abm_registers abm_regs = {
 168                 ABM_DCN10_REG_LIST(0)
 169 };
 170
 171 static const struct dce_abm_shift abm_shift = {
 172                 ABM_MASK_SH_LIST_DCN10(__SHIFT)
 173 };
 174
 175 static const struct dce_abm_mask abm_mask = {
 176                 ABM_MASK_SH_LIST_DCN10(_MASK)
 177 };
 178
 179 #define stream_enc_regs(id)\
 180 [id] = {\
 181         SE_DCN_REG_LIST(id)\
 182 }
 183
 184 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 185         stream_enc_regs(0),
 186         stream_enc_regs(1),
 187         stream_enc_regs(2),
 188         stream_enc_regs(3),
 189 };
 190
 191 static const struct dcn10_stream_encoder_shift se_shift = {
 192                 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
 193 };
 194
 195 static const struct dcn10_stream_encoder_mask se_mask = {
 196                 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
 197 };
 198
 199 #define audio_regs(id)\
 200 [id] = {\
 201                 AUD_COMMON_REG_LIST(id)\
 202 }
 203
 204 static const struct dce_audio_registers audio_regs[] = {
 205         audio_regs(0),
 206         audio_regs(1),
 207         audio_regs(2),
 208         audio_regs(3),
 209 };
 210
 211 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 212                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 213                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 214                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 215
 216 static const struct dce_audio_shift audio_shift = {
 217                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 218 };
 219
 220 static const struct dce_audio_mask audio_mask = {
 221                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 222 };
 223
 224 #define aux_regs(id)\
 225 [id] = {\
 226         AUX_REG_LIST(id)\
 227 }
 228
 229 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 230                 aux_regs(0),
 231                 aux_regs(1),
 232                 aux_regs(2),
 233                 aux_regs(3)
 234 };
 235
 236 #define hpd_regs(id)\
 237 [id] = {\
 238         HPD_REG_LIST(id)\
 239 }
 240
 241 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 242                 hpd_regs(0),
 243                 hpd_regs(1),
 244                 hpd_regs(2),
 245                 hpd_regs(3)
 246 };
 247
 248 #define link_regs(id)\
 249 [id] = {\
 250         LE_DCN10_REG_LIST(id), \
 251         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 252 }
 253
 254 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 255         link_regs(0),
 256         link_regs(1),
 257         link_regs(2),
 258         link_regs(3)
 259 };
 260
 261 static const struct dcn10_link_enc_shift le_shift = {
 262                 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
 263 };
 264
 265 static const struct dcn10_link_enc_mask le_mask = {
 266                 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
 267 };
 268
 269 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 270         { DCN_PANEL_CNTL_REG_LIST() }
 271 };
 272
 273 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 274         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 275 };
 276
 277 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 278         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 279 };
 280
 281 static const struct dce110_aux_registers_shift aux_shift = {
 282         DCN10_AUX_MASK_SH_LIST(__SHIFT)
 283 };
 284
 285 static const struct dce110_aux_registers_mask aux_mask = {
 286         DCN10_AUX_MASK_SH_LIST(_MASK)
 287 };
 288
 289 #define ipp_regs(id)\
 290 [id] = {\
 291         IPP_REG_LIST_DCN10(id),\
 292 }
 293
 294 static const struct dcn10_ipp_registers ipp_regs[] = {
 295         ipp_regs(0),
 296         ipp_regs(1),
 297         ipp_regs(2),
 298         ipp_regs(3),
 299 };
 300
 301 static const struct dcn10_ipp_shift ipp_shift = {
 302                 IPP_MASK_SH_LIST_DCN10(__SHIFT)
 303 };
 304
 305 static const struct dcn10_ipp_mask ipp_mask = {
 306                 IPP_MASK_SH_LIST_DCN10(_MASK),
 307 };
 308
 309 #define opp_regs(id)\
 310 [id] = {\
 311         OPP_REG_LIST_DCN10(id),\
 312 }
 313
 314 static const struct dcn10_opp_registers opp_regs[] = {
 315         opp_regs(0),
 316         opp_regs(1),
 317         opp_regs(2),
 318         opp_regs(3),
 319 };
 320
 321 static const struct dcn10_opp_shift opp_shift = {
 322                 OPP_MASK_SH_LIST_DCN10(__SHIFT)
 323 };
 324
 325 static const struct dcn10_opp_mask opp_mask = {
 326                 OPP_MASK_SH_LIST_DCN10(_MASK),
 327 };
 328
 329 #define aux_engine_regs(id)\
 330 [id] = {\
 331         AUX_COMMON_REG_LIST(id), \
 332         .AUX_RESET_MASK = 0 \
 333 }
 334
 335 static const struct dce110_aux_registers aux_engine_regs[] = {
 336                 aux_engine_regs(0),
 337                 aux_engine_regs(1),
 338                 aux_engine_regs(2),
 339                 aux_engine_regs(3),
 340                 aux_engine_regs(4),
 341                 aux_engine_regs(5)
 342 };
 343
 344 #define tf_regs(id)\
 345 [id] = {\
 346         TF_REG_LIST_DCN10(id),\
 347 }
 348
 349 static const struct dcn_dpp_registers tf_regs[] = {
 350         tf_regs(0),
 351         tf_regs(1),
 352         tf_regs(2),
 353         tf_regs(3),
 354 };
 355
 356 static const struct dcn_dpp_shift tf_shift = {
 357         TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
 358         TF_DEBUG_REG_LIST_SH_DCN10
 359
 360 };
 361
 362 static const struct dcn_dpp_mask tf_mask = {
 363         TF_REG_LIST_SH_MASK_DCN10(_MASK),
 364         TF_DEBUG_REG_LIST_MASK_DCN10
 365 };
 366
 367 static const struct dcn_mpc_registers mpc_regs = {
 368                 MPC_COMMON_REG_LIST_DCN1_0(0),
 369                 MPC_COMMON_REG_LIST_DCN1_0(1),
 370                 MPC_COMMON_REG_LIST_DCN1_0(2),
 371                 MPC_COMMON_REG_LIST_DCN1_0(3),
 372                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
 373                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
 374                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
 375                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
 376 };
 377
 378 static const struct dcn_mpc_shift mpc_shift = {
 379         MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
 380         SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
 381 };
 382
 383 static const struct dcn_mpc_mask mpc_mask = {
 384         MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
 385         SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
 386 };
 387
 388 #define tg_regs(id)\
 389 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
 390
 391 static const struct dcn_optc_registers tg_regs[] = {
 392         tg_regs(0),
 393         tg_regs(1),
 394         tg_regs(2),
 395         tg_regs(3),
 396 };
 397
 398 static const struct dcn_optc_shift tg_shift = {
 399         TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 400 };
 401
 402 static const struct dcn_optc_mask tg_mask = {
 403         TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 404 };
 405
 406 static const struct bios_registers bios_regs = {
 407                 NBIO_SR(BIOS_SCRATCH_3),
 408                 NBIO_SR(BIOS_SCRATCH_6)
 409 };
 410
 411 #define hubp_regs(id)\
 412 [id] = {\
 413         HUBP_REG_LIST_DCN10(id)\
 414 }
 415
 416 static const struct dcn_mi_registers hubp_regs[] = {
 417         hubp_regs(0),
 418         hubp_regs(1),
 419         hubp_regs(2),
 420         hubp_regs(3),
 421 };
 422
 423 static const struct dcn_mi_shift hubp_shift = {
 424                 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
 425 };
 426
 427 static const struct dcn_mi_mask hubp_mask = {
 428                 HUBP_MASK_SH_LIST_DCN10(_MASK)
 429 };
 430
 431 static const struct dcn_hubbub_registers hubbub_reg = {
 432                 HUBBUB_REG_LIST_DCN10(0)
 433 };
 434
 435 static const struct dcn_hubbub_shift hubbub_shift = {
 436                 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
 437 };
 438
 439 static const struct dcn_hubbub_mask hubbub_mask = {
 440                 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
 441 };
 442
 443 static int map_transmitter_id_to_phy_instance(
 444         enum transmitter transmitter)
 445 {
 446         switch (transmitter) {
 447         case TRANSMITTER_UNIPHY_A:
 448                 return 0;
 449         break;
 450         case TRANSMITTER_UNIPHY_B:
 451                 return 1;
 452         break;
 453         case TRANSMITTER_UNIPHY_C:
 454                 return 2;
 455         break;
 456         case TRANSMITTER_UNIPHY_D:
 457                 return 3;
 458         break;
 459         default:
 460                 ASSERT(0);
 461                 return 0;
 462         }
 463 }
 464
 465 #define clk_src_regs(index, pllid)\
 466 [index] = {\
 467         CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
 468 }
 469
 470 static const struct dce110_clk_src_regs clk_src_regs[] = {
 471         clk_src_regs(0, A),
 472         clk_src_regs(1, B),
 473         clk_src_regs(2, C),
 474         clk_src_regs(3, D)
 475 };
 476
 477 static const struct dce110_clk_src_shift cs_shift = {
 478                 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 479 };
 480
 481 static const struct dce110_clk_src_mask cs_mask = {
 482                 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 483 };
 484
 485 static const struct resource_caps res_cap = {
 486                 .num_timing_generator = 4,
 487                 .num_opp = 4,
 488                 .num_video_plane = 4,
 489                 .num_audio = 4,
 490                 .num_stream_encoder = 4,
 491                 .num_pll = 4,
 492                 .num_ddc = 4,
 493 };
 494
 495 static const struct resource_caps rv2_res_cap = {
 496                 .num_timing_generator = 3,
 497                 .num_opp = 3,
 498                 .num_video_plane = 3,
 499                 .num_audio = 3,
 500                 .num_stream_encoder = 3,
 501                 .num_pll = 3,
 502                 .num_ddc = 4,
 503 };
 504
 505 static const struct dc_plane_cap plane_cap = {
 506         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 507         .blends_with_above = true,
 508         .blends_with_below = true,
 509         .per_pixel_alpha = true,
 510
 511         .pixel_format_support = {
 512                         .argb8888 = true,
 513                         .nv12 = true,
 514                         .fp16 = true,
 515                         .p010 = true
 516         },
 517
 518         .max_upscale_factor = {
 519                         .argb8888 = 16000,
 520                         .nv12 = 16000,
 521                         .fp16 = 1
 522         },
 523
 524         .max_downscale_factor = {
 525                         .argb8888 = 250,
 526                         .nv12 = 250,
 527                         .fp16 = 1
 528         }
 529 };
 530
 531 static const struct dc_debug_options debug_defaults_drv = {
 532                 .sanity_checks = true,
 533                 .disable_dmcu = false,
 534                 .force_abm_enable = false,
 535                 .timing_trace = false,
 536                 .clock_trace = true,
 537
 538                 /* raven smu dones't allow 0 disp clk,
 539                  * smu min disp clk limit is 50Mhz
 540                  * keep min disp clk 100Mhz avoid smu hang
 541                  */
 542                 .min_disp_clk_khz = 100000,
 543
 544                 .disable_pplib_clock_request = false,
 545                 .disable_pplib_wm_range = false,
 546                 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
 547                 .pipe_split_policy = MPC_SPLIT_AVOID,
 548                 .force_single_disp_pipe_split = false,
 549                 .disable_dcc = DCC_ENABLE,
 550                 .voltage_align_fclk = true,
 551                 .disable_stereo_support = true,
 552                 .vsr_support = true,
 553                 .performance_trace = false,
 554                 .az_endpoint_mute_only = true,
 555                 .recovery_enabled = false, /*enable this by default after testing.*/
 556                 .max_downscale_src_width = 3840,
 557                 .underflow_assert_delay_us = 0xFFFFFFFF,
 558 };
 559
 560 static const struct dc_debug_options debug_defaults_diags = {
 561                 .disable_dmcu = false,
 562                 .force_abm_enable = false,
 563                 .timing_trace = true,
 564                 .clock_trace = true,
 565                 .disable_stutter = true,
 566                 .disable_pplib_clock_request = true,
 567                 .disable_pplib_wm_range = true,
 568                 .underflow_assert_delay_us = 0xFFFFFFFF,
 569 };
 570
 571 static void dcn10_dpp_destroy(struct dpp **dpp)
 572 {
 573         kfree(TO_DCN10_DPP(*dpp));
 574         *dpp = NULL;
 575 }
 576
 577 static struct dpp *dcn10_dpp_create(
 578         struct dc_context *ctx,
 579         uint32_t inst)
 580 {
 581         struct dcn10_dpp *dpp =
 582                 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
 583
 584         if (!dpp)
 585                 return NULL;
 586
 587         dpp1_construct(dpp, ctx, inst,
 588                        &tf_regs[inst], &tf_shift, &tf_mask);
 589         return &dpp->base;
 590 }
 591
 592 static struct input_pixel_processor *dcn10_ipp_create(
 593         struct dc_context *ctx, uint32_t inst)
 594 {
 595         struct dcn10_ipp *ipp =
 596                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 597
 598         if (!ipp) {
 599                 BREAK_TO_DEBUGGER();
 600                 return NULL;
 601         }
 602
 603         dcn10_ipp_construct(ipp, ctx, inst,
 604                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 605         return &ipp->base;
 606 }
 607
 608
 609 static struct output_pixel_processor *dcn10_opp_create(
 610         struct dc_context *ctx, uint32_t inst)
 611 {
 612         struct dcn10_opp *opp =
 613                 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
 614
 615         if (!opp) {
 616                 BREAK_TO_DEBUGGER();
 617                 return NULL;
 618         }
 619
 620         dcn10_opp_construct(opp, ctx, inst,
 621                         &opp_regs[inst], &opp_shift, &opp_mask);
 622         return &opp->base;
 623 }
 624
 625 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
 626                                                uint32_t inst)
 627 {
 628         struct aux_engine_dce110 *aux_engine =
 629                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 630
 631         if (!aux_engine)
 632                 return NULL;
 633
 634         dce110_aux_engine_construct(aux_engine, ctx, inst,
 635                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 636                                     &aux_engine_regs[inst],
 637                                         &aux_mask,
 638                                         &aux_shift,
 639                                         ctx->dc->caps.extended_aux_timeout_support);
 640
 641         return &aux_engine->base;
 642 }
 643 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 644
 645 static const struct dce_i2c_registers i2c_hw_regs[] = {
 646                 i2c_inst_regs(1),
 647                 i2c_inst_regs(2),
 648                 i2c_inst_regs(3),
 649                 i2c_inst_regs(4),
 650                 i2c_inst_regs(5),
 651                 i2c_inst_regs(6),
 652 };
 653
 654 static const struct dce_i2c_shift i2c_shifts = {
 655                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 656 };
 657
 658 static const struct dce_i2c_mask i2c_masks = {
 659                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 660 };
 661
 662 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
 663                                               uint32_t inst)
 664 {
 665         struct dce_i2c_hw *dce_i2c_hw =
 666                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 667
 668         if (!dce_i2c_hw)
 669                 return NULL;
 670
 671         dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 672                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 673
 674         return dce_i2c_hw;
 675 }
 676 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
 677 {
 678         struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
 679                                           GFP_KERNEL);
 680
 681         if (!mpc10)
 682                 return NULL;
 683
 684         dcn10_mpc_construct(mpc10, ctx,
 685                         &mpc_regs,
 686                         &mpc_shift,
 687                         &mpc_mask,
 688                         4);
 689
 690         return &mpc10->base;
 691 }
 692
 693 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
 694 {
 695         struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
 696                                           GFP_KERNEL);
 697
 698         if (!dcn10_hubbub)
 699                 return NULL;
 700
 701         hubbub1_construct(&dcn10_hubbub->base, ctx,
 702                         &hubbub_reg,
 703                         &hubbub_shift,
 704                         &hubbub_mask);
 705
 706         return &dcn10_hubbub->base;
 707 }
 708
 709 static struct timing_generator *dcn10_timing_generator_create(
 710                 struct dc_context *ctx,
 711                 uint32_t instance)
 712 {
 713         struct optc *tgn10 =
 714                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 715
 716         if (!tgn10)
 717                 return NULL;
 718
 719         tgn10->base.inst = instance;
 720         tgn10->base.ctx = ctx;
 721
 722         tgn10->tg_regs = &tg_regs[instance];
 723         tgn10->tg_shift = &tg_shift;
 724         tgn10->tg_mask = &tg_mask;
 725
 726         dcn10_timing_generator_init(tgn10);
 727
 728         return &tgn10->base;
 729 }
 730
 731 static const struct encoder_feature_support link_enc_feature = {
 732                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 733                 .max_hdmi_pixel_clock = 600000,
 734                 .hdmi_ycbcr420_supported = true,
 735                 .dp_ycbcr420_supported = true,
 736                 .flags.bits.IS_HBR2_CAPABLE = true,
 737                 .flags.bits.IS_HBR3_CAPABLE = true,
 738                 .flags.bits.IS_TPS3_CAPABLE = true,
 739                 .flags.bits.IS_TPS4_CAPABLE = true
 740 };
 741
 742 static struct link_encoder *dcn10_link_encoder_create(
 743         struct dc_context *ctx,
 744         const struct encoder_init_data *enc_init_data)
 745 {
 746         struct dcn10_link_encoder *enc10 =
 747                 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
 748         int link_regs_id;
 749
 750         if (!enc10)
 751                 return NULL;
 752
 753         link_regs_id =
 754                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 755
 756         dcn10_link_encoder_construct(enc10,
 757                                       enc_init_data,
 758                                       &link_enc_feature,
 759                                       &link_enc_regs[link_regs_id],
 760                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 761                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
 762                                       &le_shift,
 763                                       &le_mask);
 764
 765         return &enc10->base;
 766 }
 767
 768 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 769 {
 770         struct dce_panel_cntl *panel_cntl =
 771                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 772
 773         if (!panel_cntl)
 774                 return NULL;
 775
 776         dce_panel_cntl_construct(panel_cntl,
 777                         init_data,
 778                         &panel_cntl_regs[init_data->inst],
 779                         &panel_cntl_shift,
 780                         &panel_cntl_mask);
 781
 782         return &panel_cntl->base;
 783 }
 784
 785 static struct clock_source *dcn10_clock_source_create(
 786         struct dc_context *ctx,
 787         struct dc_bios *bios,
 788         enum clock_source_id id,
 789         const struct dce110_clk_src_regs *regs,
 790         bool dp_clk_src)
 791 {
 792         struct dce110_clk_src *clk_src =
 793                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 794
 795         if (!clk_src)
 796                 return NULL;
 797
 798         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 799                         regs, &cs_shift, &cs_mask)) {
 800                 clk_src->base.dp_clk_src = dp_clk_src;
 801                 return &clk_src->base;
 802         }
 803
 804         kfree(clk_src);
 805         BREAK_TO_DEBUGGER();
 806         return NULL;
 807 }
 808
 809 static void read_dce_straps(
 810         struct dc_context *ctx,
 811         struct resource_straps *straps)
 812 {
 813         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 814                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 815 }
 816
 817 static struct audio *create_audio(
 818                 struct dc_context *ctx, unsigned int inst)
 819 {
 820         return dce_audio_create(ctx, inst,
 821                         &audio_regs[inst], &audio_shift, &audio_mask);
 822 }
 823
 824 static struct stream_encoder *dcn10_stream_encoder_create(
 825         enum engine_id eng_id,
 826         struct dc_context *ctx)
 827 {
 828         struct dcn10_stream_encoder *enc1 =
 829                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 830
 831         if (!enc1)
 832                 return NULL;
 833
 834         dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 835                                         &stream_enc_regs[eng_id],
 836                                         &se_shift, &se_mask);
 837         return &enc1->base;
 838 }
 839
 840 static const struct dce_hwseq_registers hwseq_reg = {
 841                 HWSEQ_DCN1_REG_LIST()
 842 };
 843
 844 static const struct dce_hwseq_shift hwseq_shift = {
 845                 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
 846 };
 847
 848 static const struct dce_hwseq_mask hwseq_mask = {
 849                 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
 850 };
 851
 852 static struct dce_hwseq *dcn10_hwseq_create(
 853         struct dc_context *ctx)
 854 {
 855         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 856
 857         if (hws) {
 858                 hws->ctx = ctx;
 859                 hws->regs = &hwseq_reg;
 860                 hws->shifts = &hwseq_shift;
 861                 hws->masks = &hwseq_mask;
 862                 hws->wa.DEGVIDCN10_253 = true;
 863                 hws->wa.false_optc_underflow = true;
 864                 hws->wa.DEGVIDCN10_254 = true;
 865
 866                 if ((ctx->asic_id.chip_family == FAMILY_RV) &&
 867                         ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev))
 868                         switch (ctx->asic_id.pci_revision_id) {
 869                         case PRID_POLLOCK_94:
 870                         case PRID_POLLOCK_95:
 871                         case PRID_POLLOCK_E9:
 872                         case PRID_POLLOCK_EA:
 873                         case PRID_POLLOCK_EB:
 874                                 hws->wa.wait_hubpret_read_start_during_mpo_transition = true;
 875                                 break;
 876                         default:
 877                                 hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
 878                                 break;
 879                         }
 880         }
 881         return hws;
 882 }
 883
 884 static const struct resource_create_funcs res_create_funcs = {
 885         .read_dce_straps = read_dce_straps,
 886         .create_audio = create_audio,
 887         .create_stream_encoder = dcn10_stream_encoder_create,
 888         .create_hwseq = dcn10_hwseq_create,
 889 };
 890
 891 static const struct resource_create_funcs res_create_maximus_funcs = {
 892         .read_dce_straps = NULL,
 893         .create_audio = NULL,
 894         .create_stream_encoder = NULL,
 895         .create_hwseq = dcn10_hwseq_create,
 896 };
 897
 898 static void dcn10_clock_source_destroy(struct clock_source **clk_src)
 899 {
 900         kfree(TO_DCE110_CLK_SRC(*clk_src));
 901         *clk_src = NULL;
 902 }
 903
 904 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
 905 {
 906         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
 907
 908         if (!pp_smu)
 909                 return pp_smu;
 910
 911         dm_pp_get_funcs(ctx, pp_smu);
 912         return pp_smu;
 913 }
 914
 915 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
 916 {
 917         unsigned int i;
 918
 919         for (i = 0; i < pool->base.stream_enc_count; i++) {
 920                 if (pool->base.stream_enc[i] != NULL) {
 921                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 922                         pool->base.stream_enc[i] = NULL;
 923                 }
 924         }
 925
 926         if (pool->base.mpc != NULL) {
 927                 kfree(TO_DCN10_MPC(pool->base.mpc));
 928                 pool->base.mpc = NULL;
 929         }
 930
 931         kfree(pool->base.hubbub);
 932         pool->base.hubbub = NULL;
 933
 934         for (i = 0; i < pool->base.pipe_count; i++) {
 935                 if (pool->base.opps[i] != NULL)
 936                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 937
 938                 if (pool->base.dpps[i] != NULL)
 939                         dcn10_dpp_destroy(&pool->base.dpps[i]);
 940
 941                 if (pool->base.ipps[i] != NULL)
 942                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 943
 944                 if (pool->base.hubps[i] != NULL) {
 945                         kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
 946                         pool->base.hubps[i] = NULL;
 947                 }
 948
 949                 if (pool->base.irqs != NULL) {
 950                         dal_irq_service_destroy(&pool->base.irqs);
 951                 }
 952
 953                 if (pool->base.timing_generators[i] != NULL)    {
 954                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 955                         pool->base.timing_generators[i] = NULL;
 956                 }
 957         }
 958
 959         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 960                 if (pool->base.engines[i] != NULL)
 961                         dce110_engine_destroy(&pool->base.engines[i]);
 962                 kfree(pool->base.hw_i2cs[i]);
 963                 pool->base.hw_i2cs[i] = NULL;
 964                 kfree(pool->base.sw_i2cs[i]);
 965                 pool->base.sw_i2cs[i] = NULL;
 966         }
 967
 968         for (i = 0; i < pool->base.audio_count; i++) {
 969                 if (pool->base.audios[i])
 970                         dce_aud_destroy(&pool->base.audios[i]);
 971         }
 972
 973         for (i = 0; i < pool->base.clk_src_count; i++) {
 974                 if (pool->base.clock_sources[i] != NULL) {
 975                         dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
 976                         pool->base.clock_sources[i] = NULL;
 977                 }
 978         }
 979
 980         if (pool->base.dp_clock_source != NULL) {
 981                 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
 982                 pool->base.dp_clock_source = NULL;
 983         }
 984
 985         if (pool->base.abm != NULL)
 986                 dce_abm_destroy(&pool->base.abm);
 987
 988         if (pool->base.dmcu != NULL)
 989                 dce_dmcu_destroy(&pool->base.dmcu);
 990
 991         kfree(pool->base.pp_smu);
 992 }
 993
 994 static struct hubp *dcn10_hubp_create(
 995         struct dc_context *ctx,
 996         uint32_t inst)
 997 {
 998         struct dcn10_hubp *hubp1 =
 999                 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
1000
1001         if (!hubp1)
1002                 return NULL;
1003
1004         dcn10_hubp_construct(hubp1, ctx, inst,
1005                              &hubp_regs[inst], &hubp_shift, &hubp_mask);
1006         return &hubp1->base;
1007 }
1008
1009 static void get_pixel_clock_parameters(
1010         const struct pipe_ctx *pipe_ctx,
1011         struct pixel_clk_params *pixel_clk_params)
1012 {
1013         const struct dc_stream_state *stream = pipe_ctx->stream;
1014         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1015         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1016         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1017         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1018         /* TODO: un-hardcode*/
1019         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1020                 LINK_RATE_REF_FREQ_IN_KHZ;
1021         pixel_clk_params->flags.ENABLE_SS = 0;
1022         pixel_clk_params->color_depth =
1023                 stream->timing.display_color_depth;
1024         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1025         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1026
1027         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1028                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1029
1030         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1031                 pixel_clk_params->requested_pix_clk_100hz  /= 2;
1032         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1033                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1034
1035 }
1036
1037 static void build_clamping_params(struct dc_stream_state *stream)
1038 {
1039         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1040         stream->clamping.c_depth = stream->timing.display_color_depth;
1041         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1042 }
1043
1044 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1045 {
1046
1047         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1048
1049         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1050                 pipe_ctx->clock_source,
1051                 &pipe_ctx->stream_res.pix_clk_params,
1052                 &pipe_ctx->pll_settings);
1053
1054         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1055
1056         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1057                                         &pipe_ctx->stream->bit_depth_params);
1058         build_clamping_params(pipe_ctx->stream);
1059 }
1060
1061 static enum dc_status build_mapped_resource(
1062                 const struct dc *dc,
1063                 struct dc_state *context,
1064                 struct dc_stream_state *stream)
1065 {
1066         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1067
1068         if (!pipe_ctx)
1069                 return DC_ERROR_UNEXPECTED;
1070
1071         build_pipe_hw_param(pipe_ctx);
1072         return DC_OK;
1073 }
1074
1075 static enum dc_status dcn10_add_stream_to_ctx(
1076                 struct dc *dc,
1077                 struct dc_state *new_ctx,
1078                 struct dc_stream_state *dc_stream)
1079 {
1080         enum dc_status result = DC_ERROR_UNEXPECTED;
1081
1082         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1083
1084         if (result == DC_OK)
1085                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1086
1087
1088         if (result == DC_OK)
1089                 result = build_mapped_resource(dc, new_ctx, dc_stream);
1090
1091         return result;
1092 }
1093
1094 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
1095                 struct dc_state *context,
1096                 const struct resource_pool *pool,
1097                 struct dc_stream_state *stream)
1098 {
1099         struct resource_context *res_ctx = &context->res_ctx;
1100         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1101         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1102
1103         if (!head_pipe) {
1104                 ASSERT(0);
1105                 return NULL;
1106         }
1107
1108         if (!idle_pipe)
1109                 return NULL;
1110
1111         idle_pipe->stream = head_pipe->stream;
1112         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1113         idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1114         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1115
1116         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1117         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1118         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1119         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1120
1121         return idle_pipe;
1122 }
1123
1124 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1125                 const struct dc_dcc_surface_param *input,
1126                 struct dc_surface_dcc_cap *output)
1127 {
1128         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1129                         dc->res_pool->hubbub,
1130                         input,
1131                         output);
1132 }
1133
1134 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1135 {
1136         struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1137
1138         dcn10_resource_destruct(dcn10_pool);
1139         kfree(dcn10_pool);
1140         *pool = NULL;
1141 }
1142
1143 static bool dcn10_validate_bandwidth(
1144                 struct dc *dc,
1145                 struct dc_state *context,
1146                 bool fast_validate)
1147 {
1148         bool voltage_supported;
1149
1150         DC_FP_START();
1151         voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);
1152         DC_FP_END();
1153
1154         return voltage_supported;
1155 }
1156
1157 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1158 {
1159         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1160                         && caps->max_video_width != 0
1161                         && plane_state->src_rect.width > caps->max_video_width)
1162                 return DC_FAIL_SURFACE_VALIDATE;
1163
1164         return DC_OK;
1165 }
1166
1167 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1168 {
1169         int i, j;
1170         bool video_down_scaled = false;
1171         bool video_large = false;
1172         bool desktop_large = false;
1173         bool dcc_disabled = false;
1174         bool mpo_enabled = false;
1175
1176         for (i = 0; i < context->stream_count; i++) {
1177                 if (context->stream_status[i].plane_count == 0)
1178                         continue;
1179
1180                 if (context->stream_status[i].plane_count > 2)
1181                         return DC_FAIL_UNSUPPORTED_1;
1182
1183                 if (context->stream_status[i].plane_count > 1)
1184                         mpo_enabled = true;
1185
1186                 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1187                         struct dc_plane_state *plane =
1188                                 context->stream_status[i].plane_states[j];
1189
1190
1191                         if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1192
1193                                 if (plane->src_rect.width > plane->dst_rect.width ||
1194                                                 plane->src_rect.height > plane->dst_rect.height)
1195                                         video_down_scaled = true;
1196
1197                                 if (plane->src_rect.width >= 3840)
1198                                         video_large = true;
1199
1200                         } else {
1201                                 if (plane->src_rect.width >= 3840)
1202                                         desktop_large = true;
1203                                 if (!plane->dcc.enable)
1204                                         dcc_disabled = true;
1205                         }
1206                 }
1207         }
1208
1209         /* Disable MPO in multi-display configurations. */
1210         if (context->stream_count > 1 && mpo_enabled)
1211                 return DC_FAIL_UNSUPPORTED_1;
1212
1213         /*
1214          * Workaround: On DCN10 there is UMC issue that causes underflow when
1215          * playing 4k video on 4k desktop with video downscaled and single channel
1216          * memory
1217          */
1218         if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1219                         dc->dcn_soc->number_of_channels == 1)
1220                 return DC_FAIL_SURFACE_VALIDATE;
1221
1222         return DC_OK;
1223 }
1224
1225 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1226 {
1227         enum surface_pixel_format surf_pix_format = plane_state->format;
1228         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1229
1230         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1231
1232         if (bpp == 64)
1233                 swizzle = DC_SW_64KB_D;
1234         else
1235                 swizzle = DC_SW_64KB_S;
1236
1237         plane_state->tiling_info.gfx9.swizzle = swizzle;
1238         return DC_OK;
1239 }
1240
1241 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1242                 struct resource_context *res_ctx,
1243                 const struct resource_pool *pool,
1244                 struct dc_stream_state *stream)
1245 {
1246         int i;
1247         int j = -1;
1248         struct dc_link *link = stream->link;
1249
1250         for (i = 0; i < pool->stream_enc_count; i++) {
1251                 if (!res_ctx->is_stream_enc_acquired[i] &&
1252                                 pool->stream_enc[i]) {
1253                         /* Store first available for MST second display
1254                          * in daisy chain use case
1255                          */
1256                         j = i;
1257                         if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
1258                                         link->link_enc->preferred_engine)
1259                                 return pool->stream_enc[i];
1260                 }
1261         }
1262
1263         /*
1264          * For CZ and later, we can allow DIG FE and BE to differ for all display types
1265          */
1266
1267         if (j >= 0)
1268                 return pool->stream_enc[j];
1269
1270         return NULL;
1271 }
1272
1273 static const struct dc_cap_funcs cap_funcs = {
1274         .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1275 };
1276
1277 static const struct resource_funcs dcn10_res_pool_funcs = {
1278         .destroy = dcn10_destroy_resource_pool,
1279         .link_enc_create = dcn10_link_encoder_create,
1280         .panel_cntl_create = dcn10_panel_cntl_create,
1281         .validate_bandwidth = dcn10_validate_bandwidth,
1282         .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1283         .validate_plane = dcn10_validate_plane,
1284         .validate_global = dcn10_validate_global,
1285         .add_stream_to_ctx = dcn10_add_stream_to_ctx,
1286         .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1287         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1288 };
1289
1290 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1291 {
1292         uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1293         /* RV1 support max 4 pipes */
1294         value = value & 0xf;
1295         return value;
1296 }
1297
1298 /*
1299  * Some architectures don't support soft-float (e.g. aarch64), on those
1300  * this function has to be called with hardfloat enabled, make sure not
1301  * to inline it so whatever fp stuff is done stays inside
1302  */
1303 static noinline void dcn10_resource_construct_fp(
1304         struct dc *dc)
1305 {
1306         if (dc->ctx->dce_version == DCN_VERSION_1_01) {
1307                 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
1308                 struct dcn_ip_params *dcn_ip = dc->dcn_ip;
1309                 struct display_mode_lib *dml = &dc->dml;
1310
1311                 dml->ip.max_num_dpp = 3;
1312                 /* TODO how to handle 23.84? */
1313                 dcn_soc->dram_clock_change_latency = 23;
1314                 dcn_ip->max_num_dpp = 3;
1315         }
1316         if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1317                 dc->dcn_soc->urgent_latency = 3;
1318                 dc->debug.disable_dmcu = true;
1319                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1320         }
1321
1322
1323         dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1324         ASSERT(dc->dcn_soc->number_of_channels < 3);
1325         if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1326                 dc->dcn_soc->number_of_channels = 2;
1327
1328         if (dc->dcn_soc->number_of_channels == 1) {
1329                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1330                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1331                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1332                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1333                 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1334                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1335                 }
1336         }
1337 }
1338
1339 static bool dcn10_resource_construct(
1340         uint8_t num_virtual_links,
1341         struct dc *dc,
1342         struct dcn10_resource_pool *pool)
1343 {
1344         int i;
1345         int j;
1346         struct dc_context *ctx = dc->ctx;
1347         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1348
1349         ctx->dc_bios->regs = &bios_regs;
1350
1351         if (ctx->dce_version == DCN_VERSION_1_01)
1352                 pool->base.res_cap = &rv2_res_cap;
1353         else
1354                 pool->base.res_cap = &res_cap;
1355         pool->base.funcs = &dcn10_res_pool_funcs;
1356
1357         /*
1358          * TODO fill in from actual raven resource when we create
1359          * more than virtual encoder
1360          */
1361
1362         /*************************************************
1363          *  Resource + asic cap harcoding                *
1364          *************************************************/
1365         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1366
1367         /* max pipe num for ASIC before check pipe fuses */
1368         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1369
1370         if (dc->ctx->dce_version == DCN_VERSION_1_01)
1371                 pool->base.pipe_count = 3;
1372         dc->caps.max_video_width = 3840;
1373         dc->caps.max_downscale_ratio = 200;
1374         dc->caps.i2c_speed_in_khz = 100;
1375         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1376         dc->caps.max_cursor_size = 256;
1377         dc->caps.min_horizontal_blanking_period = 80;
1378         dc->caps.max_slave_planes = 1;
1379         dc->caps.max_slave_yuv_planes = 1;
1380         dc->caps.max_slave_rgb_planes = 0;
1381         dc->caps.is_apu = true;
1382         dc->caps.post_blend_color_processing = false;
1383         dc->caps.extended_aux_timeout_support = false;
1384
1385         /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1386         dc->caps.force_dp_tps4_for_cp2520 = true;
1387
1388         /* Color pipeline capabilities */
1389         dc->caps.color.dpp.dcn_arch = 1;
1390         dc->caps.color.dpp.input_lut_shared = 1;
1391         dc->caps.color.dpp.icsc = 1;
1392         dc->caps.color.dpp.dgam_ram = 1;
1393         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1394         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1395         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1396         dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1397         dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1398         dc->caps.color.dpp.post_csc = 0;
1399         dc->caps.color.dpp.gamma_corr = 0;
1400         dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1401
1402         dc->caps.color.dpp.hw_3d_lut = 0;
1403         dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
1404         dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
1405         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
1406         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1407         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1408         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1409         dc->caps.color.dpp.ocsc = 1;
1410
1411         /* no post-blend color operations */
1412         dc->caps.color.mpc.gamut_remap = 0;
1413         dc->caps.color.mpc.num_3dluts = 0;
1414         dc->caps.color.mpc.shared_3d_lut = 0;
1415         dc->caps.color.mpc.ogam_ram = 0;
1416         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1417         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1418         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1419         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1420         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1421         dc->caps.color.mpc.ocsc = 0;
1422
1423         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1424                 dc->debug = debug_defaults_drv;
1425         else
1426                 dc->debug = debug_defaults_diags;
1427
1428         /*************************************************
1429          *  Create resources                             *
1430          *************************************************/
1431
1432         pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1433                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1434                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1435                                 &clk_src_regs[0], false);
1436         pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1437                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1438                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1439                                 &clk_src_regs[1], false);
1440         pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1441                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1442                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1443                                 &clk_src_regs[2], false);
1444
1445         if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1446                 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1447                                 dcn10_clock_source_create(ctx, ctx->dc_bios,
1448                                         CLOCK_SOURCE_COMBO_PHY_PLL3,
1449                                         &clk_src_regs[3], false);
1450         }
1451
1452         pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1453
1454         if (dc->ctx->dce_version == DCN_VERSION_1_01)
1455                 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1456
1457         pool->base.dp_clock_source =
1458                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1459                                 CLOCK_SOURCE_ID_DP_DTO,
1460                                 /* todo: not reuse phy_pll registers */
1461                                 &clk_src_regs[0], true);
1462
1463         for (i = 0; i < pool->base.clk_src_count; i++) {
1464                 if (pool->base.clock_sources[i] == NULL) {
1465                         dm_error("DC: failed to create clock sources!\n");
1466                         BREAK_TO_DEBUGGER();
1467                         goto fail;
1468                 }
1469         }
1470
1471         pool->base.dmcu = dcn10_dmcu_create(ctx,
1472                         &dmcu_regs,
1473                         &dmcu_shift,
1474                         &dmcu_mask);
1475         if (pool->base.dmcu == NULL) {
1476                 dm_error("DC: failed to create dmcu!\n");
1477                 BREAK_TO_DEBUGGER();
1478                 goto fail;
1479         }
1480
1481         pool->base.abm = dce_abm_create(ctx,
1482                         &abm_regs,
1483                         &abm_shift,
1484                         &abm_mask);
1485         if (pool->base.abm == NULL) {
1486                 dm_error("DC: failed to create abm!\n");
1487                 BREAK_TO_DEBUGGER();
1488                 goto fail;
1489         }
1490
1491         dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1492         memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1493         memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1494
1495         /* Other architectures we build for build this with soft-float */
1496         dcn10_resource_construct_fp(dc);
1497
1498         if (!dc->config.is_vmin_only_asic)
1499                 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))
1500                         switch (dc->ctx->asic_id.pci_revision_id) {
1501                         case PRID_DALI_DE:
1502                         case PRID_DALI_DF:
1503                         case PRID_DALI_E3:
1504                         case PRID_DALI_E4:
1505                         case PRID_POLLOCK_94:
1506                         case PRID_POLLOCK_95:
1507                         case PRID_POLLOCK_E9:
1508                         case PRID_POLLOCK_EA:
1509                         case PRID_POLLOCK_EB:
1510                                 dc->config.is_vmin_only_asic = true;
1511                                 break;
1512                         default:
1513                                 break;
1514                         }
1515
1516         pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1517
1518         /*
1519          * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1520          * implemented. So AZ D3 should work.For issue 197007.                   *
1521          */
1522         if (pool->base.pp_smu != NULL
1523                         && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1524                 dc->debug.az_endpoint_mute_only = false;
1525
1526         DC_FP_START();
1527         if (!dc->debug.disable_pplib_clock_request)
1528                 dcn_bw_update_from_pplib(dc);
1529         dcn_bw_sync_calcs_and_dml(dc);
1530         if (!dc->debug.disable_pplib_wm_range) {
1531                 dc->res_pool = &pool->base;
1532                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1533         }
1534         DC_FP_END();
1535
1536         {
1537                 struct irq_service_init_data init_data;
1538                 init_data.ctx = dc->ctx;
1539                 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1540                 if (!pool->base.irqs)
1541                         goto fail;
1542         }
1543
1544         /* index to valid pipe resource  */
1545         j = 0;
1546         /* mem input -> ipp -> dpp -> opp -> TG */
1547         for (i = 0; i < pool->base.pipe_count; i++) {
1548                 /* if pipe is disabled, skip instance of HW pipe,
1549                  * i.e, skip ASIC register instance
1550                  */
1551                 if ((pipe_fuses & (1 << i)) != 0)
1552                         continue;
1553
1554                 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1555                 if (pool->base.hubps[j] == NULL) {
1556                         BREAK_TO_DEBUGGER();
1557                         dm_error(
1558                                 "DC: failed to create memory input!\n");
1559                         goto fail;
1560                 }
1561
1562                 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1563                 if (pool->base.ipps[j] == NULL) {
1564                         BREAK_TO_DEBUGGER();
1565                         dm_error(
1566                                 "DC: failed to create input pixel processor!\n");
1567                         goto fail;
1568                 }
1569
1570                 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1571                 if (pool->base.dpps[j] == NULL) {
1572                         BREAK_TO_DEBUGGER();
1573                         dm_error(
1574                                 "DC: failed to create dpp!\n");
1575                         goto fail;
1576                 }
1577
1578                 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1579                 if (pool->base.opps[j] == NULL) {
1580                         BREAK_TO_DEBUGGER();
1581                         dm_error(
1582                                 "DC: failed to create output pixel processor!\n");
1583                         goto fail;
1584                 }
1585
1586                 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1587                                 ctx, i);
1588                 if (pool->base.timing_generators[j] == NULL) {
1589                         BREAK_TO_DEBUGGER();
1590                         dm_error("DC: failed to create tg!\n");
1591                         goto fail;
1592                 }
1593                 /* check next valid pipe */
1594                 j++;
1595         }
1596
1597         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1598                 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1599                 if (pool->base.engines[i] == NULL) {
1600                         BREAK_TO_DEBUGGER();
1601                         dm_error(
1602                                 "DC:failed to create aux engine!!\n");
1603                         goto fail;
1604                 }
1605                 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1606                 if (pool->base.hw_i2cs[i] == NULL) {
1607                         BREAK_TO_DEBUGGER();
1608                         dm_error(
1609                                 "DC:failed to create hw i2c!!\n");
1610                         goto fail;
1611                 }
1612                 pool->base.sw_i2cs[i] = NULL;
1613         }
1614
1615         /* valid pipe num */
1616         pool->base.pipe_count = j;
1617         pool->base.timing_generator_count = j;
1618
1619         /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1620          * the value may be changed
1621          */
1622         dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1623         dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1624
1625         pool->base.mpc = dcn10_mpc_create(ctx);
1626         if (pool->base.mpc == NULL) {
1627                 BREAK_TO_DEBUGGER();
1628                 dm_error("DC: failed to create mpc!\n");
1629                 goto fail;
1630         }
1631
1632         pool->base.hubbub = dcn10_hubbub_create(ctx);
1633         if (pool->base.hubbub == NULL) {
1634                 BREAK_TO_DEBUGGER();
1635                 dm_error("DC: failed to create hubbub!\n");
1636                 goto fail;
1637         }
1638
1639         if (!resource_construct(num_virtual_links, dc, &pool->base,
1640                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1641                         &res_create_funcs : &res_create_maximus_funcs)))
1642                         goto fail;
1643
1644         dcn10_hw_sequencer_construct(dc);
1645         dc->caps.max_planes =  pool->base.pipe_count;
1646
1647         for (i = 0; i < dc->caps.max_planes; ++i)
1648                 dc->caps.planes[i] = plane_cap;
1649
1650         dc->cap_funcs = cap_funcs;
1651
1652         return true;
1653
1654 fail:
1655
1656         dcn10_resource_destruct(pool);
1657
1658         return false;
1659 }
1660
1661 struct resource_pool *dcn10_create_resource_pool(
1662                 const struct dc_init_data *init_data,
1663                 struct dc *dc)
1664 {
1665         struct dcn10_resource_pool *pool =
1666                 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1667
1668         if (!pool)
1669                 return NULL;
1670
1671         if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1672                 return &pool->base;
1673
1674         kfree(pool);
1675         BREAK_TO_DEBUGGER();
1676         return NULL;
1677 }