2 * Copyright 2022 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "umc_v8_10.h"
24 #include "amdgpu_ras.h"
25 #include "amdgpu_umc.h"
27 #include "umc/umc_8_10_0_offset.h"
28 #include "umc/umc_8_10_0_sh_mask.h"
30 #define UMC_8_NODE_DIST 0x800000
31 #define UMC_8_INST_DIST 0x4000
33 struct channelnum_map_colbit {
38 const struct channelnum_map_colbit umc_v8_10_channelnum_map_colbit_table[] = {
49 umc_v8_10_channel_idx_tbl[]
50 [UMC_V8_10_UMC_INSTANCE_NUM]
51 [UMC_V8_10_CHANNEL_INSTANCE_NUM] = {
60 static inline uint32_t get_umc_v8_10_reg_offset(struct amdgpu_device *adev,
65 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst +
66 UMC_8_NODE_DIST * node_inst;
69 static void umc_v8_10_clear_error_count_per_channel(struct amdgpu_device *adev,
70 uint32_t umc_reg_offset)
72 uint32_t ecc_err_cnt_addr;
75 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
77 /* clear error count */
78 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
79 UMC_V8_10_CE_CNT_INIT);
82 static void umc_v8_10_clear_error_count(struct amdgpu_device *adev)
84 uint32_t node_inst = 0;
85 uint32_t umc_inst = 0;
87 uint32_t umc_reg_offset = 0;
89 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
90 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
95 umc_v8_10_clear_error_count_per_channel(adev,
100 static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev,
101 uint32_t umc_reg_offset,
102 unsigned long *error_count)
104 uint64_t mc_umc_status;
105 uint32_t mc_umc_status_addr;
107 /* UMC 8_10 registers */
109 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
111 /* Rely on MCUMC_STATUS for correctable error counter
112 * MCUMC_STATUS is a 64 bit register
114 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
115 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
116 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
120 static void umc_v8_10_query_uncorrectable_error_count(struct amdgpu_device *adev,
121 uint32_t umc_reg_offset,
122 unsigned long *error_count)
124 uint64_t mc_umc_status;
125 uint32_t mc_umc_status_addr;
127 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
129 /* Check the MCUMC_STATUS. */
130 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
131 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
132 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
133 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
134 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
135 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
136 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
140 static void umc_v8_10_query_ras_error_count(struct amdgpu_device *adev,
141 void *ras_error_status)
143 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
145 uint32_t node_inst = 0;
146 uint32_t umc_inst = 0;
147 uint32_t ch_inst = 0;
148 uint32_t umc_reg_offset = 0;
150 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
151 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
156 umc_v8_10_query_correctable_error_count(adev,
158 &(err_data->ce_count));
159 umc_v8_10_query_uncorrectable_error_count(adev,
161 &(err_data->ue_count));
164 umc_v8_10_clear_error_count(adev);
167 static uint32_t umc_v8_10_get_col_bit(uint32_t channel_num)
171 for (t = 0; t < ARRAY_SIZE(umc_v8_10_channelnum_map_colbit_table); t++)
172 if (channel_num == umc_v8_10_channelnum_map_colbit_table[t].channel_num)
173 return umc_v8_10_channelnum_map_colbit_table[t].col_bit;
175 /* Failed to get col_bit. */
180 * Mapping normal address to soc physical address in swizzle mode.
182 static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev,
183 uint32_t channel_idx,
184 uint64_t na, uint64_t *soc_pa)
186 uint32_t channel_num = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
187 uint32_t col_bit = umc_v8_10_get_col_bit(channel_num);
190 if (col_bit == U32_MAX)
193 tmp_addr = SWIZZLE_MODE_TMP_ADDR(na, channel_num, channel_idx);
194 *soc_pa = SWIZZLE_MODE_ADDR_HI(tmp_addr, col_bit) |
195 SWIZZLE_MODE_ADDR_MID(na, col_bit) |
196 SWIZZLE_MODE_ADDR_LOW(tmp_addr, col_bit) |
197 SWIZZLE_MODE_ADDR_LSB(na);
202 static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
203 struct ras_err_data *err_data,
204 uint32_t umc_reg_offset,
209 uint64_t mc_umc_status_addr;
210 uint64_t mc_umc_status, err_addr;
211 uint32_t channel_index;
214 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
215 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
217 if (mc_umc_status == 0)
220 if (!err_data->err_addr) {
221 /* clear umc status */
222 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
227 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
228 adev->umc.channel_inst_num +
229 umc_inst * adev->umc.channel_inst_num +
232 /* calculate error address if ue/ce error is detected */
233 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
234 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
235 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
236 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
238 uint64_t mc_umc_addrt0;
240 mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
241 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
242 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
244 /* the lowest lsb bits should be ignored */
245 addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
247 err_addr &= ~((0x1ULL << addr_lsb) - 1);
249 /* we only save ue error information currently, ce is skipped */
250 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
251 uint64_t na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
252 uint64_t na_err_addr, retired_page_addr;
256 /* loop for all possibilities of [C6 C5] in normal address. */
257 for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
258 na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
260 /* Mapping normal error address to retired soc physical address. */
261 ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
262 na_err_addr, &retired_page_addr);
264 dev_err(adev->dev, "Failed to map pa from umc na.\n");
267 dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
269 amdgpu_umc_fill_error_record(err_data, na_err_addr,
270 retired_page_addr, channel_index, umc_inst);
275 /* clear umc status */
276 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
279 static void umc_v8_10_query_ras_error_address(struct amdgpu_device *adev,
280 void *ras_error_status)
282 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
283 uint32_t node_inst = 0;
284 uint32_t umc_inst = 0;
285 uint32_t ch_inst = 0;
286 uint32_t umc_reg_offset = 0;
288 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
289 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
294 umc_v8_10_query_error_address(adev,
303 static void umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device *adev,
304 uint32_t umc_reg_offset)
306 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
307 uint32_t ecc_err_cnt_addr;
309 ecc_err_cnt_sel_addr =
310 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel);
312 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
314 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
316 /* set ce error interrupt type to APIC based interrupt */
317 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,
319 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
320 /* set error count to initial value */
321 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT);
324 static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev)
326 uint32_t node_inst = 0;
327 uint32_t umc_inst = 0;
328 uint32_t ch_inst = 0;
329 uint32_t umc_reg_offset = 0;
331 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
332 umc_reg_offset = get_umc_v8_10_reg_offset(adev,
337 umc_v8_10_err_cnt_init_per_channel(adev, umc_reg_offset);
341 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {
342 .query_ras_error_count = umc_v8_10_query_ras_error_count,
343 .query_ras_error_address = umc_v8_10_query_ras_error_address,
346 struct amdgpu_umc_ras umc_v8_10_ras = {
348 .hw_ops = &umc_v8_10_ras_hw_ops,
350 .err_cnt_init = umc_v8_10_err_cnt_init,