2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "gc/gc_11_0_0_offset.h"
34 #include "gc/gc_11_0_0_sh_mask.h"
35 #include "gc/gc_11_0_0_default.h"
36 #include "hdp/hdp_6_0_0_offset.h"
37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
39 #include "soc15_common.h"
41 #include "sdma_v6_0_0_pkt_open.h"
42 #include "nbio_v4_3.h"
43 #include "sdma_common.h"
44 #include "sdma_v6_0.h"
45 #include "v11_structs.h"
47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
52 #define SDMA1_REG_OFFSET 0x600
53 #define SDMA0_HYP_DEC_REG_START 0x5880
54 #define SDMA0_HYP_DEC_REG_END 0x589a
55 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
57 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
58 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
59 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
60 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
61 static int sdma_v6_0_start(struct amdgpu_device *adev);
63 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
67 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
68 internal_offset <= SDMA0_HYP_DEC_REG_END) {
69 base = adev->reg_offset[GC_HWIP][0][1];
71 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
73 base = adev->reg_offset[GC_HWIP][0][0];
75 internal_offset += SDMA1_REG_OFFSET;
78 return base + internal_offset;
82 * sdma_v6_0_init_microcode - load ucode images from disk
84 * @adev: amdgpu_device pointer
86 * Use the firmware interface to load the ucode images into
87 * the driver (not loaded into hw).
88 * Returns 0 on success, error on failure.
90 static int sdma_v6_0_init_microcode(struct amdgpu_device *adev)
93 char ucode_prefix[30];
97 amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix));
99 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
101 return amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
104 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
108 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
109 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
110 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
111 amdgpu_ring_write(ring, 1);
112 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
113 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
118 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
123 BUG_ON(offset > ring->buf_mask);
124 BUG_ON(ring->ring[offset] != 0x55aa55aa);
126 cur = (ring->wptr - 1) & ring->buf_mask;
128 ring->ring[offset] = cur - offset;
130 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
134 * sdma_v6_0_ring_get_rptr - get the current read pointer
136 * @ring: amdgpu ring pointer
138 * Get the current rptr from the hardware.
140 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
144 /* XXX check if swapping is necessary on BE */
145 rptr = (u64 *)ring->rptr_cpu_addr;
147 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
148 return ((*rptr) >> 2);
152 * sdma_v6_0_ring_get_wptr - get the current write pointer
154 * @ring: amdgpu ring pointer
156 * Get the current wptr from the hardware.
158 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
162 if (ring->use_doorbell) {
163 /* XXX check if swapping is necessary on BE */
164 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
165 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
172 * sdma_v6_0_ring_set_wptr - commit the write pointer
174 * @ring: amdgpu ring pointer
176 * Write the wptr back to the hardware.
178 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
180 struct amdgpu_device *adev = ring->adev;
181 uint32_t *wptr_saved;
182 uint32_t *is_queue_unmap;
183 uint64_t aggregated_db_index;
184 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
186 DRM_DEBUG("Setting write pointer\n");
188 if (ring->is_mes_queue) {
189 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
190 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
192 aggregated_db_index =
193 amdgpu_mes_get_aggregated_doorbell_index(adev,
196 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
198 *wptr_saved = ring->wptr << 2;
199 if (*is_queue_unmap) {
200 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
201 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
202 ring->doorbell_index, ring->wptr << 2);
203 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
205 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
206 ring->doorbell_index, ring->wptr << 2);
207 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
210 WDOORBELL64(aggregated_db_index,
214 if (ring->use_doorbell) {
215 DRM_DEBUG("Using doorbell -- "
216 "wptr_offs == 0x%08x "
217 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
218 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
220 lower_32_bits(ring->wptr << 2),
221 upper_32_bits(ring->wptr << 2));
222 /* XXX check if swapping is necessary on BE */
223 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
225 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
226 ring->doorbell_index, ring->wptr << 2);
227 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
229 DRM_DEBUG("Not using doorbell -- "
230 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
231 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
233 lower_32_bits(ring->wptr << 2),
235 upper_32_bits(ring->wptr << 2));
236 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
237 ring->me, regSDMA0_QUEUE0_RB_WPTR),
238 lower_32_bits(ring->wptr << 2));
239 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
240 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
241 upper_32_bits(ring->wptr << 2));
246 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
248 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
251 for (i = 0; i < count; i++)
252 if (sdma && sdma->burst_nop && (i == 0))
253 amdgpu_ring_write(ring, ring->funcs->nop |
254 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
256 amdgpu_ring_write(ring, ring->funcs->nop);
260 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
262 * @ring: amdgpu ring pointer
263 * @ib: IB object to schedule
265 * Schedule an IB in the DMA ring.
267 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
268 struct amdgpu_job *job,
269 struct amdgpu_ib *ib,
272 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
273 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
275 /* An IB packet must end on a 8 DW boundary--the next dword
276 * must be on a 8-dword boundary. Our IB packet below is 6
277 * dwords long, thus add x number of NOPs, such that, in
278 * modular arithmetic,
279 * wptr + 6 + x = 8k, k >= 0, which in C is,
280 * (wptr + 6 + x) % 8 = 0.
281 * The expression below, is a solution of x.
283 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
285 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
286 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
287 /* base must be 32 byte aligned */
288 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
289 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
290 amdgpu_ring_write(ring, ib->length_dw);
291 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
292 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
296 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
298 * @ring: amdgpu ring pointer
299 * @job: job to retrieve vmid from
300 * @ib: IB object to schedule
302 * flush the IB by graphics cache rinse.
304 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
306 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
307 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
310 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
311 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
312 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
313 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
314 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
315 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
316 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
317 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
318 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
323 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
325 * @ring: amdgpu ring pointer
327 * Emit an hdp flush packet on the requested DMA ring.
329 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
331 struct amdgpu_device *adev = ring->adev;
332 u32 ref_and_mask = 0;
333 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
335 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
337 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
338 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
339 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
340 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
341 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
342 amdgpu_ring_write(ring, ref_and_mask); /* reference */
343 amdgpu_ring_write(ring, ref_and_mask); /* mask */
344 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
345 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
349 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
351 * @ring: amdgpu ring pointer
352 * @fence: amdgpu fence object
354 * Add a DMA fence packet to the ring to write
355 * the fence seq number and DMA trap packet to generate
356 * an interrupt if needed.
358 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
361 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
362 /* write the fence */
363 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
364 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
365 /* zero in first two bits */
367 amdgpu_ring_write(ring, lower_32_bits(addr));
368 amdgpu_ring_write(ring, upper_32_bits(addr));
369 amdgpu_ring_write(ring, lower_32_bits(seq));
371 /* optionally write high bits as well */
374 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
375 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
376 /* zero in first two bits */
378 amdgpu_ring_write(ring, lower_32_bits(addr));
379 amdgpu_ring_write(ring, upper_32_bits(addr));
380 amdgpu_ring_write(ring, upper_32_bits(seq));
383 if (flags & AMDGPU_FENCE_FLAG_INT) {
384 uint32_t ctx = ring->is_mes_queue ?
385 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
386 /* generate an interrupt */
387 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
388 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
393 * sdma_v6_0_gfx_stop - stop the gfx async dma engines
395 * @adev: amdgpu_device pointer
397 * Stop the gfx async dma ring buffers.
399 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
401 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
402 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
403 u32 rb_cntl, ib_cntl;
406 if ((adev->mman.buffer_funcs_ring == sdma0) ||
407 (adev->mman.buffer_funcs_ring == sdma1))
408 amdgpu_ttm_set_buffer_funcs_status(adev, false);
410 for (i = 0; i < adev->sdma.num_instances; i++) {
411 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
412 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
413 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
414 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
415 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
416 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
419 sdma0->sched.ready = false;
420 sdma1->sched.ready = false;
424 * sdma_v6_0_rlc_stop - stop the compute async dma engines
426 * @adev: amdgpu_device pointer
428 * Stop the compute async dma queues.
430 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
436 * sdma_v6_0_ctx_switch_enable - stop the async dma engines context switch
438 * @adev: amdgpu_device pointer
439 * @enable: enable/disable the DMA MEs context switch.
441 * Halt or unhalt the async dma engines context switch.
443 static void sdma_v6_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
448 * sdma_v6_0_enable - stop the async dma engines
450 * @adev: amdgpu_device pointer
451 * @enable: enable/disable the DMA MEs.
453 * Halt or unhalt the async dma engines.
455 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
461 sdma_v6_0_gfx_stop(adev);
462 sdma_v6_0_rlc_stop(adev);
465 for (i = 0; i < adev->sdma.num_instances; i++) {
466 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
467 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
468 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
473 * sdma_v6_0_gfx_resume - setup and start the async dma engines
475 * @adev: amdgpu_device pointer
477 * Set up the gfx DMA ring buffers and enable them.
478 * Returns 0 for success, error for failure.
480 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
482 struct amdgpu_ring *ring;
483 u32 rb_cntl, ib_cntl;
491 for (i = 0; i < adev->sdma.num_instances; i++) {
492 ring = &adev->sdma.instance[i].ring;
494 if (!amdgpu_sriov_vf(adev))
495 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
497 /* Set ring buffer size in dwords */
498 rb_bufsz = order_base_2(ring->ring_size / 4);
499 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
503 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
504 RPTR_WRITEBACK_SWAP_ENABLE, 1);
506 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
507 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
509 /* Initialize the ring buffer's read and write pointers */
510 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
512 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
513 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
515 /* setup the wptr shadow polling */
516 wptr_gpu_addr = ring->wptr_gpu_addr;
517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
518 lower_32_bits(wptr_gpu_addr));
519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
520 upper_32_bits(wptr_gpu_addr));
522 /* set the wb address whether it's enabled or not */
523 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
524 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
525 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
526 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
528 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
529 if (amdgpu_sriov_vf(adev))
530 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);
532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
535 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
536 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
540 /* before programing wptr to a less value, need set minor_ptr_update first */
541 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
543 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
544 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
545 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
548 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
549 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
551 if (ring->use_doorbell) {
552 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
553 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
554 OFFSET, ring->doorbell_index);
556 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
558 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
559 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
562 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
563 ring->doorbell_index,
564 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
566 if (amdgpu_sriov_vf(adev))
567 sdma_v6_0_ring_set_wptr(ring);
569 /* set minor_ptr_update to 0 after wptr programed */
570 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
572 /* Set up RESP_MODE to non-copy addresses */
573 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
574 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
575 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
576 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
578 /* program default cache read and write policy */
579 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
580 /* clean read policy and write policy bits */
582 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
583 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
584 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
585 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
587 if (!amdgpu_sriov_vf(adev)) {
589 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
590 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
591 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
592 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
596 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
597 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
599 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
600 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
602 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
605 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
607 ring->sched.ready = true;
609 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
610 sdma_v6_0_ctx_switch_enable(adev, true);
611 sdma_v6_0_enable(adev, true);
614 r = amdgpu_ring_test_helper(ring);
616 ring->sched.ready = false;
620 if (adev->mman.buffer_funcs_ring == ring)
621 amdgpu_ttm_set_buffer_funcs_status(adev, true);
628 * sdma_v6_0_rlc_resume - setup and start the async dma engines
630 * @adev: amdgpu_device pointer
632 * Set up the compute DMA queues and enable them.
633 * Returns 0 for success, error for failure.
635 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
641 * sdma_v6_0_load_microcode - load the sDMA ME ucode
643 * @adev: amdgpu_device pointer
645 * Loads the sDMA0/1 ucode.
646 * Returns 0 for success, -EINVAL if the ucode is not available.
648 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
650 const struct sdma_firmware_header_v2_0 *hdr;
651 const __le32 *fw_data;
657 sdma_v6_0_enable(adev, false);
659 if (!adev->sdma.instance[0].fw)
662 /* use broadcast mode to load SDMA microcode by default */
663 use_broadcast = true;
666 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
667 /* load Control Thread microcode */
668 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
669 amdgpu_ucode_print_sdma_hdr(&hdr->header);
670 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
672 fw_data = (const __le32 *)
673 (adev->sdma.instance[0].fw->data +
674 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
676 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
678 for (j = 0; j < fw_size; j++) {
679 if (amdgpu_emu_mode == 1 && j % 500 == 0)
681 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
684 /* load Context Switch microcode */
685 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
687 fw_data = (const __le32 *)
688 (adev->sdma.instance[0].fw->data +
689 le32_to_cpu(hdr->ctl_ucode_offset));
691 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
693 for (j = 0; j < fw_size; j++) {
694 if (amdgpu_emu_mode == 1 && j % 500 == 0)
696 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
699 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
700 for (i = 0; i < adev->sdma.num_instances; i++) {
701 /* load Control Thread microcode */
702 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
703 amdgpu_ucode_print_sdma_hdr(&hdr->header);
704 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
706 fw_data = (const __le32 *)
707 (adev->sdma.instance[0].fw->data +
708 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
710 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
712 for (j = 0; j < fw_size; j++) {
713 if (amdgpu_emu_mode == 1 && j % 500 == 0)
715 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
718 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
720 /* load Context Switch microcode */
721 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
723 fw_data = (const __le32 *)
724 (adev->sdma.instance[0].fw->data +
725 le32_to_cpu(hdr->ctl_ucode_offset));
727 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
729 for (j = 0; j < fw_size; j++) {
730 if (amdgpu_emu_mode == 1 && j % 500 == 0)
732 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
735 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
742 static int sdma_v6_0_soft_reset(void *handle)
744 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
748 sdma_v6_0_gfx_stop(adev);
750 for (i = 0; i < adev->sdma.num_instances; i++) {
751 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
752 tmp |= SDMA0_FREEZE__FREEZE_MASK;
753 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
754 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
755 tmp |= SDMA0_F32_CNTL__HALT_MASK;
756 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
757 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
759 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
763 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
764 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
765 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
769 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
770 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
775 return sdma_v6_0_start(adev);
778 static bool sdma_v6_0_check_soft_reset(void *handle)
780 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
781 struct amdgpu_ring *ring;
783 long tmo = msecs_to_jiffies(1000);
785 for (i = 0; i < adev->sdma.num_instances; i++) {
786 ring = &adev->sdma.instance[i].ring;
787 r = amdgpu_ring_test_ib(ring, tmo);
796 * sdma_v6_0_start - setup and start the async dma engines
798 * @adev: amdgpu_device pointer
800 * Set up the DMA engines and enable them.
801 * Returns 0 for success, error for failure.
803 static int sdma_v6_0_start(struct amdgpu_device *adev)
807 if (amdgpu_sriov_vf(adev)) {
808 sdma_v6_0_ctx_switch_enable(adev, false);
809 sdma_v6_0_enable(adev, false);
811 /* set RB registers */
812 r = sdma_v6_0_gfx_resume(adev);
816 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
817 r = sdma_v6_0_load_microcode(adev);
821 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
822 if (amdgpu_emu_mode == 1)
827 sdma_v6_0_enable(adev, true);
828 /* enable sdma ring preemption */
829 sdma_v6_0_ctx_switch_enable(adev, true);
831 /* start the gfx rings and rlc compute queues */
832 r = sdma_v6_0_gfx_resume(adev);
835 r = sdma_v6_0_rlc_resume(adev);
840 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
841 struct amdgpu_mqd_prop *prop)
843 struct v11_sdma_mqd *m = mqd;
844 uint64_t wb_gpu_addr;
846 m->sdmax_rlcx_rb_cntl =
847 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
848 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
849 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
851 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
852 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
854 wb_gpu_addr = prop->wptr_gpu_addr;
855 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
856 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
858 wb_gpu_addr = prop->rptr_gpu_addr;
859 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
860 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
862 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
863 regSDMA0_QUEUE0_IB_CNTL));
865 m->sdmax_rlcx_doorbell_offset =
866 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
868 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
870 m->sdmax_rlcx_skip_cntl = 0;
871 m->sdmax_rlcx_context_status = 0;
872 m->sdmax_rlcx_doorbell_log = 0;
874 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
875 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
880 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
882 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
883 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
887 * sdma_v6_0_ring_test_ring - simple async dma engine test
889 * @ring: amdgpu_ring structure holding ring information
891 * Test the DMA engine by writing using it to write an
893 * Returns 0 for success, error for failure.
895 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
897 struct amdgpu_device *adev = ring->adev;
903 volatile uint32_t *cpu_ptr = NULL;
907 if (ring->is_mes_queue) {
909 offset = amdgpu_mes_ctx_get_offs(ring,
910 AMDGPU_MES_CTX_PADDING_OFFS);
911 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
912 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
915 r = amdgpu_device_wb_get(adev, &index);
917 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
921 gpu_addr = adev->wb.gpu_addr + (index * 4);
922 adev->wb.wb[index] = cpu_to_le32(tmp);
925 r = amdgpu_ring_alloc(ring, 5);
927 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
928 amdgpu_device_wb_free(adev, index);
932 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
933 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
934 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
935 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
936 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
937 amdgpu_ring_write(ring, 0xDEADBEEF);
938 amdgpu_ring_commit(ring);
940 for (i = 0; i < adev->usec_timeout; i++) {
941 if (ring->is_mes_queue)
942 tmp = le32_to_cpu(*cpu_ptr);
944 tmp = le32_to_cpu(adev->wb.wb[index]);
945 if (tmp == 0xDEADBEEF)
947 if (amdgpu_emu_mode == 1)
953 if (i >= adev->usec_timeout)
956 if (!ring->is_mes_queue)
957 amdgpu_device_wb_free(adev, index);
963 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
965 * @ring: amdgpu_ring structure holding ring information
967 * Test a simple IB in the DMA ring.
968 * Returns 0 on success, error on failure.
970 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
972 struct amdgpu_device *adev = ring->adev;
974 struct dma_fence *f = NULL;
979 volatile uint32_t *cpu_ptr = NULL;
982 memset(&ib, 0, sizeof(ib));
984 if (ring->is_mes_queue) {
986 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
987 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
988 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
990 offset = amdgpu_mes_ctx_get_offs(ring,
991 AMDGPU_MES_CTX_PADDING_OFFS);
992 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
993 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
996 r = amdgpu_device_wb_get(adev, &index);
998 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1002 gpu_addr = adev->wb.gpu_addr + (index * 4);
1003 adev->wb.wb[index] = cpu_to_le32(tmp);
1005 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1007 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1012 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1013 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1014 ib.ptr[1] = lower_32_bits(gpu_addr);
1015 ib.ptr[2] = upper_32_bits(gpu_addr);
1016 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1017 ib.ptr[4] = 0xDEADBEEF;
1018 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1019 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1020 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1023 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1027 r = dma_fence_wait_timeout(f, false, timeout);
1029 DRM_ERROR("amdgpu: IB test timed out\n");
1033 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1037 if (ring->is_mes_queue)
1038 tmp = le32_to_cpu(*cpu_ptr);
1040 tmp = le32_to_cpu(adev->wb.wb[index]);
1042 if (tmp == 0xDEADBEEF)
1048 amdgpu_ib_free(adev, &ib, NULL);
1051 if (!ring->is_mes_queue)
1052 amdgpu_device_wb_free(adev, index);
1058 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1060 * @ib: indirect buffer to fill with commands
1061 * @pe: addr of the page entry
1062 * @src: src addr to copy from
1063 * @count: number of page entries to update
1065 * Update PTEs by copying them from the GART using sDMA.
1067 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1068 uint64_t pe, uint64_t src,
1071 unsigned bytes = count * 8;
1073 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1074 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1075 ib->ptr[ib->length_dw++] = bytes - 1;
1076 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1077 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1078 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1079 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1080 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1085 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1087 * @ib: indirect buffer to fill with commands
1088 * @pe: addr of the page entry
1089 * @addr: dst addr to write into pe
1090 * @count: number of page entries to update
1091 * @incr: increase next addr by incr bytes
1092 * @flags: access flags
1094 * Update PTEs by writing them manually using sDMA.
1096 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1097 uint64_t value, unsigned count,
1100 unsigned ndw = count * 2;
1102 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1103 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1104 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1105 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1106 ib->ptr[ib->length_dw++] = ndw - 1;
1107 for (; ndw > 0; ndw -= 2) {
1108 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1109 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1115 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1117 * @ib: indirect buffer to fill with commands
1118 * @pe: addr of the page entry
1119 * @addr: dst addr to write into pe
1120 * @count: number of page entries to update
1121 * @incr: increase next addr by incr bytes
1122 * @flags: access flags
1124 * Update the page tables using sDMA.
1126 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1128 uint64_t addr, unsigned count,
1129 uint32_t incr, uint64_t flags)
1131 /* for physically contiguous pages (vram) */
1132 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1133 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1134 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1135 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1136 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1137 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1138 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1139 ib->ptr[ib->length_dw++] = incr; /* increment size */
1140 ib->ptr[ib->length_dw++] = 0;
1141 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1145 * sdma_v6_0_ring_pad_ib - pad the IB
1146 * @ib: indirect buffer to fill with padding
1148 * Pad the IB with NOPs to a boundary multiple of 8.
1150 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1152 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1156 pad_count = (-ib->length_dw) & 0x7;
1157 for (i = 0; i < pad_count; i++)
1158 if (sdma && sdma->burst_nop && (i == 0))
1159 ib->ptr[ib->length_dw++] =
1160 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1161 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1163 ib->ptr[ib->length_dw++] =
1164 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1168 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1170 * @ring: amdgpu_ring pointer
1172 * Make sure all previous operations are completed (CIK).
1174 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1176 uint32_t seq = ring->fence_drv.sync_seq;
1177 uint64_t addr = ring->fence_drv.gpu_addr;
1180 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1181 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1182 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1183 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1184 amdgpu_ring_write(ring, addr & 0xfffffffc);
1185 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1186 amdgpu_ring_write(ring, seq); /* reference */
1187 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1188 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1189 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1193 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1195 * @ring: amdgpu_ring pointer
1196 * @vm: amdgpu_vm pointer
1198 * Update the page table base and flush the VM TLB
1201 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1202 unsigned vmid, uint64_t pd_addr)
1204 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1207 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1208 uint32_t reg, uint32_t val)
1210 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1211 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1212 amdgpu_ring_write(ring, reg);
1213 amdgpu_ring_write(ring, val);
1216 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1217 uint32_t val, uint32_t mask)
1219 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1220 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1221 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1222 amdgpu_ring_write(ring, reg << 2);
1223 amdgpu_ring_write(ring, 0);
1224 amdgpu_ring_write(ring, val); /* reference */
1225 amdgpu_ring_write(ring, mask); /* mask */
1226 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1227 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1230 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1231 uint32_t reg0, uint32_t reg1,
1232 uint32_t ref, uint32_t mask)
1234 amdgpu_ring_emit_wreg(ring, reg0, ref);
1235 /* wait for a cycle to reset vm_inv_eng*_ack */
1236 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1237 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1240 static int sdma_v6_0_early_init(void *handle)
1242 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244 sdma_v6_0_set_ring_funcs(adev);
1245 sdma_v6_0_set_buffer_funcs(adev);
1246 sdma_v6_0_set_vm_pte_funcs(adev);
1247 sdma_v6_0_set_irq_funcs(adev);
1248 sdma_v6_0_set_mqd_funcs(adev);
1253 static int sdma_v6_0_sw_init(void *handle)
1255 struct amdgpu_ring *ring;
1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1259 /* SDMA trap event */
1260 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1261 GFX_11_0_0__SRCID__SDMA_TRAP,
1262 &adev->sdma.trap_irq);
1266 r = sdma_v6_0_init_microcode(adev);
1268 DRM_ERROR("Failed to load sdma firmware!\n");
1272 for (i = 0; i < adev->sdma.num_instances; i++) {
1273 ring = &adev->sdma.instance[i].ring;
1274 ring->ring_obj = NULL;
1275 ring->use_doorbell = true;
1278 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1279 ring->use_doorbell?"true":"false");
1281 ring->doorbell_index =
1282 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1284 sprintf(ring->name, "sdma%d", i);
1285 r = amdgpu_ring_init(adev, ring, 1024,
1286 &adev->sdma.trap_irq,
1287 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1288 AMDGPU_RING_PRIO_DEFAULT, NULL);
1296 static int sdma_v6_0_sw_fini(void *handle)
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301 for (i = 0; i < adev->sdma.num_instances; i++)
1302 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1304 amdgpu_sdma_destroy_inst_ctx(adev, true);
1309 static int sdma_v6_0_hw_init(void *handle)
1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313 return sdma_v6_0_start(adev);
1316 static int sdma_v6_0_hw_fini(void *handle)
1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320 if (amdgpu_sriov_vf(adev))
1323 sdma_v6_0_ctx_switch_enable(adev, false);
1324 sdma_v6_0_enable(adev, false);
1329 static int sdma_v6_0_suspend(void *handle)
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1333 return sdma_v6_0_hw_fini(adev);
1336 static int sdma_v6_0_resume(void *handle)
1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340 return sdma_v6_0_hw_init(adev);
1343 static bool sdma_v6_0_is_idle(void *handle)
1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1348 for (i = 0; i < adev->sdma.num_instances; i++) {
1349 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1351 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1358 static int sdma_v6_0_wait_for_idle(void *handle)
1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1364 for (i = 0; i < adev->usec_timeout; i++) {
1365 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1366 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1368 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1375 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1378 struct amdgpu_device *adev = ring->adev;
1380 u64 sdma_gfx_preempt;
1382 amdgpu_sdma_get_index_from_ring(ring, &index);
1384 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1386 /* assert preemption condition */
1387 amdgpu_ring_set_preempt_cond_exec(ring, false);
1389 /* emit the trailing fence */
1390 ring->trail_seq += 1;
1391 amdgpu_ring_alloc(ring, 10);
1392 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1393 ring->trail_seq, 0);
1394 amdgpu_ring_commit(ring);
1396 /* assert IB preemption */
1397 WREG32(sdma_gfx_preempt, 1);
1399 /* poll the trailing fence */
1400 for (i = 0; i < adev->usec_timeout; i++) {
1401 if (ring->trail_seq ==
1402 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1407 if (i >= adev->usec_timeout) {
1409 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1412 /* deassert IB preemption */
1413 WREG32(sdma_gfx_preempt, 0);
1415 /* deassert the preemption condition */
1416 amdgpu_ring_set_preempt_cond_exec(ring, true);
1420 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1421 struct amdgpu_irq_src *source,
1423 enum amdgpu_interrupt_state state)
1427 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1429 sdma_cntl = RREG32(reg_offset);
1430 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1431 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1432 WREG32(reg_offset, sdma_cntl);
1437 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1438 struct amdgpu_irq_src *source,
1439 struct amdgpu_iv_entry *entry)
1441 int instances, queue;
1442 uint32_t mes_queue_id = entry->src_data[0];
1444 DRM_DEBUG("IH: SDMA trap\n");
1446 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1447 struct amdgpu_mes_queue *queue;
1449 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1451 spin_lock(&adev->mes.queue_id_lock);
1452 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1454 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1455 amdgpu_fence_process(queue->ring);
1457 spin_unlock(&adev->mes.queue_id_lock);
1461 queue = entry->ring_id & 0xf;
1462 instances = (entry->ring_id & 0xf0) >> 4;
1463 if (instances > 1) {
1464 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1468 switch (entry->client_id) {
1469 case SOC21_IH_CLIENTID_GFX:
1472 amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1482 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1483 struct amdgpu_irq_src *source,
1484 struct amdgpu_iv_entry *entry)
1489 static int sdma_v6_0_set_clockgating_state(void *handle,
1490 enum amd_clockgating_state state)
1495 static int sdma_v6_0_set_powergating_state(void *handle,
1496 enum amd_powergating_state state)
1501 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1505 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1506 .name = "sdma_v6_0",
1507 .early_init = sdma_v6_0_early_init,
1509 .sw_init = sdma_v6_0_sw_init,
1510 .sw_fini = sdma_v6_0_sw_fini,
1511 .hw_init = sdma_v6_0_hw_init,
1512 .hw_fini = sdma_v6_0_hw_fini,
1513 .suspend = sdma_v6_0_suspend,
1514 .resume = sdma_v6_0_resume,
1515 .is_idle = sdma_v6_0_is_idle,
1516 .wait_for_idle = sdma_v6_0_wait_for_idle,
1517 .soft_reset = sdma_v6_0_soft_reset,
1518 .check_soft_reset = sdma_v6_0_check_soft_reset,
1519 .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1520 .set_powergating_state = sdma_v6_0_set_powergating_state,
1521 .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1524 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1525 .type = AMDGPU_RING_TYPE_SDMA,
1527 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1528 .support_64bit_ptrs = true,
1529 .vmhub = AMDGPU_GFXHUB_0,
1530 .get_rptr = sdma_v6_0_ring_get_rptr,
1531 .get_wptr = sdma_v6_0_ring_get_wptr,
1532 .set_wptr = sdma_v6_0_ring_set_wptr,
1534 5 + /* sdma_v6_0_ring_init_cond_exec */
1535 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1536 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1537 /* sdma_v6_0_ring_emit_vm_flush */
1538 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1539 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1540 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1541 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1542 .emit_ib = sdma_v6_0_ring_emit_ib,
1543 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1544 .emit_fence = sdma_v6_0_ring_emit_fence,
1545 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1546 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1547 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1548 .test_ring = sdma_v6_0_ring_test_ring,
1549 .test_ib = sdma_v6_0_ring_test_ib,
1550 .insert_nop = sdma_v6_0_ring_insert_nop,
1551 .pad_ib = sdma_v6_0_ring_pad_ib,
1552 .emit_wreg = sdma_v6_0_ring_emit_wreg,
1553 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1554 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1555 .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1556 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
1557 .preempt_ib = sdma_v6_0_ring_preempt_ib,
1560 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1564 for (i = 0; i < adev->sdma.num_instances; i++) {
1565 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1566 adev->sdma.instance[i].ring.me = i;
1570 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1571 .set = sdma_v6_0_set_trap_irq_state,
1572 .process = sdma_v6_0_process_trap_irq,
1575 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1576 .process = sdma_v6_0_process_illegal_inst_irq,
1579 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1581 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1582 adev->sdma.num_instances;
1583 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1584 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1588 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1590 * @ring: amdgpu_ring structure holding ring information
1591 * @src_offset: src GPU address
1592 * @dst_offset: dst GPU address
1593 * @byte_count: number of bytes to xfer
1595 * Copy GPU buffers using the DMA engine.
1596 * Used by the amdgpu ttm implementation to move pages if
1597 * registered as the asic copy callback.
1599 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1600 uint64_t src_offset,
1601 uint64_t dst_offset,
1602 uint32_t byte_count,
1605 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1606 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1607 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1608 ib->ptr[ib->length_dw++] = byte_count - 1;
1609 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1610 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1611 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1612 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1613 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1617 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1619 * @ring: amdgpu_ring structure holding ring information
1620 * @src_data: value to write to buffer
1621 * @dst_offset: dst GPU address
1622 * @byte_count: number of bytes to xfer
1624 * Fill GPU buffers using the DMA engine.
1626 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1628 uint64_t dst_offset,
1629 uint32_t byte_count)
1631 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1632 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1633 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1634 ib->ptr[ib->length_dw++] = src_data;
1635 ib->ptr[ib->length_dw++] = byte_count - 1;
1638 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1639 .copy_max_bytes = 0x400000,
1641 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1643 .fill_max_bytes = 0x400000,
1645 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1648 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1650 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1651 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1654 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1655 .copy_pte_num_dw = 7,
1656 .copy_pte = sdma_v6_0_vm_copy_pte,
1657 .write_pte = sdma_v6_0_vm_write_pte,
1658 .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1661 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1665 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1666 for (i = 0; i < adev->sdma.num_instances; i++) {
1667 adev->vm_manager.vm_pte_scheds[i] =
1668 &adev->sdma.instance[i].ring.sched;
1670 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1673 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1674 .type = AMD_IP_BLOCK_TYPE_SDMA,
1678 .funcs = &sdma_v6_0_ip_funcs,