drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
  51
  52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
  54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
  55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
  56
  57 #define SDMA1_REG_OFFSET 0x600
  58 #define SDMA3_REG_OFFSET 0x400
  59 #define SDMA0_HYP_DEC_REG_START 0x5880
  60 #define SDMA0_HYP_DEC_REG_END 0x5893
  61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  62
  63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  67
  68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  69 {
  70         u32 base;
  71
  72         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  73             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  74                 base = adev->reg_offset[GC_HWIP][0][1];
  75                 if (instance != 0)
  76                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  77         } else {
  78                 if (instance < 2) {
  79                         base = adev->reg_offset[GC_HWIP][0][0];
  80                         if (instance == 1)
  81                                 internal_offset += SDMA1_REG_OFFSET;
  82                 } else {
  83                         base = adev->reg_offset[GC_HWIP][0][2];
  84                         if (instance == 3)
  85                                 internal_offset += SDMA3_REG_OFFSET;
  86                 }
  87         }
  88
  89         return base + internal_offset;
  90 }
  91
  92 /**
  93  * sdma_v5_2_init_microcode - load ucode images from disk
  94  *
  95  * @adev: amdgpu_device pointer
  96  *
  97  * Use the firmware interface to load the ucode images into
  98  * the driver (not loaded into hw).
  99  * Returns 0 on success, error on failure.
 100  */
 101
 102 // emulation only, won't work on real chip
 103 // navi10 real chip need to use PSP to load firmware
 104 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 105 {
 106         const char *chip_name;
 107         char fw_name[40];
 108
 109         DRM_DEBUG("\n");
 110
 111         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 112         case IP_VERSION(5, 2, 0):
 113                 chip_name = "sienna_cichlid_sdma";
 114                 break;
 115         case IP_VERSION(5, 2, 2):
 116                 chip_name = "navy_flounder_sdma";
 117                 break;
 118         case IP_VERSION(5, 2, 1):
 119                 chip_name = "vangogh_sdma";
 120                 break;
 121         case IP_VERSION(5, 2, 4):
 122                 chip_name = "dimgrey_cavefish_sdma";
 123                 break;
 124         case IP_VERSION(5, 2, 5):
 125                 chip_name = "beige_goby_sdma";
 126                 break;
 127         case IP_VERSION(5, 2, 3):
 128                 chip_name = "yellow_carp_sdma";
 129                 break;
 130         case IP_VERSION(5, 2, 6):
 131                 chip_name = "sdma_5_2_6";
 132                 break;
 133         case IP_VERSION(5, 2, 7):
 134                 chip_name = "sdma_5_2_7";
 135                 break;
 136         default:
 137                 BUG();
 138         }
 139
 140         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
 141
 142         return amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
 143 }
 144
 145 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 146 {
 147         unsigned ret;
 148
 149         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 150         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 151         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 152         amdgpu_ring_write(ring, 1);
 153         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 154         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 155
 156         return ret;
 157 }
 158
 159 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 160                                            unsigned offset)
 161 {
 162         unsigned cur;
 163
 164         BUG_ON(offset > ring->buf_mask);
 165         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 166
 167         cur = (ring->wptr - 1) & ring->buf_mask;
 168         if (cur > offset)
 169                 ring->ring[offset] = cur - offset;
 170         else
 171                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 172 }
 173
 174 /**
 175  * sdma_v5_2_ring_get_rptr - get the current read pointer
 176  *
 177  * @ring: amdgpu ring pointer
 178  *
 179  * Get the current rptr from the hardware (NAVI10+).
 180  */
 181 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 182 {
 183         u64 *rptr;
 184
 185         /* XXX check if swapping is necessary on BE */
 186         rptr = (u64 *)ring->rptr_cpu_addr;
 187
 188         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 189         return ((*rptr) >> 2);
 190 }
 191
 192 /**
 193  * sdma_v5_2_ring_get_wptr - get the current write pointer
 194  *
 195  * @ring: amdgpu ring pointer
 196  *
 197  * Get the current wptr from the hardware (NAVI10+).
 198  */
 199 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 200 {
 201         struct amdgpu_device *adev = ring->adev;
 202         u64 wptr;
 203
 204         if (ring->use_doorbell) {
 205                 /* XXX check if swapping is necessary on BE */
 206                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 207                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 208         } else {
 209                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 210                 wptr = wptr << 32;
 211                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 212                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 213         }
 214
 215         return wptr >> 2;
 216 }
 217
 218 /**
 219  * sdma_v5_2_ring_set_wptr - commit the write pointer
 220  *
 221  * @ring: amdgpu ring pointer
 222  *
 223  * Write the wptr back to the hardware (NAVI10+).
 224  */
 225 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 226 {
 227         struct amdgpu_device *adev = ring->adev;
 228
 229         DRM_DEBUG("Setting write pointer\n");
 230         if (ring->use_doorbell) {
 231                 DRM_DEBUG("Using doorbell -- "
 232                                 "wptr_offs == 0x%08x "
 233                                 "lower_32_bits(ring->wptr << 2) == 0x%08x "
 234                                 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
 235                                 ring->wptr_offs,
 236                                 lower_32_bits(ring->wptr << 2),
 237                                 upper_32_bits(ring->wptr << 2));
 238                 /* XXX check if swapping is necessary on BE */
 239                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 240                              ring->wptr << 2);
 241                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 242                                 ring->doorbell_index, ring->wptr << 2);
 243                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 244         } else {
 245                 DRM_DEBUG("Not using doorbell -- "
 246                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 247                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 248                                 ring->me,
 249                                 lower_32_bits(ring->wptr << 2),
 250                                 ring->me,
 251                                 upper_32_bits(ring->wptr << 2));
 252                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 253                         lower_32_bits(ring->wptr << 2));
 254                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 255                         upper_32_bits(ring->wptr << 2));
 256         }
 257 }
 258
 259 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 260 {
 261         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 262         int i;
 263
 264         for (i = 0; i < count; i++)
 265                 if (sdma && sdma->burst_nop && (i == 0))
 266                         amdgpu_ring_write(ring, ring->funcs->nop |
 267                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 268                 else
 269                         amdgpu_ring_write(ring, ring->funcs->nop);
 270 }
 271
 272 /**
 273  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 274  *
 275  * @ring: amdgpu ring pointer
 276  * @job: job to retrieve vmid from
 277  * @ib: IB object to schedule
 278  * @flags: unused
 279  *
 280  * Schedule an IB in the DMA ring.
 281  */
 282 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 283                                    struct amdgpu_job *job,
 284                                    struct amdgpu_ib *ib,
 285                                    uint32_t flags)
 286 {
 287         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 288         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 289
 290         /* An IB packet must end on a 8 DW boundary--the next dword
 291          * must be on a 8-dword boundary. Our IB packet below is 6
 292          * dwords long, thus add x number of NOPs, such that, in
 293          * modular arithmetic,
 294          * wptr + 6 + x = 8k, k >= 0, which in C is,
 295          * (wptr + 6 + x) % 8 = 0.
 296          * The expression below, is a solution of x.
 297          */
 298         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 299
 300         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 301                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 302         /* base must be 32 byte aligned */
 303         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 304         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 305         amdgpu_ring_write(ring, ib->length_dw);
 306         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 307         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 308 }
 309
 310 /**
 311  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
 312  *
 313  * @ring: amdgpu ring pointer
 314  *
 315  * flush the IB by graphics cache rinse.
 316  */
 317 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
 318 {
 319         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
 320                             SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
 321                             SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 322                             SDMA_GCR_GLI_INV(1);
 323
 324         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 325         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 326         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 327         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 328                         SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 329         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 330                         SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 331         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 332                         SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 333 }
 334
 335 /**
 336  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 337  *
 338  * @ring: amdgpu ring pointer
 339  *
 340  * Emit an hdp flush packet on the requested DMA ring.
 341  */
 342 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 343 {
 344         struct amdgpu_device *adev = ring->adev;
 345         u32 ref_and_mask = 0;
 346         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 347
 348         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 349
 350         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 351                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 352                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 353         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 354         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 355         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 356         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 357         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 358                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 359 }
 360
 361 /**
 362  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 363  *
 364  * @ring: amdgpu ring pointer
 365  * @addr: address
 366  * @seq: sequence number
 367  * @flags: fence related flags
 368  *
 369  * Add a DMA fence packet to the ring to write
 370  * the fence seq number and DMA trap packet to generate
 371  * an interrupt if needed.
 372  */
 373 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 374                                       unsigned flags)
 375 {
 376         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 377         /* write the fence */
 378         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 379                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 380         /* zero in first two bits */
 381         BUG_ON(addr & 0x3);
 382         amdgpu_ring_write(ring, lower_32_bits(addr));
 383         amdgpu_ring_write(ring, upper_32_bits(addr));
 384         amdgpu_ring_write(ring, lower_32_bits(seq));
 385
 386         /* optionally write high bits as well */
 387         if (write64bit) {
 388                 addr += 4;
 389                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 390                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 391                 /* zero in first two bits */
 392                 BUG_ON(addr & 0x3);
 393                 amdgpu_ring_write(ring, lower_32_bits(addr));
 394                 amdgpu_ring_write(ring, upper_32_bits(addr));
 395                 amdgpu_ring_write(ring, upper_32_bits(seq));
 396         }
 397
 398         if ((flags & AMDGPU_FENCE_FLAG_INT)) {
 399                 uint32_t ctx = ring->is_mes_queue ?
 400                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 401                 /* generate an interrupt */
 402                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 403                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 404         }
 405 }
 406
 407
 408 /**
 409  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 410  *
 411  * @adev: amdgpu_device pointer
 412  *
 413  * Stop the gfx async dma ring buffers.
 414  */
 415 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 416 {
 417         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 418         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 419         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 420         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 421         u32 rb_cntl, ib_cntl;
 422         int i;
 423
 424         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 425             (adev->mman.buffer_funcs_ring == sdma1) ||
 426             (adev->mman.buffer_funcs_ring == sdma2) ||
 427             (adev->mman.buffer_funcs_ring == sdma3))
 428                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 429
 430         for (i = 0; i < adev->sdma.num_instances; i++) {
 431                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 432                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 433                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 434                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 435                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 436                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 437         }
 438 }
 439
 440 /**
 441  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 442  *
 443  * @adev: amdgpu_device pointer
 444  *
 445  * Stop the compute async dma queues.
 446  */
 447 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 448 {
 449         /* XXX todo */
 450 }
 451
 452 /**
 453  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
 454  *
 455  * @adev: amdgpu_device pointer
 456  * @enable: enable/disable the DMA MEs context switch.
 457  *
 458  * Halt or unhalt the async dma engines context switch.
 459  */
 460 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 461 {
 462         u32 f32_cntl, phase_quantum = 0;
 463         int i;
 464
 465         if (amdgpu_sdma_phase_quantum) {
 466                 unsigned value = amdgpu_sdma_phase_quantum;
 467                 unsigned unit = 0;
 468
 469                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 470                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 471                         value = (value + 1) >> 1;
 472                         unit++;
 473                 }
 474                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 475                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 476                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 477                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 478                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 479                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 480                         WARN_ONCE(1,
 481                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 482                                   value << unit);
 483                 }
 484                 phase_quantum =
 485                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 486                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 487         }
 488
 489         for (i = 0; i < adev->sdma.num_instances; i++) {
 490                 if (enable && amdgpu_sdma_phase_quantum) {
 491                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 492                                phase_quantum);
 493                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 494                                phase_quantum);
 495                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 496                                phase_quantum);
 497                 }
 498
 499                 if (!amdgpu_sriov_vf(adev)) {
 500                         f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 501                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 502                                         AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 503                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 504                 }
 505         }
 506
 507 }
 508
 509 /**
 510  * sdma_v5_2_enable - stop the async dma engines
 511  *
 512  * @adev: amdgpu_device pointer
 513  * @enable: enable/disable the DMA MEs.
 514  *
 515  * Halt or unhalt the async dma engines.
 516  */
 517 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 518 {
 519         u32 f32_cntl;
 520         int i;
 521
 522         if (!enable) {
 523                 sdma_v5_2_gfx_stop(adev);
 524                 sdma_v5_2_rlc_stop(adev);
 525         }
 526
 527         if (!amdgpu_sriov_vf(adev)) {
 528                 for (i = 0; i < adev->sdma.num_instances; i++) {
 529                         f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 530                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 531                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 532                 }
 533         }
 534 }
 535
 536 /**
 537  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 538  *
 539  * @adev: amdgpu_device pointer
 540  *
 541  * Set up the gfx DMA ring buffers and enable them.
 542  * Returns 0 for success, error for failure.
 543  */
 544 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 545 {
 546         struct amdgpu_ring *ring;
 547         u32 rb_cntl, ib_cntl;
 548         u32 rb_bufsz;
 549         u32 doorbell;
 550         u32 doorbell_offset;
 551         u32 temp;
 552         u32 wptr_poll_cntl;
 553         u64 wptr_gpu_addr;
 554         int i, r;
 555
 556         for (i = 0; i < adev->sdma.num_instances; i++) {
 557                 ring = &adev->sdma.instance[i].ring;
 558
 559                 if (!amdgpu_sriov_vf(adev))
 560                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 561
 562                 /* Set ring buffer size in dwords */
 563                 rb_bufsz = order_base_2(ring->ring_size / 4);
 564                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 565                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 566 #ifdef __BIG_ENDIAN
 567                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 568                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 569                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 570 #endif
 571                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 572
 573                 /* Initialize the ring buffer's read and write pointers */
 574                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 575                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 576                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 577                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 578
 579                 /* setup the wptr shadow polling */
 580                 wptr_gpu_addr = ring->wptr_gpu_addr;
 581                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 582                        lower_32_bits(wptr_gpu_addr));
 583                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 584                        upper_32_bits(wptr_gpu_addr));
 585                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
 586                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 587                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 588                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 589                                                F32_POLL_ENABLE, 1);
 590                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 591                        wptr_poll_cntl);
 592
 593                 /* set the wb address whether it's enabled or not */
 594                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 595                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 596                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 597                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 598
 599                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 600
 601                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 602                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 603
 604                 ring->wptr = 0;
 605
 606                 /* before programing wptr to a less value, need set minor_ptr_update first */
 607                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 608
 609                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 610                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 611                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 612                 }
 613
 614                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 615                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 616
 617                 if (ring->use_doorbell) {
 618                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 619                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 620                                         OFFSET, ring->doorbell_index);
 621                 } else {
 622                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 623                 }
 624                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 625                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 626
 627                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 628                                                       ring->doorbell_index,
 629                                                       adev->doorbell_index.sdma_doorbell_range);
 630
 631                 if (amdgpu_sriov_vf(adev))
 632                         sdma_v5_2_ring_set_wptr(ring);
 633
 634                 /* set minor_ptr_update to 0 after wptr programed */
 635
 636                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 637
 638                 /* SRIOV VF has no control of any of registers below */
 639                 if (!amdgpu_sriov_vf(adev)) {
 640                         /* set utc l1 enable flag always to 1 */
 641                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 642                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 643
 644                         /* enable MCBP */
 645                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 646                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 647
 648                         /* Set up RESP_MODE to non-copy addresses */
 649                         temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 650                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 651                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 652                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 653
 654                         /* program default cache read and write policy */
 655                         temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 656                         /* clean read policy and write policy bits */
 657                         temp &= 0xFF0FFF;
 658                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 659                                  (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 660                                  SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 661                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 662
 663                         /* unhalt engine */
 664                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 665                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 666                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 667                 }
 668
 669                 /* enable DMA RB */
 670                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 671                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 672
 673                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 674                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 675 #ifdef __BIG_ENDIAN
 676                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 677 #endif
 678                 /* enable DMA IBs */
 679                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 680
 681                 ring->sched.ready = true;
 682
 683                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 684                         sdma_v5_2_ctx_switch_enable(adev, true);
 685                         sdma_v5_2_enable(adev, true);
 686                 }
 687
 688                 r = amdgpu_ring_test_ring(ring);
 689                 if (r) {
 690                         ring->sched.ready = false;
 691                         return r;
 692                 }
 693
 694                 if (adev->mman.buffer_funcs_ring == ring)
 695                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 696         }
 697
 698         return 0;
 699 }
 700
 701 /**
 702  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 703  *
 704  * @adev: amdgpu_device pointer
 705  *
 706  * Set up the compute DMA queues and enable them.
 707  * Returns 0 for success, error for failure.
 708  */
 709 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 710 {
 711         return 0;
 712 }
 713
 714 /**
 715  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 716  *
 717  * @adev: amdgpu_device pointer
 718  *
 719  * Loads the sDMA0/1/2/3 ucode.
 720  * Returns 0 for success, -EINVAL if the ucode is not available.
 721  */
 722 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 723 {
 724         const struct sdma_firmware_header_v1_0 *hdr;
 725         const __le32 *fw_data;
 726         u32 fw_size;
 727         int i, j;
 728
 729         /* halt the MEs */
 730         sdma_v5_2_enable(adev, false);
 731
 732         for (i = 0; i < adev->sdma.num_instances; i++) {
 733                 if (!adev->sdma.instance[i].fw)
 734                         return -EINVAL;
 735
 736                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 737                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 738                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 739
 740                 fw_data = (const __le32 *)
 741                         (adev->sdma.instance[i].fw->data +
 742                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 743
 744                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 745
 746                 for (j = 0; j < fw_size; j++) {
 747                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 748                                 msleep(1);
 749                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 750                 }
 751
 752                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 753         }
 754
 755         return 0;
 756 }
 757
 758 static int sdma_v5_2_soft_reset(void *handle)
 759 {
 760         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 761         u32 grbm_soft_reset;
 762         u32 tmp;
 763         int i;
 764
 765         for (i = 0; i < adev->sdma.num_instances; i++) {
 766                 grbm_soft_reset = REG_SET_FIELD(0,
 767                                                 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 768                                                 1);
 769                 grbm_soft_reset <<= i;
 770
 771                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 772                 tmp |= grbm_soft_reset;
 773                 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 774                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 775                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 776
 777                 udelay(50);
 778
 779                 tmp &= ~grbm_soft_reset;
 780                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 781                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 782
 783                 udelay(50);
 784         }
 785
 786         return 0;
 787 }
 788
 789 /**
 790  * sdma_v5_2_start - setup and start the async dma engines
 791  *
 792  * @adev: amdgpu_device pointer
 793  *
 794  * Set up the DMA engines and enable them.
 795  * Returns 0 for success, error for failure.
 796  */
 797 static int sdma_v5_2_start(struct amdgpu_device *adev)
 798 {
 799         int r = 0;
 800
 801         if (amdgpu_sriov_vf(adev)) {
 802                 sdma_v5_2_ctx_switch_enable(adev, false);
 803                 sdma_v5_2_enable(adev, false);
 804
 805                 /* set RB registers */
 806                 r = sdma_v5_2_gfx_resume(adev);
 807                 return r;
 808         }
 809
 810         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 811                 r = sdma_v5_2_load_microcode(adev);
 812                 if (r)
 813                         return r;
 814
 815                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 816                 if (amdgpu_emu_mode == 1)
 817                         msleep(1000);
 818         }
 819
 820         /* TODO: check whether can submit a doorbell request to raise
 821          * a doorbell fence to exit gfxoff.
 822          */
 823         if (adev->in_s0ix)
 824                 amdgpu_gfx_off_ctrl(adev, false);
 825
 826         sdma_v5_2_soft_reset(adev);
 827         /* unhalt the MEs */
 828         sdma_v5_2_enable(adev, true);
 829         /* enable sdma ring preemption */
 830         sdma_v5_2_ctx_switch_enable(adev, true);
 831
 832         /* start the gfx rings and rlc compute queues */
 833         r = sdma_v5_2_gfx_resume(adev);
 834         if (adev->in_s0ix)
 835                 amdgpu_gfx_off_ctrl(adev, true);
 836         if (r)
 837                 return r;
 838         r = sdma_v5_2_rlc_resume(adev);
 839
 840         return r;
 841 }
 842
 843 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
 844                               struct amdgpu_mqd_prop *prop)
 845 {
 846         struct v10_sdma_mqd *m = mqd;
 847         uint64_t wb_gpu_addr;
 848
 849         m->sdmax_rlcx_rb_cntl =
 850                 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 851                 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 852                 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 853                 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
 854
 855         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 856         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 857
 858         m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
 859                                                   mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 860
 861         wb_gpu_addr = prop->wptr_gpu_addr;
 862         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 863         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 864
 865         wb_gpu_addr = prop->rptr_gpu_addr;
 866         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 867         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 868
 869         m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
 870                                                         mmSDMA0_GFX_IB_CNTL));
 871
 872         m->sdmax_rlcx_doorbell_offset =
 873                 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
 874
 875         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
 876
 877         return 0;
 878 }
 879
 880 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
 881 {
 882         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
 883         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
 884 }
 885
 886 /**
 887  * sdma_v5_2_ring_test_ring - simple async dma engine test
 888  *
 889  * @ring: amdgpu_ring structure holding ring information
 890  *
 891  * Test the DMA engine by writing using it to write an
 892  * value to memory.
 893  * Returns 0 for success, error for failure.
 894  */
 895 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 896 {
 897         struct amdgpu_device *adev = ring->adev;
 898         unsigned i;
 899         unsigned index;
 900         int r;
 901         u32 tmp;
 902         u64 gpu_addr;
 903         volatile uint32_t *cpu_ptr = NULL;
 904
 905         tmp = 0xCAFEDEAD;
 906
 907         if (ring->is_mes_queue) {
 908                 uint32_t offset = 0;
 909                 offset = amdgpu_mes_ctx_get_offs(ring,
 910                                          AMDGPU_MES_CTX_PADDING_OFFS);
 911                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 912                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 913                 *cpu_ptr = tmp;
 914         } else {
 915                 r = amdgpu_device_wb_get(adev, &index);
 916                 if (r) {
 917                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 918                         return r;
 919                 }
 920
 921                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 922                 adev->wb.wb[index] = cpu_to_le32(tmp);
 923         }
 924
 925         r = amdgpu_ring_alloc(ring, 20);
 926         if (r) {
 927                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 928                 amdgpu_device_wb_free(adev, index);
 929                 return r;
 930         }
 931
 932         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 933                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 934         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 935         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 936         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 937         amdgpu_ring_write(ring, 0xDEADBEEF);
 938         amdgpu_ring_commit(ring);
 939
 940         for (i = 0; i < adev->usec_timeout; i++) {
 941                 if (ring->is_mes_queue)
 942                         tmp = le32_to_cpu(*cpu_ptr);
 943                 else
 944                         tmp = le32_to_cpu(adev->wb.wb[index]);
 945                 if (tmp == 0xDEADBEEF)
 946                         break;
 947                 if (amdgpu_emu_mode == 1)
 948                         msleep(1);
 949                 else
 950                         udelay(1);
 951         }
 952
 953         if (i >= adev->usec_timeout)
 954                 r = -ETIMEDOUT;
 955
 956         if (!ring->is_mes_queue)
 957                 amdgpu_device_wb_free(adev, index);
 958
 959         return r;
 960 }
 961
 962 /**
 963  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 964  *
 965  * @ring: amdgpu_ring structure holding ring information
 966  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 967  *
 968  * Test a simple IB in the DMA ring.
 969  * Returns 0 on success, error on failure.
 970  */
 971 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 972 {
 973         struct amdgpu_device *adev = ring->adev;
 974         struct amdgpu_ib ib;
 975         struct dma_fence *f = NULL;
 976         unsigned index;
 977         long r;
 978         u32 tmp = 0;
 979         u64 gpu_addr;
 980         volatile uint32_t *cpu_ptr = NULL;
 981
 982         tmp = 0xCAFEDEAD;
 983         memset(&ib, 0, sizeof(ib));
 984
 985         if (ring->is_mes_queue) {
 986                 uint32_t offset = 0;
 987                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 988                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 989                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 990
 991                 offset = amdgpu_mes_ctx_get_offs(ring,
 992                                          AMDGPU_MES_CTX_PADDING_OFFS);
 993                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 994                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 995                 *cpu_ptr = tmp;
 996         } else {
 997                 r = amdgpu_device_wb_get(adev, &index);
 998                 if (r) {
 999                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1000                         return r;
1001                 }
1002
1003                 gpu_addr = adev->wb.gpu_addr + (index * 4);
1004                 adev->wb.wb[index] = cpu_to_le32(tmp);
1005
1006                 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1007                 if (r) {
1008                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1009                         goto err0;
1010                 }
1011         }
1012
1013         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1014                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1015         ib.ptr[1] = lower_32_bits(gpu_addr);
1016         ib.ptr[2] = upper_32_bits(gpu_addr);
1017         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1018         ib.ptr[4] = 0xDEADBEEF;
1019         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1020         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1021         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1022         ib.length_dw = 8;
1023
1024         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1025         if (r)
1026                 goto err1;
1027
1028         r = dma_fence_wait_timeout(f, false, timeout);
1029         if (r == 0) {
1030                 DRM_ERROR("amdgpu: IB test timed out\n");
1031                 r = -ETIMEDOUT;
1032                 goto err1;
1033         } else if (r < 0) {
1034                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1035                 goto err1;
1036         }
1037
1038         if (ring->is_mes_queue)
1039                 tmp = le32_to_cpu(*cpu_ptr);
1040         else
1041                 tmp = le32_to_cpu(adev->wb.wb[index]);
1042
1043         if (tmp == 0xDEADBEEF)
1044                 r = 0;
1045         else
1046                 r = -EINVAL;
1047
1048 err1:
1049         amdgpu_ib_free(adev, &ib, NULL);
1050         dma_fence_put(f);
1051 err0:
1052         if (!ring->is_mes_queue)
1053                 amdgpu_device_wb_free(adev, index);
1054         return r;
1055 }
1056
1057
1058 /**
1059  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1060  *
1061  * @ib: indirect buffer to fill with commands
1062  * @pe: addr of the page entry
1063  * @src: src addr to copy from
1064  * @count: number of page entries to update
1065  *
1066  * Update PTEs by copying them from the GART using sDMA.
1067  */
1068 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1069                                   uint64_t pe, uint64_t src,
1070                                   unsigned count)
1071 {
1072         unsigned bytes = count * 8;
1073
1074         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1075                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1076         ib->ptr[ib->length_dw++] = bytes - 1;
1077         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1078         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1079         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1080         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1081         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1082
1083 }
1084
1085 /**
1086  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1087  *
1088  * @ib: indirect buffer to fill with commands
1089  * @pe: addr of the page entry
1090  * @value: dst addr to write into pe
1091  * @count: number of page entries to update
1092  * @incr: increase next addr by incr bytes
1093  *
1094  * Update PTEs by writing them manually using sDMA.
1095  */
1096 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1097                                    uint64_t value, unsigned count,
1098                                    uint32_t incr)
1099 {
1100         unsigned ndw = count * 2;
1101
1102         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1103                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1104         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1105         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1106         ib->ptr[ib->length_dw++] = ndw - 1;
1107         for (; ndw > 0; ndw -= 2) {
1108                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1109                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1110                 value += incr;
1111         }
1112 }
1113
1114 /**
1115  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1116  *
1117  * @ib: indirect buffer to fill with commands
1118  * @pe: addr of the page entry
1119  * @addr: dst addr to write into pe
1120  * @count: number of page entries to update
1121  * @incr: increase next addr by incr bytes
1122  * @flags: access flags
1123  *
1124  * Update the page tables using sDMA.
1125  */
1126 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1127                                      uint64_t pe,
1128                                      uint64_t addr, unsigned count,
1129                                      uint32_t incr, uint64_t flags)
1130 {
1131         /* for physically contiguous pages (vram) */
1132         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1133         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1134         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1135         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1136         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1137         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1138         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1139         ib->ptr[ib->length_dw++] = incr; /* increment size */
1140         ib->ptr[ib->length_dw++] = 0;
1141         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1142 }
1143
1144 /**
1145  * sdma_v5_2_ring_pad_ib - pad the IB
1146  *
1147  * @ib: indirect buffer to fill with padding
1148  * @ring: amdgpu_ring structure holding ring information
1149  *
1150  * Pad the IB with NOPs to a boundary multiple of 8.
1151  */
1152 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1153 {
1154         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1155         u32 pad_count;
1156         int i;
1157
1158         pad_count = (-ib->length_dw) & 0x7;
1159         for (i = 0; i < pad_count; i++)
1160                 if (sdma && sdma->burst_nop && (i == 0))
1161                         ib->ptr[ib->length_dw++] =
1162                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1163                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1164                 else
1165                         ib->ptr[ib->length_dw++] =
1166                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1167 }
1168
1169
1170 /**
1171  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1172  *
1173  * @ring: amdgpu_ring pointer
1174  *
1175  * Make sure all previous operations are completed (CIK).
1176  */
1177 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1178 {
1179         uint32_t seq = ring->fence_drv.sync_seq;
1180         uint64_t addr = ring->fence_drv.gpu_addr;
1181
1182         /* wait for idle */
1183         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1184                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1185                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1186                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1187         amdgpu_ring_write(ring, addr & 0xfffffffc);
1188         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1189         amdgpu_ring_write(ring, seq); /* reference */
1190         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1191         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1192                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1193 }
1194
1195
1196 /**
1197  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1198  *
1199  * @ring: amdgpu_ring pointer
1200  * @vmid: vmid number to use
1201  * @pd_addr: address
1202  *
1203  * Update the page table base and flush the VM TLB
1204  * using sDMA.
1205  */
1206 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1207                                          unsigned vmid, uint64_t pd_addr)
1208 {
1209         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1210 }
1211
1212 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1213                                      uint32_t reg, uint32_t val)
1214 {
1215         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1216                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1217         amdgpu_ring_write(ring, reg);
1218         amdgpu_ring_write(ring, val);
1219 }
1220
1221 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1222                                          uint32_t val, uint32_t mask)
1223 {
1224         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1225                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1226                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1227         amdgpu_ring_write(ring, reg << 2);
1228         amdgpu_ring_write(ring, 0);
1229         amdgpu_ring_write(ring, val); /* reference */
1230         amdgpu_ring_write(ring, mask); /* mask */
1231         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1232                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1233 }
1234
1235 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1236                                                    uint32_t reg0, uint32_t reg1,
1237                                                    uint32_t ref, uint32_t mask)
1238 {
1239         amdgpu_ring_emit_wreg(ring, reg0, ref);
1240         /* wait for a cycle to reset vm_inv_eng*_ack */
1241         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1242         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1243 }
1244
1245 static int sdma_v5_2_early_init(void *handle)
1246 {
1247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1248
1249         sdma_v5_2_set_ring_funcs(adev);
1250         sdma_v5_2_set_buffer_funcs(adev);
1251         sdma_v5_2_set_vm_pte_funcs(adev);
1252         sdma_v5_2_set_irq_funcs(adev);
1253         sdma_v5_2_set_mqd_funcs(adev);
1254
1255         return 0;
1256 }
1257
1258 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1259 {
1260         switch (seq_num) {
1261         case 0:
1262                 return SOC15_IH_CLIENTID_SDMA0;
1263         case 1:
1264                 return SOC15_IH_CLIENTID_SDMA1;
1265         case 2:
1266                 return SOC15_IH_CLIENTID_SDMA2;
1267         case 3:
1268                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1269         default:
1270                 break;
1271         }
1272         return -EINVAL;
1273 }
1274
1275 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1276 {
1277         switch (seq_num) {
1278         case 0:
1279                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1280         case 1:
1281                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1282         case 2:
1283                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1284         case 3:
1285                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1286         default:
1287                 break;
1288         }
1289         return -EINVAL;
1290 }
1291
1292 static int sdma_v5_2_sw_init(void *handle)
1293 {
1294         struct amdgpu_ring *ring;
1295         int r, i;
1296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297
1298         /* SDMA trap event */
1299         for (i = 0; i < adev->sdma.num_instances; i++) {
1300                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1301                                       sdma_v5_2_seq_to_trap_id(i),
1302                                       &adev->sdma.trap_irq);
1303                 if (r)
1304                         return r;
1305         }
1306
1307         r = sdma_v5_2_init_microcode(adev);
1308         if (r) {
1309                 DRM_ERROR("Failed to load sdma firmware!\n");
1310                 return r;
1311         }
1312
1313         for (i = 0; i < adev->sdma.num_instances; i++) {
1314                 ring = &adev->sdma.instance[i].ring;
1315                 ring->ring_obj = NULL;
1316                 ring->use_doorbell = true;
1317                 ring->me = i;
1318
1319                 DRM_INFO("use_doorbell being set to: [%s]\n",
1320                                 ring->use_doorbell?"true":"false");
1321
1322                 ring->doorbell_index =
1323                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1324
1325                 sprintf(ring->name, "sdma%d", i);
1326                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1327                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1328                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1329                 if (r)
1330                         return r;
1331         }
1332
1333         return r;
1334 }
1335
1336 static int sdma_v5_2_sw_fini(void *handle)
1337 {
1338         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339         int i;
1340
1341         for (i = 0; i < adev->sdma.num_instances; i++)
1342                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1343
1344         amdgpu_sdma_destroy_inst_ctx(adev, true);
1345
1346         return 0;
1347 }
1348
1349 static int sdma_v5_2_hw_init(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352
1353         return sdma_v5_2_start(adev);
1354 }
1355
1356 static int sdma_v5_2_hw_fini(void *handle)
1357 {
1358         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359
1360         if (amdgpu_sriov_vf(adev))
1361                 return 0;
1362
1363         sdma_v5_2_ctx_switch_enable(adev, false);
1364         sdma_v5_2_enable(adev, false);
1365
1366         return 0;
1367 }
1368
1369 static int sdma_v5_2_suspend(void *handle)
1370 {
1371         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372
1373         return sdma_v5_2_hw_fini(adev);
1374 }
1375
1376 static int sdma_v5_2_resume(void *handle)
1377 {
1378         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1379
1380         return sdma_v5_2_hw_init(adev);
1381 }
1382
1383 static bool sdma_v5_2_is_idle(void *handle)
1384 {
1385         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1386         u32 i;
1387
1388         for (i = 0; i < adev->sdma.num_instances; i++) {
1389                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1390
1391                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1392                         return false;
1393         }
1394
1395         return true;
1396 }
1397
1398 static int sdma_v5_2_wait_for_idle(void *handle)
1399 {
1400         unsigned i;
1401         u32 sdma0, sdma1, sdma2, sdma3;
1402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403
1404         for (i = 0; i < adev->usec_timeout; i++) {
1405                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1406                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1407                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1408                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1409
1410                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1411                         return 0;
1412                 udelay(1);
1413         }
1414         return -ETIMEDOUT;
1415 }
1416
1417 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1418 {
1419         int i, r = 0;
1420         struct amdgpu_device *adev = ring->adev;
1421         u32 index = 0;
1422         u64 sdma_gfx_preempt;
1423
1424         amdgpu_sdma_get_index_from_ring(ring, &index);
1425         sdma_gfx_preempt =
1426                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1427
1428         /* assert preemption condition */
1429         amdgpu_ring_set_preempt_cond_exec(ring, false);
1430
1431         /* emit the trailing fence */
1432         ring->trail_seq += 1;
1433         amdgpu_ring_alloc(ring, 10);
1434         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1435                                   ring->trail_seq, 0);
1436         amdgpu_ring_commit(ring);
1437
1438         /* assert IB preemption */
1439         WREG32(sdma_gfx_preempt, 1);
1440
1441         /* poll the trailing fence */
1442         for (i = 0; i < adev->usec_timeout; i++) {
1443                 if (ring->trail_seq ==
1444                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1445                         break;
1446                 udelay(1);
1447         }
1448
1449         if (i >= adev->usec_timeout) {
1450                 r = -EINVAL;
1451                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1452         }
1453
1454         /* deassert IB preemption */
1455         WREG32(sdma_gfx_preempt, 0);
1456
1457         /* deassert the preemption condition */
1458         amdgpu_ring_set_preempt_cond_exec(ring, true);
1459         return r;
1460 }
1461
1462 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1463                                         struct amdgpu_irq_src *source,
1464                                         unsigned type,
1465                                         enum amdgpu_interrupt_state state)
1466 {
1467         u32 sdma_cntl;
1468         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1469
1470         if (!amdgpu_sriov_vf(adev)) {
1471                 sdma_cntl = RREG32(reg_offset);
1472                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1473                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1474                 WREG32(reg_offset, sdma_cntl);
1475         }
1476
1477         return 0;
1478 }
1479
1480 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1481                                       struct amdgpu_irq_src *source,
1482                                       struct amdgpu_iv_entry *entry)
1483 {
1484         uint32_t mes_queue_id = entry->src_data[0];
1485
1486         DRM_DEBUG("IH: SDMA trap\n");
1487
1488         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1489                 struct amdgpu_mes_queue *queue;
1490
1491                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1492
1493                 spin_lock(&adev->mes.queue_id_lock);
1494                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1495                 if (queue) {
1496                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1497                         amdgpu_fence_process(queue->ring);
1498                 }
1499                 spin_unlock(&adev->mes.queue_id_lock);
1500                 return 0;
1501         }
1502
1503         switch (entry->client_id) {
1504         case SOC15_IH_CLIENTID_SDMA0:
1505                 switch (entry->ring_id) {
1506                 case 0:
1507                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1508                         break;
1509                 case 1:
1510                         /* XXX compute */
1511                         break;
1512                 case 2:
1513                         /* XXX compute */
1514                         break;
1515                 case 3:
1516                         /* XXX page queue*/
1517                         break;
1518                 }
1519                 break;
1520         case SOC15_IH_CLIENTID_SDMA1:
1521                 switch (entry->ring_id) {
1522                 case 0:
1523                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1524                         break;
1525                 case 1:
1526                         /* XXX compute */
1527                         break;
1528                 case 2:
1529                         /* XXX compute */
1530                         break;
1531                 case 3:
1532                         /* XXX page queue*/
1533                         break;
1534                 }
1535                 break;
1536         case SOC15_IH_CLIENTID_SDMA2:
1537                 switch (entry->ring_id) {
1538                 case 0:
1539                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1540                         break;
1541                 case 1:
1542                         /* XXX compute */
1543                         break;
1544                 case 2:
1545                         /* XXX compute */
1546                         break;
1547                 case 3:
1548                         /* XXX page queue*/
1549                         break;
1550                 }
1551                 break;
1552         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1553                 switch (entry->ring_id) {
1554                 case 0:
1555                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1556                         break;
1557                 case 1:
1558                         /* XXX compute */
1559                         break;
1560                 case 2:
1561                         /* XXX compute */
1562                         break;
1563                 case 3:
1564                         /* XXX page queue*/
1565                         break;
1566                 }
1567                 break;
1568         }
1569         return 0;
1570 }
1571
1572 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1573                                               struct amdgpu_irq_src *source,
1574                                               struct amdgpu_iv_entry *entry)
1575 {
1576         return 0;
1577 }
1578
1579 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1580                                                        bool enable)
1581 {
1582         uint32_t data, def;
1583         int i;
1584
1585         for (i = 0; i < adev->sdma.num_instances; i++) {
1586
1587                 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1588                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1589
1590                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1591                         /* Enable sdma clock gating */
1592                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1593                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1594                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1595                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1596                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1597                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1598                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1599                         if (def != data)
1600                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1601                 } else {
1602                         /* Disable sdma clock gating */
1603                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1604                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1605                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1606                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1607                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1608                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1609                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1610                         if (def != data)
1611                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1612                 }
1613         }
1614 }
1615
1616 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1617                                                       bool enable)
1618 {
1619         uint32_t data, def;
1620         int i;
1621
1622         for (i = 0; i < adev->sdma.num_instances; i++) {
1623
1624                 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1625                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1626
1627                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1628                         /* Enable sdma mem light sleep */
1629                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1630                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1631                         if (def != data)
1632                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1633
1634                 } else {
1635                         /* Disable sdma mem light sleep */
1636                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1637                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1638                         if (def != data)
1639                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1640
1641                 }
1642         }
1643 }
1644
1645 static int sdma_v5_2_set_clockgating_state(void *handle,
1646                                            enum amd_clockgating_state state)
1647 {
1648         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1649
1650         if (amdgpu_sriov_vf(adev))
1651                 return 0;
1652
1653         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1654         case IP_VERSION(5, 2, 0):
1655         case IP_VERSION(5, 2, 2):
1656         case IP_VERSION(5, 2, 1):
1657         case IP_VERSION(5, 2, 4):
1658         case IP_VERSION(5, 2, 5):
1659         case IP_VERSION(5, 2, 6):
1660         case IP_VERSION(5, 2, 3):
1661                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1662                                 state == AMD_CG_STATE_GATE);
1663                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1664                                 state == AMD_CG_STATE_GATE);
1665                 break;
1666         default:
1667                 break;
1668         }
1669
1670         return 0;
1671 }
1672
1673 static int sdma_v5_2_set_powergating_state(void *handle,
1674                                           enum amd_powergating_state state)
1675 {
1676         return 0;
1677 }
1678
1679 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
1680 {
1681         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1682         int data;
1683
1684         if (amdgpu_sriov_vf(adev))
1685                 *flags = 0;
1686
1687         /* AMD_CG_SUPPORT_SDMA_MGCG */
1688         data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1689         if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1690                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1691
1692         /* AMD_CG_SUPPORT_SDMA_LS */
1693         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1694         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1695                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1696 }
1697
1698 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1699         .name = "sdma_v5_2",
1700         .early_init = sdma_v5_2_early_init,
1701         .late_init = NULL,
1702         .sw_init = sdma_v5_2_sw_init,
1703         .sw_fini = sdma_v5_2_sw_fini,
1704         .hw_init = sdma_v5_2_hw_init,
1705         .hw_fini = sdma_v5_2_hw_fini,
1706         .suspend = sdma_v5_2_suspend,
1707         .resume = sdma_v5_2_resume,
1708         .is_idle = sdma_v5_2_is_idle,
1709         .wait_for_idle = sdma_v5_2_wait_for_idle,
1710         .soft_reset = sdma_v5_2_soft_reset,
1711         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1712         .set_powergating_state = sdma_v5_2_set_powergating_state,
1713         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1714 };
1715
1716 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1717         .type = AMDGPU_RING_TYPE_SDMA,
1718         .align_mask = 0xf,
1719         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1720         .support_64bit_ptrs = true,
1721         .secure_submission_supported = true,
1722         .vmhub = AMDGPU_GFXHUB_0,
1723         .get_rptr = sdma_v5_2_ring_get_rptr,
1724         .get_wptr = sdma_v5_2_ring_get_wptr,
1725         .set_wptr = sdma_v5_2_ring_set_wptr,
1726         .emit_frame_size =
1727                 5 + /* sdma_v5_2_ring_init_cond_exec */
1728                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1729                 3 + /* hdp_invalidate */
1730                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1731                 /* sdma_v5_2_ring_emit_vm_flush */
1732                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1733                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1734                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1735         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1736         .emit_ib = sdma_v5_2_ring_emit_ib,
1737         .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1738         .emit_fence = sdma_v5_2_ring_emit_fence,
1739         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1740         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1741         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1742         .test_ring = sdma_v5_2_ring_test_ring,
1743         .test_ib = sdma_v5_2_ring_test_ib,
1744         .insert_nop = sdma_v5_2_ring_insert_nop,
1745         .pad_ib = sdma_v5_2_ring_pad_ib,
1746         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1747         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1748         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1749         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1750         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1751         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1752 };
1753
1754 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1755 {
1756         int i;
1757
1758         for (i = 0; i < adev->sdma.num_instances; i++) {
1759                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1760                 adev->sdma.instance[i].ring.me = i;
1761         }
1762 }
1763
1764 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1765         .set = sdma_v5_2_set_trap_irq_state,
1766         .process = sdma_v5_2_process_trap_irq,
1767 };
1768
1769 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1770         .process = sdma_v5_2_process_illegal_inst_irq,
1771 };
1772
1773 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1774 {
1775         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1776                                         adev->sdma.num_instances;
1777         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1778         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1779 }
1780
1781 /**
1782  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1783  *
1784  * @ib: indirect buffer to copy to
1785  * @src_offset: src GPU address
1786  * @dst_offset: dst GPU address
1787  * @byte_count: number of bytes to xfer
1788  * @tmz: if a secure copy should be used
1789  *
1790  * Copy GPU buffers using the DMA engine.
1791  * Used by the amdgpu ttm implementation to move pages if
1792  * registered as the asic copy callback.
1793  */
1794 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1795                                        uint64_t src_offset,
1796                                        uint64_t dst_offset,
1797                                        uint32_t byte_count,
1798                                        bool tmz)
1799 {
1800         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1801                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1802                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1803         ib->ptr[ib->length_dw++] = byte_count - 1;
1804         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1805         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1806         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1807         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1808         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1809 }
1810
1811 /**
1812  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1813  *
1814  * @ib: indirect buffer to fill
1815  * @src_data: value to write to buffer
1816  * @dst_offset: dst GPU address
1817  * @byte_count: number of bytes to xfer
1818  *
1819  * Fill GPU buffers using the DMA engine.
1820  */
1821 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1822                                        uint32_t src_data,
1823                                        uint64_t dst_offset,
1824                                        uint32_t byte_count)
1825 {
1826         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1827         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1828         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1829         ib->ptr[ib->length_dw++] = src_data;
1830         ib->ptr[ib->length_dw++] = byte_count - 1;
1831 }
1832
1833 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1834         .copy_max_bytes = 0x400000,
1835         .copy_num_dw = 7,
1836         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1837
1838         .fill_max_bytes = 0x400000,
1839         .fill_num_dw = 5,
1840         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1841 };
1842
1843 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1844 {
1845         if (adev->mman.buffer_funcs == NULL) {
1846                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1847                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1848         }
1849 }
1850
1851 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1852         .copy_pte_num_dw = 7,
1853         .copy_pte = sdma_v5_2_vm_copy_pte,
1854         .write_pte = sdma_v5_2_vm_write_pte,
1855         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1856 };
1857
1858 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1859 {
1860         unsigned i;
1861
1862         if (adev->vm_manager.vm_pte_funcs == NULL) {
1863                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1864                 for (i = 0; i < adev->sdma.num_instances; i++) {
1865                         adev->vm_manager.vm_pte_scheds[i] =
1866                                 &adev->sdma.instance[i].ring.sched;
1867                 }
1868                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1869         }
1870 }
1871
1872 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1873         .type = AMD_IP_BLOCK_TYPE_SDMA,
1874         .major = 5,
1875         .minor = 2,
1876         .rev = 0,
1877         .funcs = &sdma_v5_2_ip_funcs,
1878 };