drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44 #include <linux/module.h>
  45
  46 #include <drm/drm_drv.h>
  47 #include <drm/ttm/ttm_bo_api.h>
  48 #include <drm/ttm/ttm_bo_driver.h>
  49 #include <drm/ttm/ttm_placement.h>
  50 #include <drm/ttm/ttm_range_manager.h>
  51
  52 #include <drm/amdgpu_drm.h>
  53 #include <drm/drm_drv.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_atomfirmware.h"
  62 #include "amdgpu_res_cursor.h"
  63 #include "bif/bif_4_1_d.h"
  64
  65 MODULE_IMPORT_NS(DMA_BUF);
  66
  67 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  68
  69 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  70                                    struct ttm_tt *ttm,
  71                                    struct ttm_resource *bo_mem);
  72 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  73                                       struct ttm_tt *ttm);
  74
  75 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  76                                     unsigned int type,
  77                                     uint64_t size_in_page)
  78 {
  79         return ttm_range_man_init(&adev->mman.bdev, type,
  80                                   false, size_in_page);
  81 }
  82
  83 /**
  84  * amdgpu_evict_flags - Compute placement flags
  85  *
  86  * @bo: The buffer object to evict
  87  * @placement: Possible destination(s) for evicted BO
  88  *
  89  * Fill in placement data when ttm_bo_evict() is called
  90  */
  91 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  92                                 struct ttm_placement *placement)
  93 {
  94         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  95         struct amdgpu_bo *abo;
  96         static const struct ttm_place placements = {
  97                 .fpfn = 0,
  98                 .lpfn = 0,
  99                 .mem_type = TTM_PL_SYSTEM,
 100                 .flags = 0
 101         };
 102
 103         /* Don't handle scatter gather BOs */
 104         if (bo->type == ttm_bo_type_sg) {
 105                 placement->num_placement = 0;
 106                 placement->num_busy_placement = 0;
 107                 return;
 108         }
 109
 110         /* Object isn't an AMDGPU object so ignore */
 111         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 112                 placement->placement = &placements;
 113                 placement->busy_placement = &placements;
 114                 placement->num_placement = 1;
 115                 placement->num_busy_placement = 1;
 116                 return;
 117         }
 118
 119         abo = ttm_to_amdgpu_bo(bo);
 120         if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
 121                 placement->num_placement = 0;
 122                 placement->num_busy_placement = 0;
 123                 return;
 124         }
 125
 126         switch (bo->resource->mem_type) {
 127         case AMDGPU_PL_GDS:
 128         case AMDGPU_PL_GWS:
 129         case AMDGPU_PL_OA:
 130                 placement->num_placement = 0;
 131                 placement->num_busy_placement = 0;
 132                 return;
 133
 134         case TTM_PL_VRAM:
 135                 if (!adev->mman.buffer_funcs_enabled) {
 136                         /* Move to system memory */
 137                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 138                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 139                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 140                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 141
 142                         /* Try evicting to the CPU inaccessible part of VRAM
 143                          * first, but only set GTT as busy placement, so this
 144                          * BO will be evicted to GTT rather than causing other
 145                          * BOs to be evicted from VRAM
 146                          */
 147                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 148                                                         AMDGPU_GEM_DOMAIN_GTT |
 149                                                         AMDGPU_GEM_DOMAIN_CPU);
 150                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 151                         abo->placements[0].lpfn = 0;
 152                         abo->placement.busy_placement = &abo->placements[1];
 153                         abo->placement.num_busy_placement = 1;
 154                 } else {
 155                         /* Move to GTT memory */
 156                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
 157                                                         AMDGPU_GEM_DOMAIN_CPU);
 158                 }
 159                 break;
 160         case TTM_PL_TT:
 161         case AMDGPU_PL_PREEMPT:
 162         default:
 163                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 164                 break;
 165         }
 166         *placement = abo->placement;
 167 }
 168
 169 /**
 170  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 171  * @bo: buffer object to map
 172  * @mem: memory object to map
 173  * @mm_cur: range to map
 174  * @window: which GART window to use
 175  * @ring: DMA ring to use for the copy
 176  * @tmz: if we should setup a TMZ enabled mapping
 177  * @size: in number of bytes to map, out number of bytes mapped
 178  * @addr: resulting address inside the MC address space
 179  *
 180  * Setup one of the GART windows to access a specific piece of memory or return
 181  * the physical address for local memory.
 182  */
 183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 184                                  struct ttm_resource *mem,
 185                                  struct amdgpu_res_cursor *mm_cur,
 186                                  unsigned window, struct amdgpu_ring *ring,
 187                                  bool tmz, uint64_t *size, uint64_t *addr)
 188 {
 189         struct amdgpu_device *adev = ring->adev;
 190         unsigned offset, num_pages, num_dw, num_bytes;
 191         uint64_t src_addr, dst_addr;
 192         struct dma_fence *fence;
 193         struct amdgpu_job *job;
 194         void *cpu_addr;
 195         uint64_t flags;
 196         unsigned int i;
 197         int r;
 198
 199         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 200                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 201
 202         if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
 203                 return -EINVAL;
 204
 205         /* Map only what can't be accessed directly */
 206         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 207                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 208                         mm_cur->start;
 209                 return 0;
 210         }
 211
 212
 213         /*
 214          * If start begins at an offset inside the page, then adjust the size
 215          * and addr accordingly
 216          */
 217         offset = mm_cur->start & ~PAGE_MASK;
 218
 219         num_pages = PFN_UP(*size + offset);
 220         num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
 221
 222         *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
 223
 224         *addr = adev->gmc.gart_start;
 225         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 226                 AMDGPU_GPU_PAGE_SIZE;
 227         *addr += offset;
 228
 229         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 230         num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 231
 232         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 233                                      AMDGPU_IB_POOL_DELAYED, &job);
 234         if (r)
 235                 return r;
 236
 237         src_addr = num_dw * 4;
 238         src_addr += job->ibs[0].gpu_addr;
 239
 240         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 241         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 242         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 243                                 dst_addr, num_bytes, false);
 244
 245         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 246         WARN_ON(job->ibs[0].length_dw > num_dw);
 247
 248         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 249         if (tmz)
 250                 flags |= AMDGPU_PTE_TMZ;
 251
 252         cpu_addr = &job->ibs[0].ptr[num_dw];
 253
 254         if (mem->mem_type == TTM_PL_TT) {
 255                 dma_addr_t *dma_addr;
 256
 257                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 258                 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
 259         } else {
 260                 dma_addr_t dma_address;
 261
 262                 dma_address = mm_cur->start;
 263                 dma_address += adev->vm_manager.vram_base_offset;
 264
 265                 for (i = 0; i < num_pages; ++i) {
 266                         amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
 267                                         flags, cpu_addr);
 268                         dma_address += PAGE_SIZE;
 269                 }
 270         }
 271
 272         r = amdgpu_job_submit(job, &adev->mman.entity,
 273                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 274         if (r)
 275                 goto error_free;
 276
 277         dma_fence_put(fence);
 278
 279         return r;
 280
 281 error_free:
 282         amdgpu_job_free(job);
 283         return r;
 284 }
 285
 286 /**
 287  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 288  * @adev: amdgpu device
 289  * @src: buffer/address where to read from
 290  * @dst: buffer/address where to write to
 291  * @size: number of bytes to copy
 292  * @tmz: if a secure copy should be used
 293  * @resv: resv object to sync to
 294  * @f: Returns the last fence if multiple jobs are submitted.
 295  *
 296  * The function copies @size bytes from {src->mem + src->offset} to
 297  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 298  * move and different for a BO to BO copy.
 299  *
 300  */
 301 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 302                                const struct amdgpu_copy_mem *src,
 303                                const struct amdgpu_copy_mem *dst,
 304                                uint64_t size, bool tmz,
 305                                struct dma_resv *resv,
 306                                struct dma_fence **f)
 307 {
 308         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 309         struct amdgpu_res_cursor src_mm, dst_mm;
 310         struct dma_fence *fence = NULL;
 311         int r = 0;
 312
 313         if (!adev->mman.buffer_funcs_enabled) {
 314                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 315                 return -EINVAL;
 316         }
 317
 318         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 319         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 320
 321         mutex_lock(&adev->mman.gtt_window_lock);
 322         while (src_mm.remaining) {
 323                 uint64_t from, to, cur_size;
 324                 struct dma_fence *next;
 325
 326                 /* Never copy more than 256MiB at once to avoid a timeout */
 327                 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
 328
 329                 /* Map src to window 0 and dst to window 1. */
 330                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 331                                           0, ring, tmz, &cur_size, &from);
 332                 if (r)
 333                         goto error;
 334
 335                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 336                                           1, ring, tmz, &cur_size, &to);
 337                 if (r)
 338                         goto error;
 339
 340                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 341                                        resv, &next, false, true, tmz);
 342                 if (r)
 343                         goto error;
 344
 345                 dma_fence_put(fence);
 346                 fence = next;
 347
 348                 amdgpu_res_next(&src_mm, cur_size);
 349                 amdgpu_res_next(&dst_mm, cur_size);
 350         }
 351 error:
 352         mutex_unlock(&adev->mman.gtt_window_lock);
 353         if (f)
 354                 *f = dma_fence_get(fence);
 355         dma_fence_put(fence);
 356         return r;
 357 }
 358
 359 /*
 360  * amdgpu_move_blit - Copy an entire buffer to another buffer
 361  *
 362  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 363  * help move buffers to and from VRAM.
 364  */
 365 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 366                             bool evict,
 367                             struct ttm_resource *new_mem,
 368                             struct ttm_resource *old_mem)
 369 {
 370         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 371         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 372         struct amdgpu_copy_mem src, dst;
 373         struct dma_fence *fence = NULL;
 374         int r;
 375
 376         src.bo = bo;
 377         dst.bo = bo;
 378         src.mem = old_mem;
 379         dst.mem = new_mem;
 380         src.offset = 0;
 381         dst.offset = 0;
 382
 383         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 384                                        new_mem->num_pages << PAGE_SHIFT,
 385                                        amdgpu_bo_encrypted(abo),
 386                                        bo->base.resv, &fence);
 387         if (r)
 388                 goto error;
 389
 390         /* clear the space being freed */
 391         if (old_mem->mem_type == TTM_PL_VRAM &&
 392             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 393                 struct dma_fence *wipe_fence = NULL;
 394
 395                 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence);
 396                 if (r) {
 397                         goto error;
 398                 } else if (wipe_fence) {
 399                         dma_fence_put(fence);
 400                         fence = wipe_fence;
 401                 }
 402         }
 403
 404         /* Always block for VM page tables before committing the new location */
 405         if (bo->type == ttm_bo_type_kernel)
 406                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 407         else
 408                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 409         dma_fence_put(fence);
 410         return r;
 411
 412 error:
 413         if (fence)
 414                 dma_fence_wait(fence, false);
 415         dma_fence_put(fence);
 416         return r;
 417 }
 418
 419 /*
 420  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 421  *
 422  * Called by amdgpu_bo_move()
 423  */
 424 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 425                                struct ttm_resource *mem)
 426 {
 427         u64 mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 428         struct amdgpu_res_cursor cursor;
 429         u64 end;
 430
 431         if (mem->mem_type == TTM_PL_SYSTEM ||
 432             mem->mem_type == TTM_PL_TT)
 433                 return true;
 434         if (mem->mem_type != TTM_PL_VRAM)
 435                 return false;
 436
 437         amdgpu_res_first(mem, 0, mem_size, &cursor);
 438         end = cursor.start + cursor.size;
 439         while (cursor.remaining) {
 440                 amdgpu_res_next(&cursor, cursor.size);
 441
 442                 if (!cursor.remaining)
 443                         break;
 444
 445                 /* ttm_resource_ioremap only supports contiguous memory */
 446                 if (end != cursor.start)
 447                         return false;
 448
 449                 end = cursor.start + cursor.size;
 450         }
 451
 452         return end <= adev->gmc.visible_vram_size;
 453 }
 454
 455 /*
 456  * amdgpu_bo_move - Move a buffer object to a new memory location
 457  *
 458  * Called by ttm_bo_handle_move_mem()
 459  */
 460 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 461                           struct ttm_operation_ctx *ctx,
 462                           struct ttm_resource *new_mem,
 463                           struct ttm_place *hop)
 464 {
 465         struct amdgpu_device *adev;
 466         struct amdgpu_bo *abo;
 467         struct ttm_resource *old_mem = bo->resource;
 468         int r;
 469
 470         if (new_mem->mem_type == TTM_PL_TT ||
 471             new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 472                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 473                 if (r)
 474                         return r;
 475         }
 476
 477         /* Can't move a pinned BO */
 478         abo = ttm_to_amdgpu_bo(bo);
 479         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 480                 return -EINVAL;
 481
 482         adev = amdgpu_ttm_adev(bo->bdev);
 483
 484         if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
 485                          bo->ttm == NULL)) {
 486                 ttm_bo_move_null(bo, new_mem);
 487                 goto out;
 488         }
 489         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 490             (new_mem->mem_type == TTM_PL_TT ||
 491              new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 492                 ttm_bo_move_null(bo, new_mem);
 493                 goto out;
 494         }
 495         if ((old_mem->mem_type == TTM_PL_TT ||
 496              old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 497             new_mem->mem_type == TTM_PL_SYSTEM) {
 498                 r = ttm_bo_wait_ctx(bo, ctx);
 499                 if (r)
 500                         return r;
 501
 502                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 503                 ttm_resource_free(bo, &bo->resource);
 504                 ttm_bo_assign_mem(bo, new_mem);
 505                 goto out;
 506         }
 507
 508         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 509             old_mem->mem_type == AMDGPU_PL_GWS ||
 510             old_mem->mem_type == AMDGPU_PL_OA ||
 511             new_mem->mem_type == AMDGPU_PL_GDS ||
 512             new_mem->mem_type == AMDGPU_PL_GWS ||
 513             new_mem->mem_type == AMDGPU_PL_OA) {
 514                 /* Nothing to save here */
 515                 ttm_bo_move_null(bo, new_mem);
 516                 goto out;
 517         }
 518
 519         if (bo->type == ttm_bo_type_device &&
 520             new_mem->mem_type == TTM_PL_VRAM &&
 521             old_mem->mem_type != TTM_PL_VRAM) {
 522                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 523                  * accesses the BO after it's moved.
 524                  */
 525                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 526         }
 527
 528         if (adev->mman.buffer_funcs_enabled) {
 529                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 530                       new_mem->mem_type == TTM_PL_VRAM) ||
 531                      (old_mem->mem_type == TTM_PL_VRAM &&
 532                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 533                         hop->fpfn = 0;
 534                         hop->lpfn = 0;
 535                         hop->mem_type = TTM_PL_TT;
 536                         hop->flags = TTM_PL_FLAG_TEMPORARY;
 537                         return -EMULTIHOP;
 538                 }
 539
 540                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 541         } else {
 542                 r = -ENODEV;
 543         }
 544
 545         if (r) {
 546                 /* Check that all memory is CPU accessible */
 547                 if (!amdgpu_mem_visible(adev, old_mem) ||
 548                     !amdgpu_mem_visible(adev, new_mem)) {
 549                         pr_err("Move buffer fallback to memcpy unavailable\n");
 550                         return r;
 551                 }
 552
 553                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 554                 if (r)
 555                         return r;
 556         }
 557
 558 out:
 559         /* update statistics */
 560         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 561         amdgpu_bo_move_notify(bo, evict, new_mem);
 562         return 0;
 563 }
 564
 565 /*
 566  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 567  *
 568  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 569  */
 570 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 571                                      struct ttm_resource *mem)
 572 {
 573         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 574         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 575
 576         switch (mem->mem_type) {
 577         case TTM_PL_SYSTEM:
 578                 /* system memory */
 579                 return 0;
 580         case TTM_PL_TT:
 581         case AMDGPU_PL_PREEMPT:
 582                 break;
 583         case TTM_PL_VRAM:
 584                 mem->bus.offset = mem->start << PAGE_SHIFT;
 585                 /* check if it's visible */
 586                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 587                         return -EINVAL;
 588
 589                 if (adev->mman.aper_base_kaddr &&
 590                     mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 591                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 592                                         mem->bus.offset;
 593
 594                 mem->bus.offset += adev->gmc.aper_base;
 595                 mem->bus.is_iomem = true;
 596                 break;
 597         default:
 598                 return -EINVAL;
 599         }
 600         return 0;
 601 }
 602
 603 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 604                                            unsigned long page_offset)
 605 {
 606         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 607         struct amdgpu_res_cursor cursor;
 608
 609         amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 610                          &cursor);
 611         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 612 }
 613
 614 /**
 615  * amdgpu_ttm_domain_start - Returns GPU start address
 616  * @adev: amdgpu device object
 617  * @type: type of the memory
 618  *
 619  * Returns:
 620  * GPU start address of a memory domain
 621  */
 622
 623 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 624 {
 625         switch (type) {
 626         case TTM_PL_TT:
 627                 return adev->gmc.gart_start;
 628         case TTM_PL_VRAM:
 629                 return adev->gmc.vram_start;
 630         }
 631
 632         return 0;
 633 }
 634
 635 /*
 636  * TTM backend functions.
 637  */
 638 struct amdgpu_ttm_tt {
 639         struct ttm_tt   ttm;
 640         struct drm_gem_object   *gobj;
 641         u64                     offset;
 642         uint64_t                userptr;
 643         struct task_struct      *usertask;
 644         uint32_t                userflags;
 645         bool                    bound;
 646 };
 647
 648 #define ttm_to_amdgpu_ttm_tt(ptr)       container_of(ptr, struct amdgpu_ttm_tt, ttm)
 649
 650 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 651 /*
 652  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 653  * memory and start HMM tracking CPU page table update
 654  *
 655  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 656  * once afterwards to stop HMM tracking
 657  */
 658 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
 659                                  struct hmm_range **range)
 660 {
 661         struct ttm_tt *ttm = bo->tbo.ttm;
 662         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 663         unsigned long start = gtt->userptr;
 664         struct vm_area_struct *vma;
 665         struct mm_struct *mm;
 666         bool readonly;
 667         int r = 0;
 668
 669         /* Make sure get_user_pages_done() can cleanup gracefully */
 670         *range = NULL;
 671
 672         mm = bo->notifier.mm;
 673         if (unlikely(!mm)) {
 674                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 675                 return -EFAULT;
 676         }
 677
 678         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 679                 return -ESRCH;
 680
 681         mmap_read_lock(mm);
 682         vma = vma_lookup(mm, start);
 683         if (unlikely(!vma)) {
 684                 r = -EFAULT;
 685                 goto out_unlock;
 686         }
 687         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 688                 vma->vm_file)) {
 689                 r = -EPERM;
 690                 goto out_unlock;
 691         }
 692
 693         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 694         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 695                                        ttm->num_pages, range, readonly,
 696                                        true, NULL);
 697 out_unlock:
 698         mmap_read_unlock(mm);
 699         if (r)
 700                 pr_debug("failed %d to get user pages 0x%lx\n", r, start);
 701
 702         mmput(mm);
 703
 704         return r;
 705 }
 706
 707 /*
 708  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 709  * Check if the pages backing this ttm range have been invalidated
 710  *
 711  * Returns: true if pages are still valid
 712  */
 713 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
 714                                        struct hmm_range *range)
 715 {
 716         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 717
 718         if (!gtt || !gtt->userptr || !range)
 719                 return false;
 720
 721         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 722                 gtt->userptr, ttm->num_pages);
 723
 724         WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
 725
 726         /*
 727          * FIXME: Must always hold notifier_lock for this, and must
 728          * not ignore the return code.
 729          */
 730         return !amdgpu_hmm_range_get_pages_done(range);
 731 }
 732 #endif
 733
 734 /*
 735  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 736  *
 737  * Called by amdgpu_cs_list_validate(). This creates the page list
 738  * that backs user memory and will ultimately be mapped into the device
 739  * address space.
 740  */
 741 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 742 {
 743         unsigned long i;
 744
 745         for (i = 0; i < ttm->num_pages; ++i)
 746                 ttm->pages[i] = pages ? pages[i] : NULL;
 747 }
 748
 749 /*
 750  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 751  *
 752  * Called by amdgpu_ttm_backend_bind()
 753  **/
 754 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 755                                      struct ttm_tt *ttm)
 756 {
 757         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 758         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 759         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 760         enum dma_data_direction direction = write ?
 761                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 762         int r;
 763
 764         /* Allocate an SG array and squash pages into it */
 765         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 766                                       (u64)ttm->num_pages << PAGE_SHIFT,
 767                                       GFP_KERNEL);
 768         if (r)
 769                 goto release_sg;
 770
 771         /* Map SG to device */
 772         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 773         if (r)
 774                 goto release_sg;
 775
 776         /* convert SG to linear array of pages and dma addresses */
 777         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 778                                        ttm->num_pages);
 779
 780         return 0;
 781
 782 release_sg:
 783         kfree(ttm->sg);
 784         ttm->sg = NULL;
 785         return r;
 786 }
 787
 788 /*
 789  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 790  */
 791 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 792                                         struct ttm_tt *ttm)
 793 {
 794         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 795         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 796         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 797         enum dma_data_direction direction = write ?
 798                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 799
 800         /* double check that we don't free the table twice */
 801         if (!ttm->sg || !ttm->sg->sgl)
 802                 return;
 803
 804         /* unmap the pages mapped to the device */
 805         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 806         sg_free_table(ttm->sg);
 807 }
 808
 809 static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 810                                  struct ttm_buffer_object *tbo,
 811                                  uint64_t flags)
 812 {
 813         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 814         struct ttm_tt *ttm = tbo->ttm;
 815         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 816
 817         if (amdgpu_bo_encrypted(abo))
 818                 flags |= AMDGPU_PTE_TMZ;
 819
 820         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 821                 uint64_t page_idx = 1;
 822
 823                 amdgpu_gart_bind(adev, gtt->offset, page_idx,
 824                                  gtt->ttm.dma_address, flags);
 825
 826                 /* The memory type of the first page defaults to UC. Now
 827                  * modify the memory type to NC from the second page of
 828                  * the BO onward.
 829                  */
 830                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 831                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 832
 833                 amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT),
 834                                  ttm->num_pages - page_idx,
 835                                  &(gtt->ttm.dma_address[page_idx]), flags);
 836         } else {
 837                 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 838                                  gtt->ttm.dma_address, flags);
 839         }
 840 }
 841
 842 /*
 843  * amdgpu_ttm_backend_bind - Bind GTT memory
 844  *
 845  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 846  * This handles binding GTT memory to the device address space.
 847  */
 848 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 849                                    struct ttm_tt *ttm,
 850                                    struct ttm_resource *bo_mem)
 851 {
 852         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 853         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 854         uint64_t flags;
 855         int r;
 856
 857         if (!bo_mem)
 858                 return -EINVAL;
 859
 860         if (gtt->bound)
 861                 return 0;
 862
 863         if (gtt->userptr) {
 864                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 865                 if (r) {
 866                         DRM_ERROR("failed to pin userptr\n");
 867                         return r;
 868                 }
 869         } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
 870                 if (!ttm->sg) {
 871                         struct dma_buf_attachment *attach;
 872                         struct sg_table *sgt;
 873
 874                         attach = gtt->gobj->import_attach;
 875                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 876                         if (IS_ERR(sgt))
 877                                 return PTR_ERR(sgt);
 878
 879                         ttm->sg = sgt;
 880                 }
 881
 882                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 883                                                ttm->num_pages);
 884         }
 885
 886         if (!ttm->num_pages) {
 887                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 888                      ttm->num_pages, bo_mem, ttm);
 889         }
 890
 891         if (bo_mem->mem_type != TTM_PL_TT ||
 892             !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 893                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 894                 return 0;
 895         }
 896
 897         /* compute PTE flags relevant to this BO memory */
 898         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 899
 900         /* bind pages into GART page tables */
 901         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 902         amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 903                          gtt->ttm.dma_address, flags);
 904         gtt->bound = true;
 905         return 0;
 906 }
 907
 908 /*
 909  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 910  * through AGP or GART aperture.
 911  *
 912  * If bo is accessible through AGP aperture, then use AGP aperture
 913  * to access bo; otherwise allocate logical space in GART aperture
 914  * and map bo to GART aperture.
 915  */
 916 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 917 {
 918         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 919         struct ttm_operation_ctx ctx = { false, false };
 920         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
 921         struct ttm_placement placement;
 922         struct ttm_place placements;
 923         struct ttm_resource *tmp;
 924         uint64_t addr, flags;
 925         int r;
 926
 927         if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 928                 return 0;
 929
 930         addr = amdgpu_gmc_agp_addr(bo);
 931         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 932                 bo->resource->start = addr >> PAGE_SHIFT;
 933                 return 0;
 934         }
 935
 936         /* allocate GART space */
 937         placement.num_placement = 1;
 938         placement.placement = &placements;
 939         placement.num_busy_placement = 1;
 940         placement.busy_placement = &placements;
 941         placements.fpfn = 0;
 942         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 943         placements.mem_type = TTM_PL_TT;
 944         placements.flags = bo->resource->placement;
 945
 946         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 947         if (unlikely(r))
 948                 return r;
 949
 950         /* compute PTE flags for this buffer object */
 951         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 952
 953         /* Bind pages */
 954         gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 955         amdgpu_ttm_gart_bind(adev, bo, flags);
 956         amdgpu_gart_invalidate_tlb(adev);
 957         ttm_resource_free(bo, &bo->resource);
 958         ttm_bo_assign_mem(bo, tmp);
 959
 960         return 0;
 961 }
 962
 963 /*
 964  * amdgpu_ttm_recover_gart - Rebind GTT pages
 965  *
 966  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
 967  * rebind GTT pages during a GPU reset.
 968  */
 969 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 970 {
 971         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 972         uint64_t flags;
 973
 974         if (!tbo->ttm)
 975                 return;
 976
 977         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
 978         amdgpu_ttm_gart_bind(adev, tbo, flags);
 979 }
 980
 981 /*
 982  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
 983  *
 984  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
 985  * ttm_tt_destroy().
 986  */
 987 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
 988                                       struct ttm_tt *ttm)
 989 {
 990         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 991         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 992
 993         /* if the pages have userptr pinning then clear that first */
 994         if (gtt->userptr) {
 995                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
 996         } else if (ttm->sg && gtt->gobj->import_attach) {
 997                 struct dma_buf_attachment *attach;
 998
 999                 attach = gtt->gobj->import_attach;
1000                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1001                 ttm->sg = NULL;
1002         }
1003
1004         if (!gtt->bound)
1005                 return;
1006
1007         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1008                 return;
1009
1010         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1011         amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1012         gtt->bound = false;
1013 }
1014
1015 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1016                                        struct ttm_tt *ttm)
1017 {
1018         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1019
1020         if (gtt->usertask)
1021                 put_task_struct(gtt->usertask);
1022
1023         ttm_tt_fini(&gtt->ttm);
1024         kfree(gtt);
1025 }
1026
1027 /**
1028  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1029  *
1030  * @bo: The buffer object to create a GTT ttm_tt object around
1031  * @page_flags: Page flags to be added to the ttm_tt object
1032  *
1033  * Called by ttm_tt_create().
1034  */
1035 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1036                                            uint32_t page_flags)
1037 {
1038         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1039         struct amdgpu_ttm_tt *gtt;
1040         enum ttm_caching caching;
1041
1042         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1043         if (gtt == NULL) {
1044                 return NULL;
1045         }
1046         gtt->gobj = &bo->base;
1047
1048         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1049                 caching = ttm_write_combined;
1050         else
1051                 caching = ttm_cached;
1052
1053         /* allocate space for the uninitialized page entries */
1054         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1055                 kfree(gtt);
1056                 return NULL;
1057         }
1058         return &gtt->ttm;
1059 }
1060
1061 /*
1062  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1063  *
1064  * Map the pages of a ttm_tt object to an address space visible
1065  * to the underlying device.
1066  */
1067 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1068                                   struct ttm_tt *ttm,
1069                                   struct ttm_operation_ctx *ctx)
1070 {
1071         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1072         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1073         pgoff_t i;
1074         int ret;
1075
1076         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1077         if (gtt->userptr) {
1078                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1079                 if (!ttm->sg)
1080                         return -ENOMEM;
1081                 return 0;
1082         }
1083
1084         if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1085                 return 0;
1086
1087         ret = ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1088         if (ret)
1089                 return ret;
1090
1091         for (i = 0; i < ttm->num_pages; ++i)
1092                 ttm->pages[i]->mapping = bdev->dev_mapping;
1093
1094         return 0;
1095 }
1096
1097 /*
1098  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1099  *
1100  * Unmaps pages of a ttm_tt object from the device address space and
1101  * unpopulates the page array backing it.
1102  */
1103 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1104                                      struct ttm_tt *ttm)
1105 {
1106         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1107         struct amdgpu_device *adev;
1108         pgoff_t i;
1109
1110         amdgpu_ttm_backend_unbind(bdev, ttm);
1111
1112         if (gtt->userptr) {
1113                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1114                 kfree(ttm->sg);
1115                 ttm->sg = NULL;
1116                 return;
1117         }
1118
1119         if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1120                 return;
1121
1122         for (i = 0; i < ttm->num_pages; ++i)
1123                 ttm->pages[i]->mapping = NULL;
1124
1125         adev = amdgpu_ttm_adev(bdev);
1126         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1127 }
1128
1129 /**
1130  * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1131  * task
1132  *
1133  * @tbo: The ttm_buffer_object that contains the userptr
1134  * @user_addr:  The returned value
1135  */
1136 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1137                               uint64_t *user_addr)
1138 {
1139         struct amdgpu_ttm_tt *gtt;
1140
1141         if (!tbo->ttm)
1142                 return -EINVAL;
1143
1144         gtt = (void *)tbo->ttm;
1145         *user_addr = gtt->userptr;
1146         return 0;
1147 }
1148
1149 /**
1150  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1151  * task
1152  *
1153  * @bo: The ttm_buffer_object to bind this userptr to
1154  * @addr:  The address in the current tasks VM space to use
1155  * @flags: Requirements of userptr object.
1156  *
1157  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1158  * to current task
1159  */
1160 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1161                               uint64_t addr, uint32_t flags)
1162 {
1163         struct amdgpu_ttm_tt *gtt;
1164
1165         if (!bo->ttm) {
1166                 /* TODO: We want a separate TTM object type for userptrs */
1167                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1168                 if (bo->ttm == NULL)
1169                         return -ENOMEM;
1170         }
1171
1172         /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1173         bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1174
1175         gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1176         gtt->userptr = addr;
1177         gtt->userflags = flags;
1178
1179         if (gtt->usertask)
1180                 put_task_struct(gtt->usertask);
1181         gtt->usertask = current->group_leader;
1182         get_task_struct(gtt->usertask);
1183
1184         return 0;
1185 }
1186
1187 /*
1188  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1189  */
1190 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1191 {
1192         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1193
1194         if (gtt == NULL)
1195                 return NULL;
1196
1197         if (gtt->usertask == NULL)
1198                 return NULL;
1199
1200         return gtt->usertask->mm;
1201 }
1202
1203 /*
1204  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1205  * address range for the current task.
1206  *
1207  */
1208 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1209                                   unsigned long end, unsigned long *userptr)
1210 {
1211         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1212         unsigned long size;
1213
1214         if (gtt == NULL || !gtt->userptr)
1215                 return false;
1216
1217         /* Return false if no part of the ttm_tt object lies within
1218          * the range
1219          */
1220         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1221         if (gtt->userptr > end || gtt->userptr + size <= start)
1222                 return false;
1223
1224         if (userptr)
1225                 *userptr = gtt->userptr;
1226         return true;
1227 }
1228
1229 /*
1230  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1231  */
1232 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1233 {
1234         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1235
1236         if (gtt == NULL || !gtt->userptr)
1237                 return false;
1238
1239         return true;
1240 }
1241
1242 /*
1243  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1244  */
1245 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1246 {
1247         struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1248
1249         if (gtt == NULL)
1250                 return false;
1251
1252         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1253 }
1254
1255 /**
1256  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1257  *
1258  * @ttm: The ttm_tt object to compute the flags for
1259  * @mem: The memory registry backing this ttm_tt object
1260  *
1261  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1262  */
1263 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1264 {
1265         uint64_t flags = 0;
1266
1267         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1268                 flags |= AMDGPU_PTE_VALID;
1269
1270         if (mem && (mem->mem_type == TTM_PL_TT ||
1271                     mem->mem_type == AMDGPU_PL_PREEMPT)) {
1272                 flags |= AMDGPU_PTE_SYSTEM;
1273
1274                 if (ttm->caching == ttm_cached)
1275                         flags |= AMDGPU_PTE_SNOOPED;
1276         }
1277
1278         if (mem && mem->mem_type == TTM_PL_VRAM &&
1279                         mem->bus.caching == ttm_cached)
1280                 flags |= AMDGPU_PTE_SNOOPED;
1281
1282         return flags;
1283 }
1284
1285 /**
1286  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1287  *
1288  * @adev: amdgpu_device pointer
1289  * @ttm: The ttm_tt object to compute the flags for
1290  * @mem: The memory registry backing this ttm_tt object
1291  *
1292  * Figure out the flags to use for a VM PTE (Page Table Entry).
1293  */
1294 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1295                                  struct ttm_resource *mem)
1296 {
1297         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1298
1299         flags |= adev->gart.gart_pte_flags;
1300         flags |= AMDGPU_PTE_READABLE;
1301
1302         if (!amdgpu_ttm_tt_is_readonly(ttm))
1303                 flags |= AMDGPU_PTE_WRITEABLE;
1304
1305         return flags;
1306 }
1307
1308 /*
1309  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1310  * object.
1311  *
1312  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1313  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1314  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1315  * used to clean out a memory space.
1316  */
1317 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1318                                             const struct ttm_place *place)
1319 {
1320         struct dma_resv_iter resv_cursor;
1321         struct dma_fence *f;
1322
1323         if (!amdgpu_bo_is_amdgpu_bo(bo))
1324                 return ttm_bo_eviction_valuable(bo, place);
1325
1326         /* Swapout? */
1327         if (bo->resource->mem_type == TTM_PL_SYSTEM)
1328                 return true;
1329
1330         if (bo->type == ttm_bo_type_kernel &&
1331             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1332                 return false;
1333
1334         /* If bo is a KFD BO, check if the bo belongs to the current process.
1335          * If true, then return false as any KFD process needs all its BOs to
1336          * be resident to run successfully
1337          */
1338         dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1339                                 DMA_RESV_USAGE_BOOKKEEP, f) {
1340                 if (amdkfd_fence_check_mm(f, current->mm))
1341                         return false;
1342         }
1343
1344         /* Preemptible BOs don't own system resources managed by the
1345          * driver (pages, VRAM, GART space). They point to resources
1346          * owned by someone else (e.g. pageable memory in user mode
1347          * or a DMABuf). They are used in a preemptible context so we
1348          * can guarantee no deadlocks and good QoS in case of MMU
1349          * notifiers or DMABuf move notifiers from the resource owner.
1350          */
1351         if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1352                 return false;
1353
1354         if (bo->resource->mem_type == TTM_PL_TT &&
1355             amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1356                 return false;
1357
1358         return ttm_bo_eviction_valuable(bo, place);
1359 }
1360
1361 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1362                                       void *buf, size_t size, bool write)
1363 {
1364         while (size) {
1365                 uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1366                 uint64_t bytes = 4 - (pos & 0x3);
1367                 uint32_t shift = (pos & 0x3) * 8;
1368                 uint32_t mask = 0xffffffff << shift;
1369                 uint32_t value = 0;
1370
1371                 if (size < bytes) {
1372                         mask &= 0xffffffff >> (bytes - size) * 8;
1373                         bytes = size;
1374                 }
1375
1376                 if (mask != 0xffffffff) {
1377                         amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1378                         if (write) {
1379                                 value &= ~mask;
1380                                 value |= (*(uint32_t *)buf << shift) & mask;
1381                                 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1382                         } else {
1383                                 value = (value & mask) >> shift;
1384                                 memcpy(buf, &value, bytes);
1385                         }
1386                 } else {
1387                         amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1388                 }
1389
1390                 pos += bytes;
1391                 buf += bytes;
1392                 size -= bytes;
1393         }
1394 }
1395
1396 static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1397                                         unsigned long offset, void *buf, int len, int write)
1398 {
1399         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1400         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1401         struct amdgpu_res_cursor src_mm;
1402         struct amdgpu_job *job;
1403         struct dma_fence *fence;
1404         uint64_t src_addr, dst_addr;
1405         unsigned int num_dw;
1406         int r, idx;
1407
1408         if (len != PAGE_SIZE)
1409                 return -EINVAL;
1410
1411         if (!adev->mman.sdma_access_ptr)
1412                 return -EACCES;
1413
1414         if (!drm_dev_enter(adev_to_drm(adev), &idx))
1415                 return -ENODEV;
1416
1417         if (write)
1418                 memcpy(adev->mman.sdma_access_ptr, buf, len);
1419
1420         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1421         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, &job);
1422         if (r)
1423                 goto out;
1424
1425         amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1426         src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + src_mm.start;
1427         dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1428         if (write)
1429                 swap(src_addr, dst_addr);
1430
1431         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, false);
1432
1433         amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1434         WARN_ON(job->ibs[0].length_dw > num_dw);
1435
1436         r = amdgpu_job_submit(job, &adev->mman.entity, AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1437         if (r) {
1438                 amdgpu_job_free(job);
1439                 goto out;
1440         }
1441
1442         if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1443                 r = -ETIMEDOUT;
1444         dma_fence_put(fence);
1445
1446         if (!(r || write))
1447                 memcpy(buf, adev->mman.sdma_access_ptr, len);
1448 out:
1449         drm_dev_exit(idx);
1450         return r;
1451 }
1452
1453 /**
1454  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1455  *
1456  * @bo:  The buffer object to read/write
1457  * @offset:  Offset into buffer object
1458  * @buf:  Secondary buffer to write/read from
1459  * @len: Length in bytes of access
1460  * @write:  true if writing
1461  *
1462  * This is used to access VRAM that backs a buffer object via MMIO
1463  * access for debugging purposes.
1464  */
1465 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1466                                     unsigned long offset, void *buf, int len,
1467                                     int write)
1468 {
1469         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1470         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1471         struct amdgpu_res_cursor cursor;
1472         int ret = 0;
1473
1474         if (bo->resource->mem_type != TTM_PL_VRAM)
1475                 return -EIO;
1476
1477         if (amdgpu_device_has_timeouts_enabled(adev) &&
1478                         !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1479                 return len;
1480
1481         amdgpu_res_first(bo->resource, offset, len, &cursor);
1482         while (cursor.remaining) {
1483                 size_t count, size = cursor.size;
1484                 loff_t pos = cursor.start;
1485
1486                 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1487                 size -= count;
1488                 if (size) {
1489                         /* using MM to access rest vram and handle un-aligned address */
1490                         pos += count;
1491                         buf += count;
1492                         amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1493                 }
1494
1495                 ret += cursor.size;
1496                 buf += cursor.size;
1497                 amdgpu_res_next(&cursor, cursor.size);
1498         }
1499
1500         return ret;
1501 }
1502
1503 static void
1504 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1505 {
1506         amdgpu_bo_move_notify(bo, false, NULL);
1507 }
1508
1509 static struct ttm_device_funcs amdgpu_bo_driver = {
1510         .ttm_tt_create = &amdgpu_ttm_tt_create,
1511         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1512         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1513         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1514         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1515         .evict_flags = &amdgpu_evict_flags,
1516         .move = &amdgpu_bo_move,
1517         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1518         .release_notify = &amdgpu_bo_release_notify,
1519         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1520         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1521         .access_memory = &amdgpu_ttm_access_memory,
1522 };
1523
1524 /*
1525  * Firmware Reservation functions
1526  */
1527 /**
1528  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1529  *
1530  * @adev: amdgpu_device pointer
1531  *
1532  * free fw reserved vram if it has been reserved.
1533  */
1534 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1535 {
1536         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1537                 NULL, &adev->mman.fw_vram_usage_va);
1538 }
1539
1540 /**
1541  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1542  *
1543  * @adev: amdgpu_device pointer
1544  *
1545  * create bo vram reservation from fw.
1546  */
1547 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1548 {
1549         uint64_t vram_size = adev->gmc.visible_vram_size;
1550
1551         adev->mman.fw_vram_usage_va = NULL;
1552         adev->mman.fw_vram_usage_reserved_bo = NULL;
1553
1554         if (adev->mman.fw_vram_usage_size == 0 ||
1555             adev->mman.fw_vram_usage_size > vram_size)
1556                 return 0;
1557
1558         return amdgpu_bo_create_kernel_at(adev,
1559                                           adev->mman.fw_vram_usage_start_offset,
1560                                           adev->mman.fw_vram_usage_size,
1561                                           AMDGPU_GEM_DOMAIN_VRAM,
1562                                           &adev->mman.fw_vram_usage_reserved_bo,
1563                                           &adev->mman.fw_vram_usage_va);
1564 }
1565
1566 /*
1567  * Memoy training reservation functions
1568  */
1569
1570 /**
1571  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1572  *
1573  * @adev: amdgpu_device pointer
1574  *
1575  * free memory training reserved vram if it has been reserved.
1576  */
1577 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1578 {
1579         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1580
1581         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1582         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1583         ctx->c2p_bo = NULL;
1584
1585         return 0;
1586 }
1587
1588 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1589 {
1590         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1591
1592         memset(ctx, 0, sizeof(*ctx));
1593
1594         ctx->c2p_train_data_offset =
1595                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1596         ctx->p2c_train_data_offset =
1597                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1598         ctx->train_data_size =
1599                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1600
1601         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1602                         ctx->train_data_size,
1603                         ctx->p2c_train_data_offset,
1604                         ctx->c2p_train_data_offset);
1605 }
1606
1607 /*
1608  * reserve TMR memory at the top of VRAM which holds
1609  * IP Discovery data and is protected by PSP.
1610  */
1611 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1612 {
1613         int ret;
1614         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1615         bool mem_train_support = false;
1616
1617         if (!amdgpu_sriov_vf(adev)) {
1618                 if (amdgpu_atomfirmware_mem_training_supported(adev))
1619                         mem_train_support = true;
1620                 else
1621                         DRM_DEBUG("memory training does not support!\n");
1622         }
1623
1624         /*
1625          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1626          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1627          *
1628          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1629          * discovery data and G6 memory training data respectively
1630          */
1631         adev->mman.discovery_tmr_size =
1632                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1633         if (!adev->mman.discovery_tmr_size)
1634                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1635
1636         if (mem_train_support) {
1637                 /* reserve vram for mem train according to TMR location */
1638                 amdgpu_ttm_training_data_block_init(adev);
1639                 ret = amdgpu_bo_create_kernel_at(adev,
1640                                          ctx->c2p_train_data_offset,
1641                                          ctx->train_data_size,
1642                                          AMDGPU_GEM_DOMAIN_VRAM,
1643                                          &ctx->c2p_bo,
1644                                          NULL);
1645                 if (ret) {
1646                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1647                         amdgpu_ttm_training_reserve_vram_fini(adev);
1648                         return ret;
1649                 }
1650                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1651         }
1652
1653         ret = amdgpu_bo_create_kernel_at(adev,
1654                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1655                                 adev->mman.discovery_tmr_size,
1656                                 AMDGPU_GEM_DOMAIN_VRAM,
1657                                 &adev->mman.discovery_memory,
1658                                 NULL);
1659         if (ret) {
1660                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1661                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1662                 return ret;
1663         }
1664
1665         return 0;
1666 }
1667
1668 /*
1669  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1670  * gtt/vram related fields.
1671  *
1672  * This initializes all of the memory space pools that the TTM layer
1673  * will need such as the GTT space (system memory mapped to the device),
1674  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1675  * can be mapped per VMID.
1676  */
1677 int amdgpu_ttm_init(struct amdgpu_device *adev)
1678 {
1679         uint64_t gtt_size;
1680         int r;
1681         u64 vis_vram_limit;
1682
1683         mutex_init(&adev->mman.gtt_window_lock);
1684
1685         /* No others user of address space so set it to 0 */
1686         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1687                                adev_to_drm(adev)->anon_inode->i_mapping,
1688                                adev_to_drm(adev)->vma_offset_manager,
1689                                adev->need_swiotlb,
1690                                dma_addressing_limited(adev->dev));
1691         if (r) {
1692                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1693                 return r;
1694         }
1695         adev->mman.initialized = true;
1696
1697         /* Initialize VRAM pool with all of VRAM divided into pages */
1698         r = amdgpu_vram_mgr_init(adev);
1699         if (r) {
1700                 DRM_ERROR("Failed initializing VRAM heap.\n");
1701                 return r;
1702         }
1703
1704         /* Reduce size of CPU-visible VRAM if requested */
1705         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1706         if (amdgpu_vis_vram_limit > 0 &&
1707             vis_vram_limit <= adev->gmc.visible_vram_size)
1708                 adev->gmc.visible_vram_size = vis_vram_limit;
1709
1710         /* Change the size here instead of the init above so only lpfn is affected */
1711         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1712 #ifdef CONFIG_64BIT
1713 #ifdef CONFIG_X86
1714         if (adev->gmc.xgmi.connected_to_cpu)
1715                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1716                                 adev->gmc.visible_vram_size);
1717
1718         else
1719 #endif
1720                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1721                                 adev->gmc.visible_vram_size);
1722 #endif
1723
1724         /*
1725          *The reserved vram for firmware must be pinned to the specified
1726          *place on the VRAM, so reserve it early.
1727          */
1728         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1729         if (r) {
1730                 return r;
1731         }
1732
1733         /*
1734          * only NAVI10 and onwards ASIC support for IP discovery.
1735          * If IP discovery enabled, a block of memory should be
1736          * reserved for IP discovey.
1737          */
1738         if (adev->mman.discovery_bin) {
1739                 r = amdgpu_ttm_reserve_tmr(adev);
1740                 if (r)
1741                         return r;
1742         }
1743
1744         /* allocate memory as required for VGA
1745          * This is used for VGA emulation and pre-OS scanout buffers to
1746          * avoid display artifacts while transitioning between pre-OS
1747          * and driver.  */
1748         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1749                                        AMDGPU_GEM_DOMAIN_VRAM,
1750                                        &adev->mman.stolen_vga_memory,
1751                                        NULL);
1752         if (r)
1753                 return r;
1754         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1755                                        adev->mman.stolen_extended_size,
1756                                        AMDGPU_GEM_DOMAIN_VRAM,
1757                                        &adev->mman.stolen_extended_memory,
1758                                        NULL);
1759         if (r)
1760                 return r;
1761         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1762                                        adev->mman.stolen_reserved_size,
1763                                        AMDGPU_GEM_DOMAIN_VRAM,
1764                                        &adev->mman.stolen_reserved_memory,
1765                                        NULL);
1766         if (r)
1767                 return r;
1768
1769         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1770                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1771
1772         /* Compute GTT size, either based on 1/2 the size of RAM size
1773          * or whatever the user passed on module init */
1774         if (amdgpu_gtt_size == -1) {
1775                 struct sysinfo si;
1776
1777                 si_meminfo(&si);
1778                 /* Certain GL unit tests for large textures can cause problems
1779                  * with the OOM killer since there is no way to link this memory
1780                  * to a process.  This was originally mitigated (but not necessarily
1781                  * eliminated) by limiting the GTT size.  The problem is this limit
1782                  * is often too low for many modern games so just make the limit 1/2
1783                  * of system memory which aligns with TTM. The OOM accounting needs
1784                  * to be addressed, but we shouldn't prevent common 3D applications
1785                  * from being usable just to potentially mitigate that corner case.
1786                  */
1787                 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1788                                (u64)si.totalram * si.mem_unit / 2);
1789         } else {
1790                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1791         }
1792
1793         /* Initialize GTT memory pool */
1794         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1795         if (r) {
1796                 DRM_ERROR("Failed initializing GTT heap.\n");
1797                 return r;
1798         }
1799         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1800                  (unsigned)(gtt_size / (1024 * 1024)));
1801
1802         /* Initialize preemptible memory pool */
1803         r = amdgpu_preempt_mgr_init(adev);
1804         if (r) {
1805                 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1806                 return r;
1807         }
1808
1809         /* Initialize various on-chip memory pools */
1810         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1811         if (r) {
1812                 DRM_ERROR("Failed initializing GDS heap.\n");
1813                 return r;
1814         }
1815
1816         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1817         if (r) {
1818                 DRM_ERROR("Failed initializing gws heap.\n");
1819                 return r;
1820         }
1821
1822         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1823         if (r) {
1824                 DRM_ERROR("Failed initializing oa heap.\n");
1825                 return r;
1826         }
1827
1828         if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1829                                 AMDGPU_GEM_DOMAIN_GTT,
1830                                 &adev->mman.sdma_access_bo, NULL,
1831                                 &adev->mman.sdma_access_ptr))
1832                 DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1833
1834         return 0;
1835 }
1836
1837 /*
1838  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1839  */
1840 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1841 {
1842         int idx;
1843         if (!adev->mman.initialized)
1844                 return;
1845
1846         amdgpu_ttm_training_reserve_vram_fini(adev);
1847         /* return the stolen vga memory back to VRAM */
1848         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1849         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1850         /* return the IP Discovery TMR memory back to VRAM */
1851         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1852         if (adev->mman.stolen_reserved_size)
1853                 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1854                                       NULL, NULL);
1855         amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
1856                                         &adev->mman.sdma_access_ptr);
1857         amdgpu_ttm_fw_reserve_vram_fini(adev);
1858
1859         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1860
1861                 if (adev->mman.aper_base_kaddr)
1862                         iounmap(adev->mman.aper_base_kaddr);
1863                 adev->mman.aper_base_kaddr = NULL;
1864
1865                 drm_dev_exit(idx);
1866         }
1867
1868         amdgpu_vram_mgr_fini(adev);
1869         amdgpu_gtt_mgr_fini(adev);
1870         amdgpu_preempt_mgr_fini(adev);
1871         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1872         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1873         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1874         ttm_device_fini(&adev->mman.bdev);
1875         adev->mman.initialized = false;
1876         DRM_INFO("amdgpu: ttm finalized\n");
1877 }
1878
1879 /**
1880  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1881  *
1882  * @adev: amdgpu_device pointer
1883  * @enable: true when we can use buffer functions.
1884  *
1885  * Enable/disable use of buffer functions during suspend/resume. This should
1886  * only be called at bootup or when userspace isn't running.
1887  */
1888 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1889 {
1890         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1891         uint64_t size;
1892         int r;
1893
1894         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1895             adev->mman.buffer_funcs_enabled == enable)
1896                 return;
1897
1898         if (enable) {
1899                 struct amdgpu_ring *ring;
1900                 struct drm_gpu_scheduler *sched;
1901
1902                 ring = adev->mman.buffer_funcs_ring;
1903                 sched = &ring->sched;
1904                 r = drm_sched_entity_init(&adev->mman.entity,
1905                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1906                                           1, NULL);
1907                 if (r) {
1908                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1909                                   r);
1910                         return;
1911                 }
1912         } else {
1913                 drm_sched_entity_destroy(&adev->mman.entity);
1914                 dma_fence_put(man->move);
1915                 man->move = NULL;
1916         }
1917
1918         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1919         if (enable)
1920                 size = adev->gmc.real_vram_size;
1921         else
1922                 size = adev->gmc.visible_vram_size;
1923         man->size = size;
1924         adev->mman.buffer_funcs_enabled = enable;
1925 }
1926
1927 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
1928                                   bool direct_submit,
1929                                   unsigned int num_dw,
1930                                   struct dma_resv *resv,
1931                                   bool vm_needs_flush,
1932                                   struct amdgpu_job **job)
1933 {
1934         enum amdgpu_ib_pool_type pool = direct_submit ?
1935                 AMDGPU_IB_POOL_DIRECT :
1936                 AMDGPU_IB_POOL_DELAYED;
1937         int r;
1938
1939         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, job);
1940         if (r)
1941                 return r;
1942
1943         if (vm_needs_flush) {
1944                 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1945                                                         adev->gmc.pdb0_bo :
1946                                                         adev->gart.bo);
1947                 (*job)->vm_needs_flush = true;
1948         }
1949         if (resv) {
1950                 r = amdgpu_sync_resv(adev, &(*job)->sync, resv,
1951                                      AMDGPU_SYNC_ALWAYS,
1952                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1953                 if (r) {
1954                         DRM_ERROR("sync failed (%d).\n", r);
1955                         amdgpu_job_free(*job);
1956                         return r;
1957                 }
1958         }
1959         return 0;
1960 }
1961
1962 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1963                        uint64_t dst_offset, uint32_t byte_count,
1964                        struct dma_resv *resv,
1965                        struct dma_fence **fence, bool direct_submit,
1966                        bool vm_needs_flush, bool tmz)
1967 {
1968         struct amdgpu_device *adev = ring->adev;
1969         unsigned num_loops, num_dw;
1970         struct amdgpu_job *job;
1971         uint32_t max_bytes;
1972         unsigned i;
1973         int r;
1974
1975         if (!direct_submit && !ring->sched.ready) {
1976                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1977                 return -EINVAL;
1978         }
1979
1980         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1981         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1982         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1983         r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
1984                                    resv, vm_needs_flush, &job);
1985         if (r)
1986                 return r;
1987
1988         for (i = 0; i < num_loops; i++) {
1989                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1990
1991                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1992                                         dst_offset, cur_size_in_bytes, tmz);
1993
1994                 src_offset += cur_size_in_bytes;
1995                 dst_offset += cur_size_in_bytes;
1996                 byte_count -= cur_size_in_bytes;
1997         }
1998
1999         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2000         WARN_ON(job->ibs[0].length_dw > num_dw);
2001         if (direct_submit)
2002                 r = amdgpu_job_submit_direct(job, ring, fence);
2003         else
2004                 r = amdgpu_job_submit(job, &adev->mman.entity,
2005                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2006         if (r)
2007                 goto error_free;
2008
2009         return r;
2010
2011 error_free:
2012         amdgpu_job_free(job);
2013         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2014         return r;
2015 }
2016
2017 static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2018                                uint64_t dst_addr, uint32_t byte_count,
2019                                struct dma_resv *resv,
2020                                struct dma_fence **fence,
2021                                bool vm_needs_flush)
2022 {
2023         struct amdgpu_device *adev = ring->adev;
2024         unsigned int num_loops, num_dw;
2025         struct amdgpu_job *job;
2026         uint32_t max_bytes;
2027         unsigned int i;
2028         int r;
2029
2030         max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2031         num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2032         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2033         r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2034                                    &job);
2035         if (r)
2036                 return r;
2037
2038         for (i = 0; i < num_loops; i++) {
2039                 uint32_t cur_size = min(byte_count, max_bytes);
2040
2041                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2042                                         cur_size);
2043
2044                 dst_addr += cur_size;
2045                 byte_count -= cur_size;
2046         }
2047
2048         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2049         WARN_ON(job->ibs[0].length_dw > num_dw);
2050         r = amdgpu_job_submit(job, &adev->mman.entity,
2051                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2052         if (r)
2053                 goto error_free;
2054
2055         return 0;
2056
2057 error_free:
2058         amdgpu_job_free(job);
2059         return r;
2060 }
2061
2062 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2063                         uint32_t src_data,
2064                         struct dma_resv *resv,
2065                         struct dma_fence **f)
2066 {
2067         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2068         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2069         struct dma_fence *fence = NULL;
2070         struct amdgpu_res_cursor dst;
2071         int r;
2072
2073         if (!adev->mman.buffer_funcs_enabled) {
2074                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2075                 return -EINVAL;
2076         }
2077
2078         amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2079
2080         mutex_lock(&adev->mman.gtt_window_lock);
2081         while (dst.remaining) {
2082                 struct dma_fence *next;
2083                 uint64_t cur_size, to;
2084
2085                 /* Never fill more than 256MiB at once to avoid timeouts */
2086                 cur_size = min(dst.size, 256ULL << 20);
2087
2088                 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2089                                           1, ring, false, &cur_size, &to);
2090                 if (r)
2091                         goto error;
2092
2093                 r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2094                                         &next, true);
2095                 if (r)
2096                         goto error;
2097
2098                 dma_fence_put(fence);
2099                 fence = next;
2100
2101                 amdgpu_res_next(&dst, cur_size);
2102         }
2103 error:
2104         mutex_unlock(&adev->mman.gtt_window_lock);
2105         if (f)
2106                 *f = dma_fence_get(fence);
2107         dma_fence_put(fence);
2108         return r;
2109 }
2110
2111 /**
2112  * amdgpu_ttm_evict_resources - evict memory buffers
2113  * @adev: amdgpu device object
2114  * @mem_type: evicted BO's memory type
2115  *
2116  * Evicts all @mem_type buffers on the lru list of the memory type.
2117  *
2118  * Returns:
2119  * 0 for success or a negative error code on failure.
2120  */
2121 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2122 {
2123         struct ttm_resource_manager *man;
2124
2125         switch (mem_type) {
2126         case TTM_PL_VRAM:
2127         case TTM_PL_TT:
2128         case AMDGPU_PL_GWS:
2129         case AMDGPU_PL_GDS:
2130         case AMDGPU_PL_OA:
2131                 man = ttm_manager_type(&adev->mman.bdev, mem_type);
2132                 break;
2133         default:
2134                 DRM_ERROR("Trying to evict invalid memory type\n");
2135                 return -EINVAL;
2136         }
2137
2138         return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2139 }
2140
2141 #if defined(CONFIG_DEBUG_FS)
2142
2143 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2144 {
2145         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2146
2147         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2148 }
2149
2150 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2151
2152 /*
2153  * amdgpu_ttm_vram_read - Linear read access to VRAM
2154  *
2155  * Accesses VRAM via MMIO for debugging purposes.
2156  */
2157 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2158                                     size_t size, loff_t *pos)
2159 {
2160         struct amdgpu_device *adev = file_inode(f)->i_private;
2161         ssize_t result = 0;
2162
2163         if (size & 0x3 || *pos & 0x3)
2164                 return -EINVAL;
2165
2166         if (*pos >= adev->gmc.mc_vram_size)
2167                 return -ENXIO;
2168
2169         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2170         while (size) {
2171                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2172                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2173
2174                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2175                 if (copy_to_user(buf, value, bytes))
2176                         return -EFAULT;
2177
2178                 result += bytes;
2179                 buf += bytes;
2180                 *pos += bytes;
2181                 size -= bytes;
2182         }
2183
2184         return result;
2185 }
2186
2187 /*
2188  * amdgpu_ttm_vram_write - Linear write access to VRAM
2189  *
2190  * Accesses VRAM via MMIO for debugging purposes.
2191  */
2192 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2193                                     size_t size, loff_t *pos)
2194 {
2195         struct amdgpu_device *adev = file_inode(f)->i_private;
2196         ssize_t result = 0;
2197         int r;
2198
2199         if (size & 0x3 || *pos & 0x3)
2200                 return -EINVAL;
2201
2202         if (*pos >= adev->gmc.mc_vram_size)
2203                 return -ENXIO;
2204
2205         while (size) {
2206                 uint32_t value;
2207
2208                 if (*pos >= adev->gmc.mc_vram_size)
2209                         return result;
2210
2211                 r = get_user(value, (uint32_t *)buf);
2212                 if (r)
2213                         return r;
2214
2215                 amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2216
2217                 result += 4;
2218                 buf += 4;
2219                 *pos += 4;
2220                 size -= 4;
2221         }
2222
2223         return result;
2224 }
2225
2226 static const struct file_operations amdgpu_ttm_vram_fops = {
2227         .owner = THIS_MODULE,
2228         .read = amdgpu_ttm_vram_read,
2229         .write = amdgpu_ttm_vram_write,
2230         .llseek = default_llseek,
2231 };
2232
2233 /*
2234  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2235  *
2236  * This function is used to read memory that has been mapped to the
2237  * GPU and the known addresses are not physical addresses but instead
2238  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2239  */
2240 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2241                                  size_t size, loff_t *pos)
2242 {
2243         struct amdgpu_device *adev = file_inode(f)->i_private;
2244         struct iommu_domain *dom;
2245         ssize_t result = 0;
2246         int r;
2247
2248         /* retrieve the IOMMU domain if any for this device */
2249         dom = iommu_get_domain_for_dev(adev->dev);
2250
2251         while (size) {
2252                 phys_addr_t addr = *pos & PAGE_MASK;
2253                 loff_t off = *pos & ~PAGE_MASK;
2254                 size_t bytes = PAGE_SIZE - off;
2255                 unsigned long pfn;
2256                 struct page *p;
2257                 void *ptr;
2258
2259                 bytes = bytes < size ? bytes : size;
2260
2261                 /* Translate the bus address to a physical address.  If
2262                  * the domain is NULL it means there is no IOMMU active
2263                  * and the address translation is the identity
2264                  */
2265                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2266
2267                 pfn = addr >> PAGE_SHIFT;
2268                 if (!pfn_valid(pfn))
2269                         return -EPERM;
2270
2271                 p = pfn_to_page(pfn);
2272                 if (p->mapping != adev->mman.bdev.dev_mapping)
2273                         return -EPERM;
2274
2275                 ptr = kmap(p);
2276                 r = copy_to_user(buf, ptr + off, bytes);
2277                 kunmap(p);
2278                 if (r)
2279                         return -EFAULT;
2280
2281                 size -= bytes;
2282                 *pos += bytes;
2283                 result += bytes;
2284         }
2285
2286         return result;
2287 }
2288
2289 /*
2290  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2291  *
2292  * This function is used to write memory that has been mapped to the
2293  * GPU and the known addresses are not physical addresses but instead
2294  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2295  */
2296 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2297                                  size_t size, loff_t *pos)
2298 {
2299         struct amdgpu_device *adev = file_inode(f)->i_private;
2300         struct iommu_domain *dom;
2301         ssize_t result = 0;
2302         int r;
2303
2304         dom = iommu_get_domain_for_dev(adev->dev);
2305
2306         while (size) {
2307                 phys_addr_t addr = *pos & PAGE_MASK;
2308                 loff_t off = *pos & ~PAGE_MASK;
2309                 size_t bytes = PAGE_SIZE - off;
2310                 unsigned long pfn;
2311                 struct page *p;
2312                 void *ptr;
2313
2314                 bytes = bytes < size ? bytes : size;
2315
2316                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2317
2318                 pfn = addr >> PAGE_SHIFT;
2319                 if (!pfn_valid(pfn))
2320                         return -EPERM;
2321
2322                 p = pfn_to_page(pfn);
2323                 if (p->mapping != adev->mman.bdev.dev_mapping)
2324                         return -EPERM;
2325
2326                 ptr = kmap(p);
2327                 r = copy_from_user(ptr + off, buf, bytes);
2328                 kunmap(p);
2329                 if (r)
2330                         return -EFAULT;
2331
2332                 size -= bytes;
2333                 *pos += bytes;
2334                 result += bytes;
2335         }
2336
2337         return result;
2338 }
2339
2340 static const struct file_operations amdgpu_ttm_iomem_fops = {
2341         .owner = THIS_MODULE,
2342         .read = amdgpu_iomem_read,
2343         .write = amdgpu_iomem_write,
2344         .llseek = default_llseek
2345 };
2346
2347 #endif
2348
2349 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2350 {
2351 #if defined(CONFIG_DEBUG_FS)
2352         struct drm_minor *minor = adev_to_drm(adev)->primary;
2353         struct dentry *root = minor->debugfs_root;
2354
2355         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2356                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2357         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2358                             &amdgpu_ttm_iomem_fops);
2359         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2360                             &amdgpu_ttm_page_pool_fops);
2361         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2362                                                              TTM_PL_VRAM),
2363                                             root, "amdgpu_vram_mm");
2364         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2365                                                              TTM_PL_TT),
2366                                             root, "amdgpu_gtt_mm");
2367         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2368                                                              AMDGPU_PL_GDS),
2369                                             root, "amdgpu_gds_mm");
2370         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2371                                                              AMDGPU_PL_GWS),
2372                                             root, "amdgpu_gws_mm");
2373         ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2374                                                              AMDGPU_PL_OA),
2375                                             root, "amdgpu_oa_mm");
2376
2377 #endif
2378 }