drivers/clk/spear/spear3xx_clock.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * SPEAr3xx machines clock framework source file
   4  *
   5  * Copyright (C) 2012 ST Microelectronics
   6  * Viresh Kumar <vireshk@kernel.org>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/clkdev.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/spinlock_types.h>
  15 #include "clk.h"
  16
  17 static DEFINE_SPINLOCK(_lock);
  18
  19 #define PLL1_CTR                        (misc_base + 0x008)
  20 #define PLL1_FRQ                        (misc_base + 0x00C)
  21 #define PLL2_CTR                        (misc_base + 0x014)
  22 #define PLL2_FRQ                        (misc_base + 0x018)
  23 #define PLL_CLK_CFG                     (misc_base + 0x020)
  24         /* PLL_CLK_CFG register masks */
  25         #define MCTR_CLK_SHIFT          28
  26         #define MCTR_CLK_MASK           3
  27
  28 #define CORE_CLK_CFG                    (misc_base + 0x024)
  29         /* CORE CLK CFG register masks */
  30         #define GEN_SYNTH2_3_CLK_SHIFT  18
  31         #define GEN_SYNTH2_3_CLK_MASK   1
  32
  33         #define HCLK_RATIO_SHIFT        10
  34         #define HCLK_RATIO_MASK         2
  35         #define PCLK_RATIO_SHIFT        8
  36         #define PCLK_RATIO_MASK         2
  37
  38 #define PERIP_CLK_CFG                   (misc_base + 0x028)
  39         /* PERIP_CLK_CFG register masks */
  40         #define UART_CLK_SHIFT          4
  41         #define UART_CLK_MASK           1
  42         #define FIRDA_CLK_SHIFT         5
  43         #define FIRDA_CLK_MASK          2
  44         #define GPT0_CLK_SHIFT          8
  45         #define GPT1_CLK_SHIFT          11
  46         #define GPT2_CLK_SHIFT          12
  47         #define GPT_CLK_MASK            1
  48
  49 #define PERIP1_CLK_ENB                  (misc_base + 0x02C)
  50         /* PERIP1_CLK_ENB register masks */
  51         #define UART_CLK_ENB            3
  52         #define SSP_CLK_ENB             5
  53         #define I2C_CLK_ENB             7
  54         #define JPEG_CLK_ENB            8
  55         #define FIRDA_CLK_ENB           10
  56         #define GPT1_CLK_ENB            11
  57         #define GPT2_CLK_ENB            12
  58         #define ADC_CLK_ENB             15
  59         #define RTC_CLK_ENB             17
  60         #define GPIO_CLK_ENB            18
  61         #define DMA_CLK_ENB             19
  62         #define SMI_CLK_ENB             21
  63         #define GMAC_CLK_ENB            23
  64         #define USBD_CLK_ENB            24
  65         #define USBH_CLK_ENB            25
  66         #define C3_CLK_ENB              31
  67
  68 #define RAS_CLK_ENB                     (misc_base + 0x034)
  69         #define RAS_AHB_CLK_ENB         0
  70         #define RAS_PLL1_CLK_ENB        1
  71         #define RAS_APB_CLK_ENB         2
  72         #define RAS_32K_CLK_ENB         3
  73         #define RAS_24M_CLK_ENB         4
  74         #define RAS_48M_CLK_ENB         5
  75         #define RAS_PLL2_CLK_ENB        7
  76         #define RAS_SYNT0_CLK_ENB       8
  77         #define RAS_SYNT1_CLK_ENB       9
  78         #define RAS_SYNT2_CLK_ENB       10
  79         #define RAS_SYNT3_CLK_ENB       11
  80
  81 #define PRSC0_CLK_CFG                   (misc_base + 0x044)
  82 #define PRSC1_CLK_CFG                   (misc_base + 0x048)
  83 #define PRSC2_CLK_CFG                   (misc_base + 0x04C)
  84 #define AMEM_CLK_CFG                    (misc_base + 0x050)
  85         #define AMEM_CLK_ENB            0
  86
  87 #define CLCD_CLK_SYNT                   (misc_base + 0x05C)
  88 #define FIRDA_CLK_SYNT                  (misc_base + 0x060)
  89 #define UART_CLK_SYNT                   (misc_base + 0x064)
  90 #define GMAC_CLK_SYNT                   (misc_base + 0x068)
  91 #define GEN0_CLK_SYNT                   (misc_base + 0x06C)
  92 #define GEN1_CLK_SYNT                   (misc_base + 0x070)
  93 #define GEN2_CLK_SYNT                   (misc_base + 0x074)
  94 #define GEN3_CLK_SYNT                   (misc_base + 0x078)
  95
  96 /* pll rate configuration table, in ascending order of rates */
  97 static struct pll_rate_tbl pll_rtbl[] = {
  98         {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
  99         {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
 100         {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
 101 };
 102
 103 /* aux rate configuration table, in ascending order of rates */
 104 static struct aux_rate_tbl aux_rtbl[] = {
 105         /* For PLL1 = 332 MHz */
 106         {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */
 107         {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */
 108         {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */
 109         {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */
 110         {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */
 111         {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */
 112         {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
 113         {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
 114         {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
 115         {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
 116 };
 117
 118 /* gpt rate configuration table, in ascending order of rates */
 119 static struct gpt_rate_tbl gpt_rtbl[] = {
 120         /* For pll1 = 332 MHz */
 121         {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
 122         {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
 123         {.mscale = 1, .nscale = 0}, /* 83 MHz */
 124 };
 125
 126 /* clock parents */
 127 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
 128 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
 129 };
 130 static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
 131 static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
 132 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
 133 static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
 134 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
 135         "pll2_clk", };
 136
 137 #ifdef CONFIG_MACH_SPEAR300
 138 static void __init spear300_clk_init(void)
 139 {
 140         struct clk *clk;
 141
 142         clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
 143                         1, 1);
 144         clk_register_clkdev(clk, NULL, "60000000.clcd");
 145
 146         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
 147                         1);
 148         clk_register_clkdev(clk, NULL, "94000000.flash");
 149
 150         clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
 151                         1);
 152         clk_register_clkdev(clk, NULL, "70000000.sdhci");
 153
 154         clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
 155                         1);
 156         clk_register_clkdev(clk, NULL, "a9000000.gpio");
 157
 158         clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
 159                         1);
 160         clk_register_clkdev(clk, NULL, "a0000000.kbd");
 161 }
 162 #else
 163 static inline void spear300_clk_init(void) { }
 164 #endif
 165
 166 /* array of all spear 310 clock lookups */
 167 #ifdef CONFIG_MACH_SPEAR310
 168 static void __init spear310_clk_init(void)
 169 {
 170         struct clk *clk;
 171
 172         clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
 173                         1);
 174         clk_register_clkdev(clk, "emi", NULL);
 175
 176         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
 177                         1);
 178         clk_register_clkdev(clk, NULL, "44000000.flash");
 179
 180         clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
 181                         1);
 182         clk_register_clkdev(clk, NULL, "tdm");
 183
 184         clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
 185                         1);
 186         clk_register_clkdev(clk, NULL, "b2000000.serial");
 187
 188         clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
 189                         1);
 190         clk_register_clkdev(clk, NULL, "b2080000.serial");
 191
 192         clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
 193                         1);
 194         clk_register_clkdev(clk, NULL, "b2100000.serial");
 195
 196         clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
 197                         1);
 198         clk_register_clkdev(clk, NULL, "b2180000.serial");
 199
 200         clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
 201                         1);
 202         clk_register_clkdev(clk, NULL, "b2200000.serial");
 203 }
 204 #else
 205 static inline void spear310_clk_init(void) { }
 206 #endif
 207
 208 /* array of all spear 320 clock lookups */
 209 #ifdef CONFIG_MACH_SPEAR320
 210
 211 #define SPEAR320_CONTROL_REG            (soc_config_base + 0x0010)
 212 #define SPEAR320_EXT_CTRL_REG           (soc_config_base + 0x0018)
 213
 214         #define SPEAR320_UARTX_PCLK_MASK                0x1
 215         #define SPEAR320_UART2_PCLK_SHIFT               8
 216         #define SPEAR320_UART3_PCLK_SHIFT               9
 217         #define SPEAR320_UART4_PCLK_SHIFT               10
 218         #define SPEAR320_UART5_PCLK_SHIFT               11
 219         #define SPEAR320_UART6_PCLK_SHIFT               12
 220         #define SPEAR320_RS485_PCLK_SHIFT               13
 221         #define SMII_PCLK_SHIFT                         18
 222         #define SMII_PCLK_MASK                          2
 223         #define SMII_PCLK_VAL_PAD                       0x0
 224         #define SMII_PCLK_VAL_PLL2                      0x1
 225         #define SMII_PCLK_VAL_SYNTH0                    0x2
 226         #define SDHCI_PCLK_SHIFT                        15
 227         #define SDHCI_PCLK_MASK                         1
 228         #define SDHCI_PCLK_VAL_48M                      0x0
 229         #define SDHCI_PCLK_VAL_SYNTH3                   0x1
 230         #define I2S_REF_PCLK_SHIFT                      8
 231         #define I2S_REF_PCLK_MASK                       1
 232         #define I2S_REF_PCLK_SYNTH_VAL                  0x1
 233         #define I2S_REF_PCLK_PLL2_VAL                   0x0
 234         #define UART1_PCLK_SHIFT                        6
 235         #define UART1_PCLK_MASK                         1
 236         #define SPEAR320_UARTX_PCLK_VAL_SYNTH1          0x0
 237         #define SPEAR320_UARTX_PCLK_VAL_APB             0x1
 238
 239 static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
 240 static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
 241 static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
 242         "ras_syn0_gclk", };
 243 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
 244
 245 static void __init spear320_clk_init(void __iomem *soc_config_base,
 246                                      struct clk *ras_apb_clk)
 247 {
 248         struct clk *clk;
 249
 250         clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
 251                         0, 125000000);
 252         clk_register_clkdev(clk, "smii_125m_pad", NULL);
 253
 254         clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
 255                         1, 1);
 256         clk_register_clkdev(clk, NULL, "90000000.clcd");
 257
 258         clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
 259                         1);
 260         clk_register_clkdev(clk, "emi", NULL);
 261
 262         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
 263                         1);
 264         clk_register_clkdev(clk, NULL, "4c000000.flash");
 265
 266         clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
 267                         1);
 268         clk_register_clkdev(clk, NULL, "a7000000.i2c");
 269
 270         clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
 271                         1);
 272         clk_register_clkdev(clk, NULL, "a8000000.pwm");
 273
 274         clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
 275                         1);
 276         clk_register_clkdev(clk, NULL, "a5000000.spi");
 277
 278         clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
 279                         1);
 280         clk_register_clkdev(clk, NULL, "a6000000.spi");
 281
 282         clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
 283                         1);
 284         clk_register_clkdev(clk, NULL, "c_can_platform.0");
 285
 286         clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
 287                         1);
 288         clk_register_clkdev(clk, NULL, "c_can_platform.1");
 289
 290         clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
 291                         1);
 292         clk_register_clkdev(clk, NULL, "a9400000.i2s");
 293
 294         clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
 295                         ARRAY_SIZE(i2s_ref_parents),
 296                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 297                         SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
 298                         I2S_REF_PCLK_MASK, 0, &_lock);
 299         clk_register_clkdev(clk, "i2s_ref_clk", NULL);
 300
 301         clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
 302                         CLK_SET_RATE_PARENT, 1,
 303                         4);
 304         clk_register_clkdev(clk, "i2s_sclk", NULL);
 305
 306         clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
 307                         1);
 308         clk_register_clkdev(clk, "hclk", "aa000000.eth");
 309
 310         clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
 311                         1);
 312         clk_register_clkdev(clk, "hclk", "ab000000.eth");
 313
 314         clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
 315                         ARRAY_SIZE(uartx_parents),
 316                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 317                         SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
 318                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 319         clk_register_clkdev(clk, NULL, "a9300000.serial");
 320
 321         clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
 322                         ARRAY_SIZE(sdhci_parents),
 323                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 324                         SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
 325                         0, &_lock);
 326         clk_register_clkdev(clk, NULL, "70000000.sdhci");
 327
 328         clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
 329                         ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
 330                         SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
 331                         0, &_lock);
 332         clk_register_clkdev(clk, NULL, "smii_pclk");
 333
 334         clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
 335         clk_register_clkdev(clk, NULL, "smii");
 336
 337         clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
 338                         ARRAY_SIZE(uartx_parents),
 339                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 340                         SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
 341                         0, &_lock);
 342         clk_register_clkdev(clk, NULL, "a3000000.serial");
 343         /* Enforce ras_apb_clk */
 344         clk_set_parent(clk, ras_apb_clk);
 345
 346         clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
 347                         ARRAY_SIZE(uartx_parents),
 348                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 349                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
 350                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 351         clk_register_clkdev(clk, NULL, "a4000000.serial");
 352         /* Enforce ras_apb_clk */
 353         clk_set_parent(clk, ras_apb_clk);
 354
 355         clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
 356                         ARRAY_SIZE(uartx_parents),
 357                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 358                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
 359                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 360         clk_register_clkdev(clk, NULL, "a9100000.serial");
 361
 362         clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
 363                         ARRAY_SIZE(uartx_parents),
 364                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 365                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
 366                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 367         clk_register_clkdev(clk, NULL, "a9200000.serial");
 368
 369         clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
 370                         ARRAY_SIZE(uartx_parents),
 371                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 372                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
 373                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 374         clk_register_clkdev(clk, NULL, "60000000.serial");
 375
 376         clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
 377                         ARRAY_SIZE(uartx_parents),
 378                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 379                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
 380                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
 381         clk_register_clkdev(clk, NULL, "60100000.serial");
 382 }
 383 #else
 384 static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
 385 #endif
 386
 387 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
 388 {
 389         struct clk *clk, *clk1, *ras_apb_clk;
 390
 391         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
 392         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 393
 394         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
 395         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 396
 397         /* clock derived from 32 KHz osc clk */
 398         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 399                         PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
 400         clk_register_clkdev(clk, NULL, "fc900000.rtc");
 401
 402         /* clock derived from 24 MHz osc clk */
 403         clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
 404                         48000000);
 405         clk_register_clkdev(clk, "pll3_clk", NULL);
 406
 407         clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
 408                         1);
 409         clk_register_clkdev(clk, NULL, "fc880000.wdt");
 410
 411         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
 412                         "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
 413                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 414         clk_register_clkdev(clk, "vco1_clk", NULL);
 415         clk_register_clkdev(clk1, "pll1_clk", NULL);
 416
 417         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
 418                         "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
 419                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 420         clk_register_clkdev(clk, "vco2_clk", NULL);
 421         clk_register_clkdev(clk1, "pll2_clk", NULL);
 422
 423         /* clock derived from pll1 clk */
 424         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
 425                         CLK_SET_RATE_PARENT, 1, 1);
 426         clk_register_clkdev(clk, "cpu_clk", NULL);
 427
 428         clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
 429                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
 430                         HCLK_RATIO_MASK, 0, &_lock);
 431         clk_register_clkdev(clk, "ahb_clk", NULL);
 432
 433         clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
 434                         UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
 435                         &_lock, &clk1);
 436         clk_register_clkdev(clk, "uart_syn_clk", NULL);
 437         clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 438
 439         clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
 440                         ARRAY_SIZE(uart0_parents),
 441                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 442                         PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
 443                         &_lock);
 444         clk_register_clkdev(clk, "uart0_mclk", NULL);
 445
 446         clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
 447                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0,
 448                         &_lock);
 449         clk_register_clkdev(clk, NULL, "d0000000.serial");
 450
 451         clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
 452                         FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
 453                         &_lock, &clk1);
 454         clk_register_clkdev(clk, "firda_syn_clk", NULL);
 455         clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
 456
 457         clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
 458                         ARRAY_SIZE(firda_parents),
 459                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 460                         PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
 461                         &_lock);
 462         clk_register_clkdev(clk, "firda_mclk", NULL);
 463
 464         clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
 465                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,
 466                         &_lock);
 467         clk_register_clkdev(clk, NULL, "firda");
 468
 469         /* gpt clocks */
 470         clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
 471                         ARRAY_SIZE(gpt_rtbl), &_lock);
 472         clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
 473                         ARRAY_SIZE(gpt0_parents),
 474                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 475                         PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 476         clk_register_clkdev(clk, NULL, "gpt0");
 477
 478         clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
 479                         ARRAY_SIZE(gpt_rtbl), &_lock);
 480         clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
 481                         ARRAY_SIZE(gpt1_parents),
 482                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 483                         PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 484         clk_register_clkdev(clk, "gpt1_mclk", NULL);
 485         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
 486                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0,
 487                         &_lock);
 488         clk_register_clkdev(clk, NULL, "gpt1");
 489
 490         clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
 491                         ARRAY_SIZE(gpt_rtbl), &_lock);
 492         clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
 493                         ARRAY_SIZE(gpt2_parents),
 494                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 495                         PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 496         clk_register_clkdev(clk, "gpt2_mclk", NULL);
 497         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
 498                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0,
 499                         &_lock);
 500         clk_register_clkdev(clk, NULL, "gpt2");
 501
 502         /* general synths clocks */
 503         clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
 504                         0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
 505                         &_lock, &clk1);
 506         clk_register_clkdev(clk, "gen0_syn_clk", NULL);
 507         clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
 508
 509         clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
 510                         0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
 511                         &_lock, &clk1);
 512         clk_register_clkdev(clk, "gen1_syn_clk", NULL);
 513         clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
 514
 515         clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
 516                         ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
 517                         CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
 518                         GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
 519         clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
 520
 521         clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
 522                         "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
 523                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 524         clk_register_clkdev(clk, "gen2_syn_clk", NULL);
 525         clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
 526
 527         clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
 528                         "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
 529                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 530         clk_register_clkdev(clk, "gen3_syn_clk", NULL);
 531         clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
 532
 533         /* clock derived from pll3 clk */
 534         clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
 535                         USBH_CLK_ENB, 0, &_lock);
 536         clk_register_clkdev(clk, NULL, "e1800000.ehci");
 537         clk_register_clkdev(clk, NULL, "e1900000.ohci");
 538         clk_register_clkdev(clk, NULL, "e2100000.ohci");
 539
 540         clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
 541                         1);
 542         clk_register_clkdev(clk, "usbh.0_clk", NULL);
 543
 544         clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
 545                         1);
 546         clk_register_clkdev(clk, "usbh.1_clk", NULL);
 547
 548         clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
 549                         USBD_CLK_ENB, 0, &_lock);
 550         clk_register_clkdev(clk, NULL, "e1100000.usbd");
 551
 552         /* clock derived from ahb clk */
 553         clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
 554                         1);
 555         clk_register_clkdev(clk, "ahbmult2_clk", NULL);
 556
 557         clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
 558                         ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
 559                         PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
 560         clk_register_clkdev(clk, "ddr_clk", NULL);
 561
 562         clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
 563                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
 564                         PCLK_RATIO_MASK, 0, &_lock);
 565         clk_register_clkdev(clk, "apb_clk", NULL);
 566
 567         clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
 568                         AMEM_CLK_ENB, 0, &_lock);
 569         clk_register_clkdev(clk, "amem_clk", NULL);
 570
 571         clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 572                         C3_CLK_ENB, 0, &_lock);
 573         clk_register_clkdev(clk, NULL, "c3_clk");
 574
 575         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 576                         DMA_CLK_ENB, 0, &_lock);
 577         clk_register_clkdev(clk, NULL, "fc400000.dma");
 578
 579         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 580                         GMAC_CLK_ENB, 0, &_lock);
 581         clk_register_clkdev(clk, NULL, "e0800000.eth");
 582
 583         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 584                         I2C_CLK_ENB, 0, &_lock);
 585         clk_register_clkdev(clk, NULL, "d0180000.i2c");
 586
 587         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 588                         JPEG_CLK_ENB, 0, &_lock);
 589         clk_register_clkdev(clk, NULL, "jpeg");
 590
 591         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 592                         SMI_CLK_ENB, 0, &_lock);
 593         clk_register_clkdev(clk, NULL, "fc000000.flash");
 594
 595         /* clock derived from apb clk */
 596         clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 597                         ADC_CLK_ENB, 0, &_lock);
 598         clk_register_clkdev(clk, NULL, "d0080000.adc");
 599
 600         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 601                         GPIO_CLK_ENB, 0, &_lock);
 602         clk_register_clkdev(clk, NULL, "fc980000.gpio");
 603
 604         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 605                         SSP_CLK_ENB, 0, &_lock);
 606         clk_register_clkdev(clk, NULL, "d0100000.spi");
 607
 608         /* RAS clk enable */
 609         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
 610                         RAS_AHB_CLK_ENB, 0, &_lock);
 611         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
 612
 613         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
 614                         RAS_APB_CLK_ENB, 0, &_lock);
 615         clk_register_clkdev(clk, "ras_apb_clk", NULL);
 616         ras_apb_clk = clk;
 617
 618         clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
 619                         RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
 620         clk_register_clkdev(clk, "ras_32k_clk", NULL);
 621
 622         clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
 623                         RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
 624         clk_register_clkdev(clk, "ras_24m_clk", NULL);
 625
 626         clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
 627                         RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
 628         clk_register_clkdev(clk, "ras_pll1_clk", NULL);
 629
 630         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
 631                         RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
 632         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
 633
 634         clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
 635                         RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
 636         clk_register_clkdev(clk, "ras_pll3_clk", NULL);
 637
 638         clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
 639                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
 640                         &_lock);
 641         clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
 642
 643         clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
 644                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
 645                         &_lock);
 646         clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
 647
 648         clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
 649                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
 650                         &_lock);
 651         clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
 652
 653         clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
 654                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,
 655                         &_lock);
 656         clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
 657
 658         if (of_machine_is_compatible("st,spear300"))
 659                 spear300_clk_init();
 660         else if (of_machine_is_compatible("st,spear310"))
 661                 spear310_clk_init();
 662         else if (of_machine_is_compatible("st,spear320"))
 663                 spear320_clk_init(soc_config_base, ras_apb_clk);
 664 }