Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: StarFive JH7100 Pin Controller
   8
   9 description: |
  10   Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
  11
  12   Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
  13   and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
  14   configurable bias, drive strength, schmitt trigger etc. The SoC has an
  15   interesting 2-layered approach to pin muxing best illustrated by the diagram
  16   below.
  17
  18                           Signal group 0, 1, ... or 6
  19                                  ___|___
  20                                 |       |
  21     LCD output -----------------|       |
  22     CMOS Camera interface ------|       |--- PAD_GPIO[0]
  23     Ethernet PHY interface -----|  MUX  |--- PAD_GPIO[1]
  24       ...                       |       |      ...
  25                                 |       |--- PAD_GPIO[63]
  26      -------- GPIO0 ------------|       |
  27     |  -------|-- GPIO1 --------|       |--- PAD_FUNC_SHARE[0]
  28     | |       |   |             |       |--- PAD_FUNC_SHARE[1]
  29     | |       |   |  ...        |       |       ...
  30     | |       |   |             |       |--- PAD_FUNC_SHARE[141]
  31     | |  -----|---|-- GPIO63 ---|       |
  32     | | |     |   |   |          -------
  33     UART0     UART1 --
  34
  35
  36   The big MUX in the diagram only has 7 different ways of mapping peripherals
  37   on the left to pins on the right. StarFive calls the 7 configurations "signal
  38   groups".
  39   However some peripherals have their I/O go through the 64 "GPIOs". The
  40   diagram only shows UART0 and UART1, but this also includes a number of other
  41   UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
  42   GPIOs such that any GPIO can be set up to be controlled by any of the
  43   peripherals.
  44   Note that signal group 0 doesn't map any of the GPIOs to pins, and only
  45   signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
  46
  47 maintainers:
  48   - Emil Renner Berthing <kernel@esmil.dk>
  49   - Drew Fustini <drew@beagleboard.org>
  50
  51 properties:
  52   compatible:
  53     const: starfive,jh7100-pinctrl
  54
  55   reg:
  56     minItems: 2
  57     maxItems: 2
  58
  59   reg-names:
  60     items:
  61       - const: gpio
  62       - const: padctl
  63
  64   clocks:
  65     maxItems: 1
  66
  67   resets:
  68     maxItems: 1
  69
  70   gpio-controller: true
  71
  72   "#gpio-cells":
  73     const: 2
  74
  75   interrupts:
  76     maxItems: 1
  77     description: The GPIO parent interrupt.
  78
  79   interrupt-controller: true
  80
  81   "#interrupt-cells":
  82     const: 2
  83
  84   starfive,signal-group:
  85     description: |
  86       Select one of the 7 signal groups. If this property is not set it
  87       defaults to the configuration already chosen by the earlier boot stages.
  88     $ref: /schemas/types.yaml#/definitions/uint32
  89     enum: [0, 1, 2, 3, 4, 5, 6]
  90
  91 required:
  92   - compatible
  93   - reg
  94   - reg-names
  95   - clocks
  96   - gpio-controller
  97   - "#gpio-cells"
  98   - interrupts
  99   - interrupt-controller
 100   - "#interrupt-cells"
 101
 102 patternProperties:
 103   '-[0-9]+$':
 104     type: object
 105     patternProperties:
 106       '-pins$':
 107         type: object
 108         description: |
 109           A pinctrl node should contain at least one subnode representing the
 110           pinctrl groups available on the machine. Each subnode will list the
 111           pins it needs, and how they should be configured, with regard to
 112           muxer configuration, bias, input enable/disable, input schmitt
 113           trigger enable/disable, slew-rate and drive strength.
 114         $ref: "/schemas/pinctrl/pincfg-node.yaml"
 115
 116         properties:
 117           pins:
 118             description: |
 119               The list of pin identifiers that properties in the node apply to.
 120               This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
 121               macros.
 122               Either this or "pinmux" has to be specified, but not both.
 123             $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"
 124
 125           pinmux:
 126             description: |
 127               The list of GPIOs and their mux settings that properties in the
 128               node apply to. This should be set using the GPIOMUX macro.
 129               Either this or "pins" has to be specified, but not both.
 130             $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
 131
 132           bias-disable: true
 133
 134           bias-pull-up:
 135             type: boolean
 136
 137           bias-pull-down:
 138             type: boolean
 139
 140           drive-strength:
 141             enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
 142
 143           input-enable: true
 144
 145           input-disable: true
 146
 147           input-schmitt-enable: true
 148
 149           input-schmitt-disable: true
 150
 151           slew-rate:
 152             maximum: 7
 153
 154           starfive,strong-pull-up:
 155             description: enable strong pull-up.
 156             type: boolean
 157
 158         additionalProperties: false
 159
 160     additionalProperties: false
 161
 162 additionalProperties: false
 163
 164 examples:
 165   - |
 166     #include <dt-bindings/clock/starfive-jh7100.h>
 167     #include <dt-bindings/reset/starfive-jh7100.h>
 168     #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
 169
 170     soc {
 171         #address-cells = <2>;
 172         #size-cells = <2>;
 173
 174         pinctrl@11910000 {
 175             compatible = "starfive,jh7100-pinctrl";
 176             reg = <0x0 0x11910000 0x0 0x10000>,
 177                   <0x0 0x11858000 0x0 0x1000>;
 178             reg-names = "gpio", "padctl";
 179             clocks = <&clkgen JH7100_CLK_GPIO_APB>;
 180             resets = <&clkgen JH7100_RSTN_GPIO_APB>;
 181             interrupts = <32>;
 182             gpio-controller;
 183             #gpio-cells = <2>;
 184             interrupt-controller;
 185             #interrupt-cells = <2>;
 186             starfive,signal-group = <6>;
 187
 188             gmac_pins_default: gmac-0 {
 189                 gtxclk-pins {
 190                     pins = <PAD_FUNC_SHARE(115)>;
 191                     bias-pull-up;
 192                     drive-strength = <35>;
 193                     input-enable;
 194                     input-schmitt-enable;
 195                     slew-rate = <0>;
 196                 };
 197                 miitxclk-pins {
 198                     pins = <PAD_FUNC_SHARE(116)>;
 199                     bias-pull-up;
 200                     drive-strength = <14>;
 201                     input-enable;
 202                     input-schmitt-disable;
 203                     slew-rate = <0>;
 204                 };
 205                 tx-pins {
 206                     pins = <PAD_FUNC_SHARE(117)>,
 207                            <PAD_FUNC_SHARE(119)>,
 208                            <PAD_FUNC_SHARE(120)>,
 209                            <PAD_FUNC_SHARE(121)>,
 210                            <PAD_FUNC_SHARE(122)>,
 211                            <PAD_FUNC_SHARE(123)>,
 212                            <PAD_FUNC_SHARE(124)>,
 213                            <PAD_FUNC_SHARE(125)>,
 214                            <PAD_FUNC_SHARE(126)>;
 215                     bias-disable;
 216                     drive-strength = <35>;
 217                     input-disable;
 218                     input-schmitt-disable;
 219                     slew-rate = <0>;
 220                 };
 221                 rxclk-pins {
 222                     pins = <PAD_FUNC_SHARE(127)>;
 223                     bias-pull-up;
 224                     drive-strength = <14>;
 225                     input-enable;
 226                     input-schmitt-disable;
 227                     slew-rate = <6>;
 228                 };
 229                 rxer-pins {
 230                     pins = <PAD_FUNC_SHARE(129)>;
 231                     bias-pull-up;
 232                     drive-strength = <14>;
 233                     input-enable;
 234                     input-schmitt-disable;
 235                     slew-rate = <0>;
 236                 };
 237                 rx-pins {
 238                     pins = <PAD_FUNC_SHARE(128)>,
 239                            <PAD_FUNC_SHARE(130)>,
 240                            <PAD_FUNC_SHARE(131)>,
 241                            <PAD_FUNC_SHARE(132)>,
 242                            <PAD_FUNC_SHARE(133)>,
 243                            <PAD_FUNC_SHARE(134)>,
 244                            <PAD_FUNC_SHARE(135)>,
 245                            <PAD_FUNC_SHARE(136)>,
 246                            <PAD_FUNC_SHARE(137)>,
 247                            <PAD_FUNC_SHARE(138)>,
 248                            <PAD_FUNC_SHARE(139)>,
 249                            <PAD_FUNC_SHARE(140)>,
 250                            <PAD_FUNC_SHARE(141)>;
 251                     bias-pull-up;
 252                     drive-strength = <14>;
 253                     input-enable;
 254                     input-schmitt-enable;
 255                     slew-rate = <0>;
 256                 };
 257             };
 258
 259             i2c0_pins_default: i2c0-0 {
 260                 i2c-pins {
 261                     pinmux = <GPIOMUX(62, GPO_LOW,
 262                               GPO_I2C0_PAD_SCK_OEN,
 263                               GPI_I2C0_PAD_SCK_IN)>,
 264                              <GPIOMUX(61, GPO_LOW,
 265                               GPO_I2C0_PAD_SDA_OEN,
 266                               GPI_I2C0_PAD_SDA_IN)>;
 267                     bias-disable; /* external pull-up */
 268                     input-enable;
 269                     input-schmitt-enable;
 270                 };
 271             };
 272
 273             uart3_pins_default: uart3-0 {
 274                 rx-pins {
 275                     pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
 276                               GPI_UART3_PAD_SIN)>;
 277                     bias-pull-up;
 278                     input-enable;
 279                     input-schmitt-enable;
 280                 };
 281                 tx-pins {
 282                     pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
 283                               GPO_ENABLE, GPI_NONE)>;
 284                     bias-disable;
 285                     input-disable;
 286                     input-schmitt-disable;
 287                 };
 288             };
 289         };
 290
 291         gmac {
 292             pinctrl-0 = <&gmac_pins_default>;
 293             pinctrl-names = "default";
 294         };
 295
 296         i2c0 {
 297             pinctrl-0 = <&i2c0_pins_default>;
 298             pinctrl-names = "default";
 299         };
 300
 301         uart3 {
 302             pinctrl-0 = <&uart3_pins_default>;
 303             pinctrl-names = "default";
 304         };
 305     };
 306
 307 ...