Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM8250 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11
  12 description: |
  13   This binding describes the Top Level Mode Multiplexer block found in the
  14   SM8250 platform.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sm8250-pinctrl
  19
  20   reg:
  21     minItems: 3
  22     maxItems: 3
  23
  24   reg-names:
  25     items:
  26       - const: "west"
  27       - const: "south"
  28       - const: "north"
  29
  30   interrupts:
  31     description: Specifies the TLMM summary IRQ
  32     maxItems: 1
  33
  34   interrupt-controller: true
  35
  36   '#interrupt-cells':
  37     description:
  38       Specifies the PIN numbers and Flags, as defined in defined in
  39       include/dt-bindings/interrupt-controller/irq.h
  40     const: 2
  41
  42   gpio-controller: true
  43
  44   '#gpio-cells':
  45     description: Specifying the pin number and flags, as defined in
  46       include/dt-bindings/gpio/gpio.h
  47     const: 2
  48
  49   gpio-ranges:
  50     maxItems: 1
  51
  52   wakeup-parent: true
  53
  54 #PIN CONFIGURATION NODES
  55 patternProperties:
  56   '^.*$':
  57     if:
  58       type: object
  59     then:
  60       properties:
  61         pins:
  62           description:
  63             List of gpio pins affected by the properties specified in this
  64             subnode.
  65           items:
  66             oneOf:
  67               - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
  68               - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
  69           minItems: 1
  70           maxItems: 36
  71
  72         function:
  73           description:
  74             Specify the alternative function to be configured for the specified
  75             pins.
  76
  77           enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
  78                   cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
  79                   cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
  80                   ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
  81                   ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
  82                   mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
  83                   mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
  84                   mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
  85                   pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
  86                   pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
  87                   qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
  88                   qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
  89                   qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
  90                   sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
  91                   tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
  92                   tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
  93                   tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
  94
  95         drive-strength:
  96           enum: [2, 4, 6, 8, 10, 12, 14, 16]
  97           default: 2
  98           description:
  99             Selects the drive strength for the specified pins, in mA.
 100
 101         bias-pull-down: true
 102
 103         bias-pull-up: true
 104
 105         bias-disable: true
 106
 107         output-high: true
 108
 109         output-low: true
 110
 111       required:
 112         - pins
 113         - function
 114
 115       additionalProperties: false
 116
 117 allOf:
 118   - $ref: "pinctrl.yaml#"
 119
 120 required:
 121   - compatible
 122   - reg
 123   - reg-names
 124   - interrupts
 125   - interrupt-controller
 126   - '#interrupt-cells'
 127   - gpio-controller
 128   - '#gpio-cells'
 129   - gpio-ranges
 130
 131 additionalProperties: false
 132
 133 examples:
 134   - |
 135         #include <dt-bindings/interrupt-controller/arm-gic.h>
 136         pinctrl@1f00000 {
 137                 compatible = "qcom,sm8250-pinctrl";
 138                 reg = <0x0f100000 0x300000>,
 139                       <0x0f500000 0x300000>,
 140                       <0x0f900000 0x300000>;
 141                 reg-names = "west", "south", "north";
 142                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 143                 gpio-controller;
 144                 #gpio-cells = <2>;
 145                 interrupt-controller;
 146                 #interrupt-cells = <2>;
 147                 gpio-ranges = <&tlmm 0 0 180>;
 148                 wakeup-parent = <&pdc>;
 149         };