Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
   8
   9 maintainers:
  10   - Iskren Chernev <iskren.chernev@gmail.com>
  11
  12 description:
  13   This binding describes the Top Level Mode Multiplexer block found in the
  14   SM4250/6115 platforms.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sm6115-tlmm
  19
  20   reg:
  21     minItems: 3
  22     maxItems: 3
  23
  24   reg-names:
  25     items:
  26       - const: west
  27       - const: south
  28       - const: east
  29
  30   interrupts:
  31     description: Specifies the TLMM summary IRQ
  32     maxItems: 1
  33
  34   interrupt-controller: true
  35
  36   '#interrupt-cells':
  37     description:
  38       Specifies the PIN numbers and Flags, as defined in defined in
  39       include/dt-bindings/interrupt-controller/irq.h
  40     const: 2
  41
  42   gpio-controller: true
  43
  44   '#gpio-cells':
  45     description: Specifying the pin number and flags, as defined in
  46       include/dt-bindings/gpio/gpio.h
  47     const: 2
  48
  49   gpio-ranges:
  50     maxItems: 1
  51
  52   gpio-reserved-ranges: true
  53
  54   wakeup-parent: true
  55
  56 #PIN CONFIGURATION NODES
  57 patternProperties:
  58   '-state$':
  59     oneOf:
  60       - $ref: "#/$defs/qcom-sm6115-tlmm-state"
  61       - patternProperties:
  62           "-pins$":
  63             $ref: "#/$defs/qcom-sm6115-tlmm-state"
  64         additionalProperties: false
  65
  66 '$defs':
  67   qcom-sm6115-tlmm-state:
  68     type: object
  69     description:
  70       Pinctrl node's client devices use subnodes for desired pin configuration.
  71       Client device subnodes use below standard properties.
  72
  73     properties:
  74       pins:
  75         description:
  76           List of gpio pins affected by the properties specified in this
  77           subnode.
  78         items:
  79           oneOf:
  80             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
  81             - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
  82                       sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
  83         minItems: 1
  84         maxItems: 36
  85
  86       function:
  87         description:
  88           Specify the alternative function to be configured for the specified
  89           pins.
  90
  91         enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
  92                 cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
  93                 ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
  94                 gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
  95                 mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
  96                 m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
  97                 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
  98                 qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
  99                 sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
 100                 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
 101                 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
 102                 wlan1_adc0, elan1_adc1 ]
 103
 104       drive-strength:
 105         enum: [2, 4, 6, 8, 10, 12, 14, 16]
 106         default: 2
 107         description:
 108           Selects the drive strength for the specified pins, in mA.
 109
 110       bias-pull-down: true
 111
 112       bias-pull-up: true
 113
 114       bias-disable: true
 115
 116       output-high: true
 117
 118       output-low: true
 119
 120     required:
 121       - pins
 122
 123     allOf:
 124       - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
 125       - if:
 126           properties:
 127             pins:
 128               pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
 129         then:
 130           required:
 131             - function
 132
 133     additionalProperties: false
 134
 135 allOf:
 136   - $ref: "pinctrl.yaml#"
 137
 138 required:
 139   - compatible
 140   - reg
 141   - reg-names
 142   - interrupts
 143   - interrupt-controller
 144   - '#interrupt-cells'
 145   - gpio-controller
 146   - '#gpio-cells'
 147   - gpio-ranges
 148
 149 additionalProperties: false
 150
 151 examples:
 152   - |
 153     #include <dt-bindings/interrupt-controller/arm-gic.h>
 154     tlmm: pinctrl@500000 {
 155         compatible = "qcom,sm6115-tlmm";
 156         reg = <0x500000 0x400000>,
 157               <0x900000 0x400000>,
 158               <0xd00000 0x400000>;
 159         reg-names = "west", "south", "east";
 160         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 161         gpio-controller;
 162         #gpio-cells = <2>;
 163         interrupt-controller;
 164         #interrupt-cells = <2>;
 165         gpio-ranges = <&tlmm 0 0 114>;
 166
 167         sdc2_on_state: sdc2-on-state {
 168             clk-pins {
 169                 pins = "sdc2_clk";
 170                 bias-disable;
 171                 drive-strength = <16>;
 172             };
 173
 174             cmd-pins {
 175                 pins = "sdc2_cmd";
 176                 bias-pull-up;
 177                 drive-strength = <10>;
 178             };
 179
 180             data-pins {
 181                 pins = "sdc2_data";
 182                 bias-pull-up;
 183                 drive-strength = <10>;
 184             };
 185
 186             sd-cd-pins {
 187                 pins = "gpio88";
 188                 function = "gpio";
 189                 bias-pull-up;
 190                 drive-strength = <2>;
 191             };
 192         };
 193     };