Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SC8280XP TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <bjorn.andersson@linaro.org>
  11
  12 description: |
  13   This binding describes the Top Level Mode Multiplexer block found in the
  14   SC8280XP platform.
  15
  16 allOf:
  17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sc8280xp-tlmm
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts: true
  27   interrupt-controller: true
  28   '#interrupt-cells': true
  29   gpio-controller: true
  30   gpio-reserved-ranges: true
  31   '#gpio-cells': true
  32   gpio-ranges: true
  33   wakeup-parent: true
  34
  35 required:
  36   - compatible
  37   - reg
  38
  39 additionalProperties: false
  40
  41 patternProperties:
  42   '-state$':
  43     oneOf:
  44       - $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
  45       - patternProperties:
  46           ".*":
  47             $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
  48
  49 '$defs':
  50   qcom-sc8280xp-tlmm-state:
  51     type: object
  52     description:
  53       Pinctrl node's client devices use subnodes for desired pin configuration.
  54       Client device subnodes use below standard properties.
  55     $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
  56
  57     properties:
  58       pins:
  59         description:
  60           List of gpio pins affected by the properties specified in this
  61           subnode.
  62         items:
  63           oneOf:
  64             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
  65             - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
  66         minItems: 1
  67         maxItems: 16
  68
  69       function:
  70         description:
  71           Specify the alternative function to be configured for the specified
  72           pins.
  73
  74         enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
  75                 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
  76                 cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
  77                 cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
  78                 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
  79                 ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
  80                 edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
  81                 emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
  82                 emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
  83                 emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
  84                 gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
  85                 jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
  86                 mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
  87                 mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
  88                 mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
  89                 mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
  90                 mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
  91                 mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
  92                 mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
  93                 pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
  94                 phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
  95                 prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
  96                 qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
  97                 qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
  98                 qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
  99                 sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
 100                 tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
 101                 usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
 102                 usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
 103                 vsense_trigger ]
 104
 105       bias-disable: true
 106       bias-pull-down: true
 107       bias-pull-up: true
 108       drive-strength: true
 109       input-enable: true
 110       output-high: true
 111       output-low: true
 112
 113     required:
 114       - pins
 115       - function
 116
 117     additionalProperties: false
 118
 119 examples:
 120   - |
 121         #include <dt-bindings/interrupt-controller/arm-gic.h>
 122         pinctrl@f100000 {
 123                 compatible = "qcom,sc8280xp-tlmm";
 124                 reg = <0x0f100000 0x300000>;
 125                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 126                 gpio-controller;
 127                 #gpio-cells = <2>;
 128                 interrupt-controller;
 129                 #interrupt-cells = <2>;
 130                 gpio-ranges = <&tlmm 0 0 230>;
 131
 132                 gpio-wo-subnode-state {
 133                         pins = "gpio1";
 134                         function = "gpio";
 135                 };
 136
 137                 uart-w-subnodes-state {
 138                         rx {
 139                                 pins = "gpio4";
 140                                 function = "qup14";
 141                                 bias-pull-up;
 142                         };
 143
 144                         tx {
 145                                 pins = "gpio5";
 146                                 function = "qup14";
 147                                 bias-disable;
 148                         };
 149                 };
 150         };
 151 ...