Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SC7280 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description: |
  13   This binding describes the Top Level Mode Multiplexer block found in the
  14   SC7280 platform.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sc7280-pinctrl
  19
  20   reg:
  21     maxItems: 1
  22
  23   interrupts:
  24     description: Specifies the TLMM summary IRQ
  25     maxItems: 1
  26
  27   interrupt-controller: true
  28
  29   '#interrupt-cells':
  30     description:
  31       Specifies the PIN numbers and Flags, as defined in defined in
  32       include/dt-bindings/interrupt-controller/irq.h
  33     const: 2
  34
  35   gpio-controller: true
  36
  37   '#gpio-cells':
  38     description: Specifying the pin number and flags, as defined in
  39       include/dt-bindings/gpio/gpio.h
  40     const: 2
  41
  42   gpio-ranges:
  43     maxItems: 1
  44
  45   gpio-line-names:
  46     maxItems: 174
  47
  48   wakeup-parent: true
  49
  50 #PIN CONFIGURATION NODES
  51 patternProperties:
  52   '-pins$':
  53     type: object
  54     description:
  55       Pinctrl node's client devices use subnodes for desired pin configuration.
  56       Client device subnodes use below standard properties.
  57
  58     properties:
  59       pins:
  60         description:
  61           List of gpio pins affected by the properties specified in this
  62           subnode.
  63         items:
  64           oneOf:
  65             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
  66             - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
  67                       sdc2_cmd, sdc2_data, ufs_reset ]
  68         minItems: 1
  69         maxItems: 16
  70
  71       function:
  72         description:
  73           Specify the alternative function to be configured for the specified
  74           pins.
  75
  76         enum: [ atest_char, atest_char0, atest_char1, atest_char2,
  77                 atest_char3, atest_usb0, atest_usb00, atest_usb01,
  78                 atest_usb02, atest_usb03, atest_usb1, atest_usb10,
  79                 atest_usb11, atest_usb12, atest_usb13, audio_ref,
  80                 cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
  81                 cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
  82                 cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
  83                 cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
  84                 dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
  85                 gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
  86                 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
  87                 mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
  88                 mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
  89                 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
  90                 mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
  91                 mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
  92                 mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
  93                 pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
  94                 pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
  95                 qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
  96                 qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
  97                 qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
  98                 qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
  99                 sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
 100                 sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
 101                 tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
 102                 uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
 103                 usb_phy, vfr_0, vfr_1, vsense_trigger ]
 104
 105       drive-strength:
 106         enum: [2, 4, 6, 8, 10, 12, 14, 16]
 107         default: 2
 108         description:
 109           Selects the drive strength for the specified pins, in mA.
 110
 111       bias-pull-down: true
 112
 113       bias-pull-up: true
 114
 115       bias-disable: true
 116
 117       output-high: true
 118
 119       output-low: true
 120
 121     required:
 122       - pins
 123
 124     allOf:
 125       - $ref: /schemas/pinctrl/pincfg-node.yaml
 126       - if:
 127           properties:
 128             pins:
 129               pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
 130         then:
 131           required:
 132             - function
 133
 134     additionalProperties: false
 135
 136 allOf:
 137   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 138
 139 required:
 140   - compatible
 141   - reg
 142   - interrupts
 143   - interrupt-controller
 144   - '#interrupt-cells'
 145   - gpio-controller
 146   - '#gpio-cells'
 147   - gpio-ranges
 148
 149 additionalProperties: false
 150
 151 examples:
 152   - |
 153     #include <dt-bindings/interrupt-controller/arm-gic.h>
 154     tlmm: pinctrl@f000000 {
 155         compatible = "qcom,sc7280-pinctrl";
 156         reg = <0xf000000 0x1000000>;
 157         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 158         gpio-controller;
 159         #gpio-cells = <2>;
 160         interrupt-controller;
 161         #interrupt-cells = <2>;
 162         gpio-ranges = <&tlmm 0 0 175>;
 163         wakeup-parent = <&pdc>;
 164
 165         qup_uart5_default: qup-uart5-pins {
 166             pins = "gpio46", "gpio47";
 167             function = "qup13";
 168             drive-strength = <2>;
 169             bias-disable;
 170         };
 171     };