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clk: sunxi: pll2: Add A13 support
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 21 Sep 2015 11:32:43 +0000 (13:32 +0200)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 21 Oct 2015 19:51:28 +0000 (21:51 +0200)
commiteb662f854710e6a438789a4b0d1d0cce8c12379d
tree1550ceffb453194a49357c0321b0c6dd56b279batree
parent460d0d444822e9032a2573fc051b45c68b89a97acommit | diff
clk: sunxi: pll2: Add A13 support

The A13, unlike the A10 and A20, doesn't use a pass-through exception for
the 0 value in the pre and post dividers, but increments all the values
written in the register by one.

Add an exception for both these cases to handle them nicely.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
drivers/clk/sunxi/clk-a10-pll2.c diff | blob | history
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