drm/amd/display: Use new num clk levels struct for max mclk index
authorDillon Varone <Dillon.Varone@amd.com>
Fri, 11 Nov 2022 19:06:58 +0000 (14:06 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Nov 2022 14:01:53 +0000 (09:01 -0500)
commite667ee3b0c049bf0c69426879586a2572bb28d26
treee1247aed16850beba7d76e2eed7c5f995b26ead7
parent2a5dd86a69ea5435f1a837bdb7fafcda609a7c91
drm/amd/display: Use new num clk levels struct for max mclk index

[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.

[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c