MIPS: Tidy up CP0.Config6 bits definition
authorHuacai Chen <chenhc@lemote.com>
Sat, 23 May 2020 07:51:45 +0000 (15:51 +0800)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Sun, 24 May 2020 07:24:49 +0000 (09:24 +0200)
commit8267e78f020a8de2752754c42ec1d56e92431477
tree022412532fa0a8ae7f4e8e481696bfd32922c5bb
parent41528ba6afe62d472a729b223f8542ccc1156df1
MIPS: Tidy up CP0.Config6 bits definition

CP0.Config6 is a Vendor-defined register whose bits definitions are
different from one to another. Recently, Xuerui's Loongson-3 patch and
Serge's P5600 patch make the definitions inconsistency and unclear.

To make life easy, this patch tidy the definition up:
1, Add a _MTI_ infix for proAptiv/P5600 feature bits;
2, Add a _LOONGSON_ infix for Loongson-3 feature bits;
3, Add bit6/bit7 definition for Loongson-3 which will be used later.

All existing users of these macros are updated.

Cc: WANG Xuerui <git@xen0n.name>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/include/asm/mipsregs.h
arch/mips/kernel/cpu-probe.c
arch/mips/mm/c-r4k.c