dt-bindings: clk: sun5i: add DRAM gates compatible
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 23 Mar 2016 16:38:28 +0000 (17:38 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 21 Apr 2016 22:29:23 +0000 (00:29 +0200)
commit7f2ea3847d47d49929d41573a3b26c80ddebbef5
treef7a4ab1eadcea14597f1f2ad9bd8cb8bbda6f4a0
parentf4b9ef653c047165f096d32816904be5ee337a63
dt-bindings: clk: sun5i: add DRAM gates compatible

The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Documentation/devicetree/bindings/clock/sunxi.txt