Merge tag 'x86-bugs-2022-06-01' of git://git.kernel.org/pub/scm/linux/kernel/git...

[sfrench/cifs-2.6.git] / tools / arch / x86 / include / asm / msr-index.h

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 4425d6773183b5def8edf9d1f7ba34f4a4a98c64..d27e0581b7777ba086a772453cc52f6afacdcdeb 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -76,6 +76,8 @@
 
 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
 #define MSR_IA32_CORE_CAPS                       0x000000cf
+#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT    2
+#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS        BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT     BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
 
@@ -179,6 +181,11 @@
 #define MSR_IA32_POWER_CTL             0x000001fc
 #define MSR_IA32_POWER_CTL_BIT_EE      19
 
+/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
+#define MSR_INTEGRITY_CAPS                     0x000002d9
+#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT   4
+#define MSR_INTEGRITY_CAPS_PERIODIC_BIST       BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
+
 #define MSR_LBR_NHM_FROM               0x00000680
 #define MSR_LBR_NHM_TO                 0x000006c0
 #define MSR_LBR_CORE_FROM              0x00000040
@@ -337,6 +344,7 @@
 
 /* Run Time Average Power Limiting (RAPL) Interface */
 
+#define MSR_VR_CURRENT_CONFIG  0x00000601
 #define MSR_RAPL_POWER_UNIT            0x00000606
 
 #define MSR_PKG_POWER_LIMIT            0x00000610
@@ -527,8 +535,10 @@
 #define MSR_AMD64_SEV                  0xc0010131
 #define MSR_AMD64_SEV_ENABLED_BIT      0
 #define MSR_AMD64_SEV_ES_ENABLED_BIT   1
+#define MSR_AMD64_SEV_SNP_ENABLED_BIT  2
 #define MSR_AMD64_SEV_ENABLED          BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
 #define MSR_AMD64_SEV_ES_ENABLED       BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
+#define MSR_AMD64_SEV_SNP_ENABLED      BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
 
 #define MSR_AMD64_VIRT_SPEC_CTRL       0xc001011f
 
@@ -549,6 +559,11 @@
 #define AMD_CPPC_DES_PERF(x)           (((x) & 0xff) << 16)
 #define AMD_CPPC_ENERGY_PERF_PREF(x)   (((x) & 0xff) << 24)
 
+/* AMD Performance Counter Global Status and Control MSRs */
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS      0xc0000300
+#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL         0xc0000301
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR  0xc0000302
+
 /* Fam 17h MSRs */
 #define MSR_F17H_IRPERF                        0xc00000e9
 
@@ -713,6 +728,10 @@
 #define MSR_IA32_PERF_CTL              0x00000199
 #define INTEL_PERF_CTL_MASK            0xffff
 
+/* AMD Branch Sampling configuration */
+#define MSR_AMD_DBG_EXTN_CFG           0xc000010f
+#define MSR_AMD_SAMP_BR_FROM           0xc0010300
+
 #define MSR_IA32_MPERF                 0x000000e7
 #define MSR_IA32_APERF                 0x000000e8