Merge tag 'sound-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...

[sfrench/cifs-2.6.git] / sound / soc / sof / intel / hda.h

diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 06476ffe96d73a77cdc74498c130f66e9cdb6313..5ef3e8775e364172b2dd0f69e057e3480872250e 100644 (file)
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -187,6 +187,69 @@
 
 #define HDA_DSP_STACK_DUMP_SIZE                        32
 
+/* ROM/FW status register */
+#define FSR_STATE_MASK                         GENMASK(23, 0)
+#define FSR_WAIT_STATE_MASK                    GENMASK(27, 24)
+#define FSR_MODULE_MASK                                GENMASK(30, 28)
+#define FSR_HALTED                             BIT(31)
+#define FSR_TO_STATE_CODE(x)                   ((x) & FSR_STATE_MASK)
+#define FSR_TO_WAIT_STATE_CODE(x)              (((x) & FSR_WAIT_STATE_MASK) >> 24)
+#define FSR_TO_MODULE_CODE(x)                  (((x) & FSR_MODULE_MASK) >> 28)
+
+/* Wait states */
+#define FSR_WAIT_FOR_IPC_BUSY                  0x1
+#define FSR_WAIT_FOR_IPC_DONE                  0x2
+#define FSR_WAIT_FOR_CACHE_INVALIDATION                0x3
+#define FSR_WAIT_FOR_LP_SRAM_OFF               0x4
+#define FSR_WAIT_FOR_DMA_BUFFER_FULL           0x5
+#define FSR_WAIT_FOR_CSE_CSR                   0x6
+
+/* Module codes */
+#define FSR_MOD_ROM                            0x0
+#define FSR_MOD_ROM_BYP                                0x1
+#define FSR_MOD_BASE_FW                                0x2
+#define FSR_MOD_LP_BOOT                                0x3
+#define FSR_MOD_BRNGUP                         0x4
+#define FSR_MOD_ROM_EXT                                0x5
+
+/* State codes (module dependent) */
+/* Module independent states */
+#define FSR_STATE_INIT                         0x0
+#define FSR_STATE_INIT_DONE                    0x1
+#define FSR_STATE_FW_ENTERED                   0x5
+
+/* ROM states */
+#define FSR_STATE_ROM_INIT                     FSR_STATE_INIT
+#define FSR_STATE_ROM_INIT_DONE                        FSR_STATE_INIT_DONE
+#define FSR_STATE_ROM_CSE_MANIFEST_LOADED      0x2
+#define FSR_STATE_ROM_FW_MANIFEST_LOADED       0x3
+#define FSR_STATE_ROM_FW_FW_LOADED             0x4
+#define FSR_STATE_ROM_FW_ENTERED               FSR_STATE_FW_ENTERED
+#define FSR_STATE_ROM_VERIFY_FEATURE_MASK      0x6
+#define FSR_STATE_ROM_GET_LOAD_OFFSET          0x7
+#define FSR_STATE_ROM_FETCH_ROM_EXT            0x8
+#define FSR_STATE_ROM_FETCH_ROM_EXT_DONE       0x9
+
+/* (ROM) CSE states */
+#define FSR_STATE_ROM_CSE_IMR_REQUEST                  0x10
+#define FSR_STATE_ROM_CSE_IMR_GRANTED                  0x11
+#define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST       0x12
+#define FSR_STATE_ROM_CSE_IMAGE_VALIDATED              0x13
+
+#define FSR_STATE_ROM_CSE_IPC_IFACE_INIT       0x20
+#define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1    0x21
+#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY        0x22
+#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL      0x23
+#define FSR_STATE_ROM_CSE_IPC_DOWN             0x24
+
+/* BRINGUP (or BRNGUP) states */
+#define FSR_STATE_BRINGUP_INIT                 FSR_STATE_INIT
+#define FSR_STATE_BRINGUP_INIT_DONE            FSR_STATE_INIT_DONE
+#define FSR_STATE_BRINGUP_HPSRAM_LOAD          0x2
+#define FSR_STATE_BRINGUP_UNPACK_START         0X3
+#define FSR_STATE_BRINGUP_IMR_RESTORE          0x4
+#define FSR_STATE_BRINGUP_FW_ENTERED           FSR_STATE_FW_ENTERED
+
 /* ROM  status/error values */
 #define HDA_DSP_ROM_STS_MASK                   GENMASK(23, 0)
 #define HDA_DSP_ROM_INIT                       0x1
@@ -419,6 +482,7 @@ enum sof_hda_D0_substate {
 /* represents DSP HDA controller frontend - i.e. host facing control */
 struct sof_intel_hda_dev {
        bool imrboot_supported;
+       bool skip_imr_boot;
 
        int boot_iteration;
 
@@ -605,6 +669,7 @@ struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned
                                              int direction);
 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
                   struct hdac_ext_stream *hext_stream);
+int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
 #define HDA_CL_STREAM_FORMAT 0x40
 
 /* pre and post fw run ops */
@@ -716,6 +781,8 @@ extern struct snd_sof_dsp_ops sof_tgl_ops;
 int sof_tgl_ops_init(struct snd_sof_dev *sdev);
 extern struct snd_sof_dsp_ops sof_icl_ops;
 int sof_icl_ops_init(struct snd_sof_dev *sdev);
+extern struct snd_sof_dsp_ops sof_mtl_ops;
+int sof_mtl_ops_init(struct snd_sof_dev *sdev);
 
 extern const struct sof_intel_dsp_desc apl_chip_info;
 extern const struct sof_intel_dsp_desc cnl_chip_info;
@@ -725,6 +792,7 @@ extern const struct sof_intel_dsp_desc tglh_chip_info;
 extern const struct sof_intel_dsp_desc ehl_chip_info;
 extern const struct sof_intel_dsp_desc jsl_chip_info;
 extern const struct sof_intel_dsp_desc adls_chip_info;
+extern const struct sof_intel_dsp_desc mtl_chip_info;
 
 /* Probes support */
 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
@@ -767,11 +835,13 @@ int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_f
 extern int sof_hda_position_quirk;
 
 void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops);
+void hda_ops_free(struct snd_sof_dev *sdev);
 
 /* IPC4 */
 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context);
 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
 irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context);
 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
+extern struct sdw_intel_ops sdw_callback;
 
 #endif