x86: update reference for PAE tlb flushing

[sfrench/cifs-2.6.git] / include / asm-x86 / pgtable-3level.h

diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h
index ad71960bca3acc9ac0fb803db76c3a412aa605a4..1d763eec740ff882c329889db1a9ae7006ac8817 100644 (file)
--- a/include/asm-x86/pgtable-3level.h
+++ b/include/asm-x86/pgtable-3level.h
@@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp)
        set_pud(pudp, __pud(0));
 
        /*
-        * Pentium-II erratum A13: in PAE mode we explicitly have to flush
-        * the TLB via cr3 if the top-level pgd is changed...
+        * According to Intel App note "TLBs, Paging-Structure Caches,
+        * and Their Invalidation", April 2007, document 317080-001,
+        * section 8.1: in PAE mode we explicitly have to flush the
+        * TLB via cr3 if the top-level pgd is changed...
         *
         * Make sure the pud entry we're updating is within the
         * current pgd to avoid unnecessary TLB flushes.