Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel...

[sfrench/cifs-2.6.git] / drivers / perf / Kconfig

diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 54ff5cc17ccdb459bfa430331060abfd68ea6da2..7526a9e714fa985d79d20b77003483a81f7b60a7 100644 (file)
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -96,6 +96,20 @@ config STARFIVE_STARLINK_PMU
           an L3 memory system. The L3 cache events are added into perf event
           subsystem, allowing monitoring of various L3 cache perf events.
 
+config ANDES_CUSTOM_PMU
+       bool "Andes custom PMU support"
+       depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
+       default y
+       help
+         The Andes cores implement the PMU overflow extension very
+         similar to the standard Sscofpmf and Smcntrpmf extension.
+
+         This will patch the overflow and pending CSRs and handle the
+         non-standard behaviour via the regular SBI PMU driver and
+         interface.
+
+         If you don't know what to do here, say "Y".
+
 config ARM_PMU_ACPI
        depends on ARM_PMU && ACPI
        def_bool y