PCI: dwc: Refactor core initialization code for EP mode

[sfrench/cifs-2.6.git] / drivers / pci / controller / dwc / pcie-designware-ep.c

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index cfeccd7e9fff29bd5a116ad0d8b4e5ef28c07a34..84a102df9f621e6d45b3dd0c80d263fe6478e50e 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -492,19 +492,53 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
        return 0;
 }
 
-int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 {
+       struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+       unsigned int offset;
+       unsigned int nbars;
+       u8 hdr_type;
+       u32 reg;
        int i;
+
+       hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+       if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
+               dev_err(pci->dev,
+                       "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
+                       hdr_type);
+               return -EIO;
+       }
+
+       ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
+
+       ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
+
+       offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
+       if (offset) {
+               reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
+               nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
+                       PCI_REBAR_CTRL_NBAR_SHIFT;
+
+               dw_pcie_dbi_ro_wr_en(pci);
+               for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
+                       dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
+               dw_pcie_dbi_ro_wr_dis(pci);
+       }
+
+       dw_pcie_setup(pci);
+
+       return 0;
+}
+
+int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+{
        int ret;
-       u32 reg;
        void *addr;
-       u8 hdr_type;
-       unsigned int nbars;
-       unsigned int offset;
        struct pci_epc *epc;
        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
        struct device *dev = pci->dev;
        struct device_node *np = dev->of_node;
+       const struct pci_epc_features *epc_features;
 
        if (!pci->dbi_base || !pci->dbi_base2) {
                dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
@@ -563,13 +597,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
        if (ep->ops->ep_init)
                ep->ops->ep_init(ep);
 
-       hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
-       if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
-               dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
-                       hdr_type);
-               return -EIO;
-       }
-
        ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
        if (ret < 0)
                epc->max_functions = 1;
@@ -587,23 +614,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
                dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
                return -ENOMEM;
        }
-       ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
 
-       ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
-
-       offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
-       if (offset) {
-               reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
-               nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
-                       PCI_REBAR_CTRL_NBAR_SHIFT;
-
-               dw_pcie_dbi_ro_wr_en(pci);
-               for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
-                       dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
-               dw_pcie_dbi_ro_wr_dis(pci);
+       if (ep->ops->get_features) {
+               epc_features = ep->ops->get_features(ep);
+               if (epc_features->core_init_notifier)
+                       return 0;
        }
 
-       dw_pcie_setup(pci);
-
-       return 0;
+       return dw_pcie_ep_init_complete(ep);
 }