PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address

[sfrench/cifs-2.6.git] / drivers / pci / controller / dwc / pcie-designware-ep.c

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index b48c70e8c7c9a6820e9c2b77c6db7771567e865a..1cdcbd102ce86830a424bd790bd653717b3eb578 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -134,6 +134,7 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
 
        dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
        clear_bit(atu_index, ep->ib_window_map);
+       ep->epf_bar[bar] = NULL;
 }
 
 static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
@@ -167,6 +168,7 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
                dw_pcie_writel_dbi(pci, reg + 4, 0);
        }
 
+       ep->epf_bar[bar] = epf_bar;
        dw_pcie_dbi_ro_wr_dis(pci);
 
        return 0;
@@ -429,55 +431,41 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
                             u16 interrupt_num)
 {
        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+       struct pci_epf_msix_tbl *msix_tbl;
        struct pci_epc *epc = ep->epc;
-       u16 tbl_offset, bir;
-       u32 bar_addr_upper, bar_addr_lower;
-       u32 msg_addr_upper, msg_addr_lower;
+       struct pci_epf_bar *epf_bar;
        u32 reg, msg_data, vec_ctrl;
-       u64 tbl_addr, msg_addr, reg_u64;
-       void __iomem *msix_tbl;
+       unsigned int aligned_offset;
+       u32 tbl_offset;
+       u64 msg_addr;
        int ret;
+       u8 bir;
 
        reg = ep->msix_cap + PCI_MSIX_TABLE;
        tbl_offset = dw_pcie_readl_dbi(pci, reg);
        bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
        tbl_offset &= PCI_MSIX_TABLE_OFFSET;
 
-       reg = PCI_BASE_ADDRESS_0 + (4 * bir);
-       bar_addr_upper = 0;
-       bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
-       reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
-       if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
-               bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
+       epf_bar = ep->epf_bar[bir];
+       msix_tbl = epf_bar->addr;
+       msix_tbl = (struct pci_epf_msix_tbl *)((char *)msix_tbl + tbl_offset);
 
-       tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
-       tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
-       tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
-
-       msix_tbl = ioremap(ep->phys_base + tbl_addr,
-                                  PCI_MSIX_ENTRY_SIZE);
-       if (!msix_tbl)
-               return -EINVAL;
-
-       msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
-       msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
-       msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
-       msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
-       vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
-
-       iounmap(msix_tbl);
+       msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;
+       msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
+       vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl;
 
        if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) {
                dev_dbg(pci->dev, "MSI-X entry ctrl set\n");
                return -EPERM;
        }
 
-       ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
+       aligned_offset = msg_addr & (epc->mem->page_size - 1);
+       ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,  msg_addr,
                                  epc->mem->page_size);
        if (ret)
                return ret;
 
-       writel(msg_data, ep->msi_mem);
+       writel(msg_data, ep->msi_mem + aligned_offset);
 
        dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);