Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma

[sfrench/cifs-2.6.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.h

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 35c61da7ba156be04bb76d7cb041cc99eba0161b..12be85f0986ea6d726dd4110139eae7b14bd0d49 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -35,26 +35,15 @@
 
 #include <linux/bitops.h>
 
-#define HNS_ROCE_VF_QPC_BT_NUM                 256
-#define HNS_ROCE_VF_SCCC_BT_NUM                        64
-#define HNS_ROCE_VF_SRQC_BT_NUM                        64
-#define HNS_ROCE_VF_CQC_BT_NUM                 64
-#define HNS_ROCE_VF_MPT_BT_NUM                 64
-#define HNS_ROCE_VF_SMAC_NUM                   32
-#define HNS_ROCE_VF_SL_NUM                     8
-#define HNS_ROCE_VF_GMV_BT_NUM                 256
-
 #define HNS_ROCE_V2_MAX_QP_NUM                 0x1000
 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM          0x200
 #define HNS_ROCE_V2_MAX_WQE_NUM                        0x8000
-#define        HNS_ROCE_V2_MAX_SRQ                     0x100000
 #define HNS_ROCE_V2_MAX_SRQ_WR                 0x8000
 #define HNS_ROCE_V2_MAX_SRQ_SGE                        64
 #define HNS_ROCE_V2_MAX_CQ_NUM                 0x100000
 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM          0x100
 #define HNS_ROCE_V2_MAX_SRQ_NUM                        0x100000
 #define HNS_ROCE_V2_MAX_CQE_NUM                        0x400000
-#define HNS_ROCE_V2_MAX_SRQWQE_NUM             0x8000
 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM             64
 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM             64
 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM         0x200000
@@ -63,13 +52,10 @@
 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ          32
 #define HNS_ROCE_V2_UAR_NUM                    256
 #define HNS_ROCE_V2_PHY_UAR_NUM                        1
-#define HNS_ROCE_V2_MAX_IRQ_NUM                        65
-#define HNS_ROCE_V2_COMP_VEC_NUM               63
 #define HNS_ROCE_V2_AEQE_VEC_NUM               1
 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM           1
 #define HNS_ROCE_V2_MAX_MTPT_NUM               0x100000
 #define HNS_ROCE_V2_MAX_MTT_SEGS               0x1000000
-#define HNS_ROCE_V2_MAX_CQE_SEGS               0x1000000
 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS            0x1000000
 #define HNS_ROCE_V2_MAX_IDX_SEGS               0x1000000
 #define HNS_ROCE_V2_MAX_PD_NUM                 0x1000000
@@ -81,7 +67,6 @@
 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ             16
 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ            64
 #define HNS_ROCE_V2_IRRL_ENTRY_SZ              64
-#define HNS_ROCE_V2_TRRL_ENTRY_SZ              48
 #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ   100
 #define HNS_ROCE_V2_CQC_ENTRY_SZ               64
 #define HNS_ROCE_V2_SRQC_ENTRY_SZ              64
@@ -103,7 +88,6 @@
 #define HNS_ROCE_INVALID_LKEY                  0x0
 #define HNS_ROCE_INVALID_SGE_LENGTH            0x80000000
 #define HNS_ROCE_CMQ_TX_TIMEOUT                        30000
-#define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE       2
 #define HNS_ROCE_V2_RSV_QPS                    8
 
 #define HNS_ROCE_V2_HW_RST_TIMEOUT             1000
@@ -117,12 +101,14 @@
 #define HNS_ROCE_CQE_HOP_NUM                   1
 #define HNS_ROCE_SRQWQE_HOP_NUM                        1
 #define HNS_ROCE_PBL_HOP_NUM                   2
-#define HNS_ROCE_EQE_HOP_NUM                   2
 #define HNS_ROCE_IDX_HOP_NUM                   1
 #define HNS_ROCE_SQWQE_HOP_NUM                 2
 #define HNS_ROCE_EXT_SGE_HOP_NUM               1
 #define HNS_ROCE_RQWQE_HOP_NUM                 2
 
+#define HNS_ROCE_V2_EQE_HOP_NUM                        2
+#define HNS_ROCE_V3_EQE_HOP_NUM                        1
+
 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K       6
 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K                2
 #define HNS_ROCE_V2_GID_INDEX_NUM              16
@@ -1441,7 +1427,7 @@ struct hns_roce_v2_priv {
 struct hns_roce_dip {
        u8 dgid[GID_LEN_V2];
        u32 dip_idx;
-       struct list_head node;  /* all dips are on a list */
+       struct list_head node; /* all dips are on a list */
 };
 
 /* only for RNR timeout issue of HIP08 */