drm/radeon: handle PCIe root ports with addressing limitations

[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index dceb554e567446354f976cc39efcd1c012c443c2..b8cc058266672144d36f7330a9ba79f66cebc83c 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1365,27 +1365,25 @@ int radeon_device_init(struct radeon_device *rdev,
        else
                rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
 
-       /* set DMA mask + need_dma32 flags.
+       /* set DMA mask.
         * PCIE - can handle 40-bits.
         * IGP - can handle 40-bits
         * AGP - generally dma32 is safest
         * PCI - dma32 for legacy pci gart, 40 bits on newer asics
         */
-       rdev->need_dma32 = false;
+       dma_bits = 40;
        if (rdev->flags & RADEON_IS_AGP)
-               rdev->need_dma32 = true;
+               dma_bits = 32;
        if ((rdev->flags & RADEON_IS_PCI) &&
            (rdev->family <= CHIP_RS740))
-               rdev->need_dma32 = true;
+               dma_bits = 32;
 #ifdef CONFIG_PPC64
        if (rdev->family == CHIP_CEDAR)
-               rdev->need_dma32 = true;
+               dma_bits = 32;
 #endif
 
-       dma_bits = rdev->need_dma32 ? 32 : 40;
        r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
        if (r) {
-               rdev->need_dma32 = true;
                dma_bits = 32;
                pr_warn("radeon: No suitable DMA available\n");
        }