drm/radeon: fix indentation.

[sfrench/cifs-2.6.git] / drivers / gpu / drm / radeon / r600_cs.c

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 2f36fa1576e03dc704bfbbb00f3acb2cb523c55a..b69c8de35bd315b56e13986bd2f4447ae422d50e 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -1671,8 +1671,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                }
 
                offset = reloc->gpu_offset +
-                        (idx_value & 0xfffffff0) +
-                        ((u64)(tmp & 0xff) << 32);
+                        (idx_value & 0xfffffff0) +
+                        ((u64)(tmp & 0xff) << 32);
 
                ib[idx + 0] = offset;
                ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
@@ -1712,8 +1712,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                }
 
                offset = reloc->gpu_offset +
-                        idx_value +
-                        ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
+                        idx_value +
+                        ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
 
                ib[idx+0] = offset;
                ib[idx+1] = upper_32_bits(offset) & 0xff;
@@ -1764,8 +1764,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        }
 
                        offset = reloc->gpu_offset +
-                                (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
-                                ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
+                                (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
+                                ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
                        ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
                        ib[idx+2] = upper_32_bits(offset) & 0xff;
@@ -1876,8 +1876,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                return -EINVAL;
                        }
                        offset = reloc->gpu_offset +
-                                (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
-                                ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
+                                (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
+                                ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
                        ib[idx+1] = offset & 0xfffffff8;
                        ib[idx+2] = upper_32_bits(offset) & 0xff;
@@ -1898,8 +1898,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                }
 
                offset = reloc->gpu_offset +
-                        (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
-                        ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
+                        (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
+                        ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
 
                ib[idx+1] = offset & 0xfffffffc;
                ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);