Merge tag 'drm-next-2021-02-26' of git://anongit.freedesktop.org/drm/drm

[sfrench/cifs-2.6.git] / drivers / gpu / drm / msm / dsi / pll / dsi_pll_10nm.c

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index e4e9bf04b73687a48d239bb26c54ccf2d7e65a52..de3b802ccd3d75a4795258301c92abc656fa865b 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -172,9 +172,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll)
 
        multiplier = 1 << config->frac_bits;
        dec_multiple = div_u64(pll_freq * multiplier, divider);
-       div_u64_rem(dec_multiple, multiplier, &frac);
-
-       dec = div_u64(dec_multiple, multiplier);
+       dec = div_u64_rem(dec_multiple, multiplier, &frac);
 
        if (pll_freq <= 1900000000UL)
                regs->pll_prop_gain_rate = 8;
@@ -306,7 +304,8 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll)
                  reg->frac_div_start_mid);
        pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
                  reg->frac_div_start_high);
-       pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
+       pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
+                 reg->pll_lockdet_rate);
        pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
        pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
        pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
@@ -345,6 +344,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 
 static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
 {
+       struct device *dev = &pll->pdev->dev;
        int rc;
        u32 status = 0;
        u32 const delay_us = 100;
@@ -357,8 +357,8 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
                                       delay_us,
                                       timeout_us);
        if (rc)
-               pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
-                      pll->id, status);
+               DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n",
+                             pll->id, status);
 
        return rc;
 }
@@ -405,6 +405,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
 {
        struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
        struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+       struct device *dev = &pll_10nm->pdev->dev;
        int rc;
 
        dsi_pll_enable_pll_bias(pll_10nm);
@@ -413,7 +414,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
 
        rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
        if (rc) {
-               pr_err("vco_set_rate failed, rc=%d\n", rc);
+               DRM_DEV_ERROR(dev, "vco_set_rate failed, rc=%d\n", rc);
                return rc;
        }
 
@@ -430,7 +431,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
        /* Check for PLL lock */
        rc = dsi_pll_10nm_lock_status(pll_10nm);
        if (rc) {
-               pr_err("PLL(%d) lock failed\n", pll_10nm->id);
+               DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->id);
                goto error;
        }
 
@@ -483,6 +484,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
 {
        struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
        struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+       struct dsi_pll_config *config = &pll_10nm->pll_configuration;
        void __iomem *base = pll_10nm->mmio;
        u64 ref_clk = pll_10nm->vco_ref_clk_rate;
        u64 vco_rate = 0x0;
@@ -503,9 +505,8 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
        /*
         * TODO:
         *      1. Assumes prescaler is disabled
-        *      2. Multiplier is 2^18. it should be 2^(num_of_frac_bits)
         */
-       multiplier = 1 << 18;
+       multiplier = 1 << config->frac_bits;
        pll_freq = dec * (ref_clk * 2);
        tmp64 = (ref_clk * 2 * frac);
        pll_freq += div_u64(tmp64, multiplier);