Merge tag 'drm-msm-fixes-2022-06-28' into msm-next-staging

[sfrench/cifs-2.6.git] / drivers / gpu / drm / msm / dp / dp_ctrl.c

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index b7f5b8d3bbd6138bed6903bc3d3ae9974ee0911f..703249384e7c7d0b000b2b51f89c45791ab6684e 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1534,6 +1534,8 @@ end:
        return ret;
 }
 
+static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl);
+
 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
 {
        int ret = 0;
@@ -1557,7 +1559,7 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
 
        ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
        if (!ret)
-               ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
+               ret = dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl);
        else
                DRM_ERROR("failed to enable DP link controller\n");
 
@@ -1813,7 +1815,27 @@ static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
        return dp_ctrl_setup_main_link(ctrl, &training_step);
 }
 
-int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
+static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl)
+{
+       int ret;
+       struct dp_ctrl_private *ctrl;
+
+       ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+       ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
+
+       ret = dp_ctrl_enable_stream_clocks(ctrl);
+       if (ret) {
+               DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
+               return ret;
+       }
+
+       dp_ctrl_send_phy_test_pattern(ctrl);
+
+       return 0;
+}
+
+int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
 {
        int ret = 0;
        bool mainlink_ready = false;
@@ -1849,12 +1871,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
                goto end;
        }
 
-       if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
-               dp_ctrl_send_phy_test_pattern(ctrl);
-               return 0;
-       }
-
-       if (!dp_ctrl_channel_eq_ok(ctrl))
+       if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))
                dp_ctrl_link_retrain(ctrl);
 
        /* stop txing train pattern to end link training */