Merge drm/drm-next into drm-misc-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / msm / disp / dpu1 / dpu_hw_interrupts.h

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index d6a17f052b3a62de583565a6253faa4af398fad0..50cf9523d367ffe0c8a4fc2c6f492e95b5eef847 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -17,30 +17,25 @@ enum dpu_hw_intr_reg {
        MDP_SSPP_TOP0_INTR,
        MDP_SSPP_TOP0_INTR2,
        MDP_SSPP_TOP0_HIST_INTR,
+       /* All MDP_INTFn_INTR should come sequentially */
        MDP_INTF0_INTR,
        MDP_INTF1_INTR,
        MDP_INTF2_INTR,
        MDP_INTF3_INTR,
        MDP_INTF4_INTR,
        MDP_INTF5_INTR,
+       MDP_INTF6_INTR,
+       MDP_INTF7_INTR,
+       MDP_INTF8_INTR,
        MDP_INTF1_TEAR_INTR,
        MDP_INTF2_TEAR_INTR,
        MDP_AD4_0_INTR,
        MDP_AD4_1_INTR,
-       MDP_INTF0_7xxx_INTR,
-       MDP_INTF1_7xxx_INTR,
-       MDP_INTF1_7xxx_TEAR_INTR,
-       MDP_INTF2_7xxx_INTR,
-       MDP_INTF2_7xxx_TEAR_INTR,
-       MDP_INTF3_7xxx_INTR,
-       MDP_INTF4_7xxx_INTR,
-       MDP_INTF5_7xxx_INTR,
-       MDP_INTF6_7xxx_INTR,
-       MDP_INTF7_7xxx_INTR,
-       MDP_INTF8_7xxx_INTR,
        MDP_INTR_MAX,
 };
 
+#define MDP_INTFn_INTR(intf)   (MDP_INTF0_INTR + (intf - INTF_0))
+
 #define DPU_IRQ_IDX(reg_idx, offset)   (reg_idx * 32 + offset)
 
 /**
@@ -60,6 +55,7 @@ struct dpu_hw_intr {
        u32 total_irqs;
        spinlock_t irq_lock;
        unsigned long irq_mask;
+       const struct dpu_intr_reg *intr_set;
 
        struct {
                void (*cb)(void *arg, int irq_idx);