drm/meson: Add G12A support for OSD1 Plane
[sfrench/cifs-2.6.git] / drivers / gpu / drm / meson / meson_plane.c
index b7786218cb10ae17f0226e13eda3923d73d2d2b1..bf8f1fab63aa9f558437933bd61eebee16a1f7e9 100644 (file)
@@ -294,6 +294,13 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
        priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
        priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
 
+       if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
+               priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
+               priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
+               priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
+               priv->viu.osb_blend1_size = dst_h << 16 | dst_w;
+       }
+
        /* Update Canvas with buffer address */
        gem = drm_fb_cma_get_gem_obj(fb, 0);
 
@@ -320,8 +327,12 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
        struct meson_drm *priv = meson_plane->priv;
 
        /* Disable OSD1 */
-       writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
-                           priv->io_base + _REG(VPP_MISC));
+       if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
+               writel_bits_relaxed(BIT(0) | BIT(21), 0,
+                       priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
+       else
+               writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
+                                   priv->io_base + _REG(VPP_MISC));
 
        meson_plane->enabled = false;