drm/i915/guc: Implement GuC priority management

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_trace.h

diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 9613a7c19661f3467b74d7320cca1a37dc585c06..806ad688274bf61a601d1923f4fd569f34bdb636 100644 (file)
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -904,6 +904,7 @@ DECLARE_EVENT_CLASS(intel_context,
                             __field(int, pin_count)
                             __field(u32, sched_state)
                             __field(u32, guc_sched_state_no_lock)
+                            __field(u8, guc_prio)
                             ),
 
                    TP_fast_assign(
@@ -912,12 +913,19 @@ DECLARE_EVENT_CLASS(intel_context,
                           __entry->sched_state = ce->guc_state.sched_state;
                           __entry->guc_sched_state_no_lock =
                           atomic_read(&ce->guc_sched_state_no_lock);
+                          __entry->guc_prio = ce->guc_prio;
                           ),
 
-                   TP_printk("guc_id=%d, pin_count=%d sched_state=0x%x,0x%x",
+                   TP_printk("guc_id=%d, pin_count=%d sched_state=0x%x,0x%x, guc_prio=%u",
                              __entry->guc_id, __entry->pin_count,
                              __entry->sched_state,
-                             __entry->guc_sched_state_no_lock)
+                             __entry->guc_sched_state_no_lock,
+                             __entry->guc_prio)
+);
+
+DEFINE_EVENT(intel_context, intel_context_set_prio,
+            TP_PROTO(struct intel_context *ce),
+            TP_ARGS(ce)
 );
 
 DEFINE_EVENT(intel_context, intel_context_reset,
@@ -1017,6 +1025,11 @@ trace_i915_request_out(struct i915_request *rq)
 {
 }
 
+static inline void
+trace_intel_context_set_prio(struct intel_context *ce)
+{
+}
+
 static inline void
 trace_intel_context_reset(struct intel_context *ce)
 {