Merge drm/drm-next into drm-intel-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d1b0022f4b7b79a3689c516e2bc6dcac28cbc1b..bf5c39d9f953072b66bfa485732644efa0ad6304 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -975,6 +975,18 @@
 #define GEN12_COMPUTE2_RING_BASE       0x1e000
 #define GEN12_COMPUTE3_RING_BASE       0x26000
 #define BLT_RING_BASE          0x22000
+#define XEHPC_BCS1_RING_BASE   0x3e0000
+#define XEHPC_BCS2_RING_BASE   0x3e2000
+#define XEHPC_BCS3_RING_BASE   0x3e4000
+#define XEHPC_BCS4_RING_BASE   0x3e6000
+#define XEHPC_BCS5_RING_BASE   0x3e8000
+#define XEHPC_BCS6_RING_BASE   0x3ea000
+#define XEHPC_BCS7_RING_BASE   0x3ec000
+#define XEHPC_BCS8_RING_BASE   0x3ee000
+#define DG1_GSC_HECI1_BASE     0x00258000
+#define DG1_GSC_HECI2_BASE     0x00259000
+#define DG2_GSC_HECI1_BASE     0x00373000
+#define DG2_GSC_HECI2_BASE     0x00374000
 
 
 
@@ -1841,6 +1853,18 @@
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
 #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
 #define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
+#define PVC_RP_STATE_CAP       _MMIO(0x281014)
+
+#define GT0_PERF_LIMIT_REASONS         _MMIO(0x1381a8)
+#define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
+#define   PROCHOT_MASK                 REG_BIT(1)
+#define   THERMAL_LIMIT_MASK           REG_BIT(2)
+#define   RATL_MASK                    REG_BIT(6)
+#define   VR_THERMALERT_MASK           REG_BIT(7)
+#define   VR_TDC_MASK                  REG_BIT(8)
+#define   POWER_LIMIT_4_MASK           REG_BIT(9)
+#define   POWER_LIMIT_1_MASK           REG_BIT(11)
+#define   POWER_LIMIT_2_MASK           REG_BIT(12)
 
 #define CHV_CLK_CTL1                   _MMIO(0x101100)
 #define VLV_CLK_CTL2                   _MMIO(0x101104)
@@ -6749,6 +6773,14 @@
 #define     DG1_UNCORE_GET_INIT_STATUS         0x0
 #define     DG1_UNCORE_INIT_STATUS_COMPLETE    0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US    0x23
+#define   XEHP_PCODE_FREQUENCY_CONFIG          0x6e    /* xehpsdv, pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define     PCODE_MBOX_FC_SC_READ_FUSED_P0     0x0
+#define     PCODE_MBOX_FC_SC_READ_FUSED_PN     0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define     PCODE_MBOX_DOMAIN_NONE             0x0
+#define     PCODE_MBOX_DOMAIN_MEDIAFF          0x3
 #define GEN6_PCODE_DATA                                _MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT       8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT     16
@@ -8319,20 +8351,6 @@ enum skl_power_gate {
 #define   SGGI_DIS                     REG_BIT(15)
 #define   SGR_DIS                      REG_BIT(13)
 
-#define XEHPSDV_FLAT_CCS_BASE_ADDR     _MMIO(0x4910)
-#define   XEHPSDV_CCS_BASE_SHIFT       8
-
-/* gamt regs */
-#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
-#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
-#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
-#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
-#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
-
-#define MMCD_MISC_CTRL         _MMIO(0x4ddc) /* skl+ */
-#define  MMCD_PCLA             (1 << 31)
-#define  MMCD_HOTSPOT_EN       (1 << 27)
-
 #define _ICL_PHY_MISC_A                0x64C00
 #define _ICL_PHY_MISC_B                0x64C04
 #define _DG2_PHY_MISC_TC1      0x64C14 /* TC1="PHY E" but offset as if "PHY F" */