drm/i915: Remove memory frequency calculation

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c8152de643f1d6ff8e116b1272dc12d8c9541a4..da9055c3ebf0f90cfeaea3d5edfbac059a1532f1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11106,12 +11106,6 @@ enum skl_power_gate {
 #define  DC_STATE_DEBUG_MASK_CORES     (1 << 0)
 #define  DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
 
-#define BXT_P_CR_MC_BIOS_REQ_0_0_0     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
-#define  BXT_REQ_DATA_MASK                     0x3F
-#define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT         12
-#define  BXT_DRAM_CHANNEL_ACTIVE_MASK          (0xF << 12)
-#define  BXT_MEMORY_FREQ_MULTIPLIER_HZ         133333333
-
 #define BXT_D_CR_DRP0_DUNIT8                   0x1000
 #define BXT_D_CR_DRP0_DUNIT9                   0x1200
 #define  BXT_D_CR_DRP0_DUNIT_START             8
@@ -11142,9 +11136,7 @@ enum skl_power_gate {
 #define  BXT_DRAM_TYPE_LPDDR4                  (0x2 << 22)
 #define  BXT_DRAM_TYPE_DDR4                    (0x4 << 22)
 
-#define SKL_MEMORY_FREQ_MULTIPLIER_HZ          266666666
 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
-#define  SKL_REQ_DATA_MASK                     (0xF << 0)
 #define  DG1_GEAR_TYPE                         REG_BIT(16)
 
 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)