drm/i915/display/adlp: Add new PSR2 workarounds

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd63760207b0ac44c77e7eab9e40d3706bbebd95..67351ed5ab5b97b37ccacd734c28924783b0ddaf 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8205,6 +8205,7 @@ enum {
 #define  VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
 #define  FECSTALL_DIS_DPTSTREAM_DPTTG  REG_BIT(23)
 #define  DDI_TRAINING_OVERRIDE_ENABLE  REG_BIT(19)
+#define  ADLP_1_BASED_X_GRANULARITY    REG_BIT(18)
 #define  DDI_TRAINING_OVERRIDE_VALUE   REG_BIT(18)
 #define  DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
 #define  DDIE_TRAINING_OVERRIDE_VALUE  REG_BIT(16) /* CHICKEN_TRANS_A only */
@@ -12759,4 +12760,7 @@ enum skl_power_gate {
 #define CLKREQ_POLICY                  _MMIO(0x101038)
 #define  CLKREQ_POLICY_MEM_UP_OVRD     REG_BIT(1)
 
+#define CLKGATE_DIS_MISC                       _MMIO(0x46534)
+#define  CLKGATE_DIS_MISC_DMASC_GATING_DIS     REG_BIT(21)
+
 #endif /* _I915_REG_H_ */