drm/i915/pxp: black pixels on pxp disabled

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4be684b0fcd4de6d563edb03651ad6e3782dd244..47bfffe0b4de3ff81b76c7b77e20ca5fac3a298a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7260,6 +7260,7 @@ enum {
 #define _PLANE_COLOR_CTL_3_A                   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE                (1 << 30) /* Pre-ICL */
 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE     (1 << 28)
+#define   PLANE_COLOR_PLANE_CSC_ENABLE                 REG_BIT(21) /* ICL+ */
 #define   PLANE_COLOR_INPUT_CSC_ENABLE         (1 << 20) /* ICL+ */
 #define   PLANE_COLOR_PIPE_CSC_ENABLE          (1 << 23) /* Pre-ICL */
 #define   PLANE_COLOR_CSC_MODE_BYPASS                  (0 << 17)
@@ -11377,6 +11378,51 @@ enum skl_power_gate {
                                        _PAL_PREC_MULTI_SEG_DATA_A, \
                                        _PAL_PREC_MULTI_SEG_DATA_B)
 
+#define _MMIO_PLANE_GAMC(plane, i, a, b)  _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A   0x70210
+#define _PLANE_CSC_RY_GY_2_A   0x70310
+
+#define _PLANE_CSC_RY_GY_1_B   0x71210
+#define _PLANE_CSC_RY_GY_2_B   0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe)       _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+                                             _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe)       _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+                                             _PLANE_INPUT_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index)    _MMIO_PLANE(plane, \
+                                                           _PLANE_CSC_RY_GY_1(pipe) +  (index) * 4, \
+                                                           _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A               0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A               0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B               0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B               0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe)   _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+                                             _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe)   _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+                                             _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index)   _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+                                                           (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+                                                           (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A              0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A              0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B              0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B              0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe)  _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+                                             _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe)  _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+                                             _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index)  _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+                                                           (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+                                                           (index) * 4)
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01        (VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23        (VLV_DISPLAY_BASE + 0x67904)