drm/i915/fbc: Align FBC segments to 512B on glk+

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 61d29068925c469481ea2cef0cee3692db95d01a..24017d38c6f60e18b8e11710f03e3fe7dda49388 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3360,6 +3360,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
 #define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL    (1 << 14)
 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION    (1 << 23)
+#define GLK_FBC_STRIDE         _MMIO(0x43228)
+#define   FBC_STRIDE_OVERRIDE  REG_BIT(15)
+#define   FBC_STRIDE_MASK      REG_GENMASK(14, 0)
+#define   FBC_STRIDE(x)                REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
 #define ILK_FBC_RT_BASE                _MMIO(0x2128)
 #define   ILK_FBC_RT_VALID     (1 << 0)
 #define   SNB_FBC_FRONT_BUFFER (1 << 1)