Merge drm/drm-next into drm-intel-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 05b84196216c43c90149e14729ff1c40fcebc5b6..360743a8a1636a44b037a1fbb925fcc8ebb7a1c5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -63,7 +63,6 @@
 #include "intel_runtime_pm.h"
 #include "intel_step.h"
 #include "intel_uncore.h"
-#include "intel_wopcm.h"
 
 struct drm_i915_clock_gating_funcs;
 struct drm_i915_gem_object;
@@ -236,8 +235,6 @@ struct drm_i915_private {
 
        struct intel_gvt *gvt;
 
-       struct intel_wopcm wopcm;
-
        struct pci_dev *bridge_dev;
 
        struct rb_root uabi_engines;
@@ -727,6 +724,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
        (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
+#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+       (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
+        IS_GRAPHICS_STEP(__i915, since, until))
+
 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
        (IS_METEORLAKE(__i915) && \
         IS_DISPLAY_STEP(__i915, since, until))
@@ -769,12 +770,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
 
-#define ENGINE_INSTANCES_MASK(gt, first, count) ({             \
+#define __ENGINE_INSTANCES_MASK(mask, first, count) ({                 \
        unsigned int first__ = (first);                                 \
        unsigned int count__ = (count);                                 \
-       ((gt)->info.engine_mask &                                               \
-        GENMASK(first__ + count__ - 1, first__)) >> first__;           \
+       ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__;  \
 })
+
+#define ENGINE_INSTANCES_MASK(gt, first, count) \
+       __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
+
 #define RCS_MASK(gt) \
        ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 #define BCS_MASK(gt) \