drm/i915/gvt: Initialize intel_gvt_gtt_entry in stack

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / gtt.c

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 244ad17297646be945d55218ddcadef799de335b..f3a75bb9ec276c983d3f49b8a4dbc291d2410e5e 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2183,7 +2183,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
        struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
        unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
        unsigned long gma, gfn;
-       struct intel_gvt_gtt_entry e, m;
+       struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
+       struct intel_gvt_gtt_entry m = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
        dma_addr_t dma_addr;
        int ret;
        struct intel_gvt_partial_pte *partial_pte, *pos, *n;
@@ -2250,7 +2251,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
 
        if (!partial_update && (ops->test_present(&e))) {
                gfn = ops->get_pfn(&e);
-               m = e;
+               m.val64 = e.val64;
+               m.type = e.type;
 
                /* one PTE update may be issued in multiple writes and the
                 * first write may not construct a valid gfn