Merge tag 'gvt-next-2020-03-10' of https://github.com/intel/gvt-linux into drm-intel...

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / gtt.c

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 25bd5c052909675b00fa44fc24c6d3d80100de45..2a4b23f8aa740e7b6a17d2650509e8ae34456aa2 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -71,7 +71,7 @@ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
 /* translate a guest gmadr to host gmadr */
 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
 {
-       struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+       struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
 
        if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),
                     "invalid guest gmadr %llx\n", g_addr))
@@ -89,7 +89,7 @@ int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
 /* translate a host gmadr to guest gmadr */
 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
 {
-       struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+       struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
 
        if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
                     "invalid host gmadr %llx\n", h_addr))
@@ -279,24 +279,23 @@ static inline int get_pse_type(int type)
        return gtt_type_table[type].pse_entry_type;
 }
 
-static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
+static u64 read_pte64(struct i915_ggtt *ggtt, unsigned long index)
 {
-       void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
+       void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
 
        return readq(addr);
 }
 
-static void ggtt_invalidate(struct drm_i915_private *dev_priv)
+static void ggtt_invalidate(struct intel_gt *gt)
 {
-       mmio_hw_access_pre(dev_priv);
-       I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
-       mmio_hw_access_post(dev_priv);
+       mmio_hw_access_pre(gt);
+       intel_uncore_write(gt->uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+       mmio_hw_access_post(gt);
 }
 
-static void write_pte64(struct drm_i915_private *dev_priv,
-               unsigned long index, u64 pte)
+static void write_pte64(struct i915_ggtt *ggtt, unsigned long index, u64 pte)
 {
-       void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
+       void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
 
        writeq(pte, addr);
 }
@@ -319,7 +318,7 @@ static inline int gtt_get_entry64(void *pt,
                if (WARN_ON(ret))
                        return ret;
        } else if (!pt) {
-               e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
+               e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index);
        } else {
                e->val64 = *((u64 *)pt + index);
        }
@@ -344,7 +343,7 @@ static inline int gtt_set_entry64(void *pt,
                if (WARN_ON(ret))
                        return ret;
        } else if (!pt) {
-               write_pte64(vgpu->gvt->dev_priv, index, e->val64);
+               write_pte64(vgpu->gvt->gt->ggtt, index, e->val64);
        } else {
                *((u64 *)pt + index) = e->val64;
        }
@@ -738,7 +737,7 @@ static int detach_oos_page(struct intel_vgpu *vgpu,
 
 static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
 {
-       struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
+       struct device *kdev = &spt->vgpu->gvt->gt->i915->drm.pdev->dev;
 
        trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
 
@@ -823,7 +822,7 @@ static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
                struct intel_vgpu *vgpu, enum intel_gvt_gtt_type type)
 {
-       struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
+       struct device *kdev = &vgpu->gvt->gt->i915->drm.pdev->dev;
        struct intel_vgpu_ppgtt_spt *spt = NULL;
        dma_addr_t daddr;
        int ret;
@@ -944,7 +943,7 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
 static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
                struct intel_gvt_gtt_entry *e)
 {
-       struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+       struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
        struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
        struct intel_vgpu_ppgtt_spt *s;
        enum intel_gvt_gtt_type cur_pt_type;
@@ -1051,7 +1050,7 @@ fail:
 
 static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
 {
-       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+       struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 
        if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
                u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
@@ -1160,7 +1159,7 @@ static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
        struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
        unsigned long pfn;
 
-       if (!HAS_PAGE_SIZES(vgpu->gvt->dev_priv, I915_GTT_PAGE_SIZE_2M))
+       if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
                return 0;
 
        pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, ops->get_pfn(entry));
@@ -2321,7 +2320,7 @@ out:
        ggtt_invalidate_pte(vgpu, &e);
 
        ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
-       ggtt_invalidate(gvt->dev_priv);
+       ggtt_invalidate(gvt->gt);
        return 0;
 }
 
@@ -2354,14 +2353,14 @@ int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
 static int alloc_scratch_pages(struct intel_vgpu *vgpu,
                enum intel_gvt_gtt_type type)
 {
-       struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
+       struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
        struct intel_vgpu_gtt *gtt = &vgpu->gtt;
        struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
        int page_entry_num = I915_GTT_PAGE_SIZE >>
                                vgpu->gvt->device_info.gtt_entry_size_shift;
        void *scratch_pt;
        int i;
-       struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
+       struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev;
        dma_addr_t daddr;
 
        if (drm_WARN_ON(&i915->drm,
@@ -2419,7 +2418,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
 static int release_scratch_page_tree(struct intel_vgpu *vgpu)
 {
        int i;
-       struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
+       struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev;
        dma_addr_t daddr;
 
        for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
@@ -2691,7 +2690,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
 {
        int ret;
        void *page;
-       struct device *dev = &gvt->dev_priv->drm.pdev->dev;
+       struct device *dev = &gvt->gt->i915->drm.pdev->dev;
        dma_addr_t daddr;
 
        gvt_dbg_core("init gtt\n");
@@ -2740,7 +2739,7 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
  */
 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
 {
-       struct device *dev = &gvt->dev_priv->drm.pdev->dev;
+       struct device *dev = &gvt->gt->i915->drm.pdev->dev;
        dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
                                        I915_GTT_PAGE_SHIFT);
 
@@ -2788,7 +2787,6 @@ void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
 {
        struct intel_gvt *gvt = vgpu->gvt;
-       struct drm_i915_private *dev_priv = gvt->dev_priv;
        struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
        struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
        struct intel_gvt_gtt_entry old_entry;
@@ -2818,7 +2816,7 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
                ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
        }
 
-       ggtt_invalidate(dev_priv);
+       ggtt_invalidate(gvt->gt);
 }
 
 /**