Merge drm/drm-next into drm-intel-next

[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gt / intel_gt_regs.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fd1f9cd35e9d7a172124340902a242d4580d4e9e..c122eab3373880edeb07bf688155e5e832720990 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -7,7 +7,8 @@
 #define __INTEL_GT_REGS__
 
 #include "i915_reg_defs.h"
-#include "display/intel_display_reg_defs.h"    /* VLV_DISPLAY_BASE */
+
+#define VLV_GUNIT_BASE                 0x180000
 
 /*
  * The perf control registers are technically multicast registers, but the
@@ -1460,7 +1461,7 @@
 #define GEN12_RCU_MODE                         _MMIO(0x14800)
 #define   GEN12_RCU_MODE_CCS_ENABLE            REG_BIT(0)
 
-#define CHV_FUSE_GT                            _MMIO(VLV_DISPLAY_BASE + 0x2168)
+#define CHV_FUSE_GT                            _MMIO(VLV_GUNIT_BASE + 0x2168)
 #define   CHV_FGT_DISABLE_SS0                  (1 << 10)
 #define   CHV_FGT_DISABLE_SS1                  (1 << 11)
 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT          16